Datasheet CD4006BMS Datasheet (Intersil Corporation)

CD4006BMS

December 1992

Features

• High-Voltage Type (20V Rating)

• Fully Static Operation

• Shifting Rates Up to 12MHz at 10V (typ)

• Permanent Register Storage with Clock Line High or
Low - No Information Recirculation Required

• 100% Tested for Quiescent Current at 20V

• Standardized, Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full Pack­age-Temperature Range; 100nA at 18V and +25

• Noise Margin (Full Package-Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Stan­dards No. 13B, “Standard Specifications for Descrip­tion of “B” Series CMOS Devices”

CMOS 18-Stage Static Register

Pinout

CD4006BM

TOP VIEW

D1

1
2

D1 + 4’

D2
D3
D4

VSS

3
4
5
6
7

CLOCK

o

C

Functional Diagram

14
13
12
11
10

9
8

VDD
D1 + 4
D2 + 5
D2 + 4
D3 + 4
D4 + 5
D4 + 4

VDD

14

Applications

• Serial Shift Registers

• Frequency Division

• Time Delay Circuits

Description

CD4006BMS types are composed of 4 separate shift register
sections: two sections of four stages and two sections of five
stages with an output tap at the fourth stage. Each section has
an independent single-rail data path.

A common clock signal is used for all stages. Data are shifted
to the next stages on negative-going transitions of the clock.
Through appropriate connections of inputs and outputs, multi­ple register sections of 4, 5, 8, and 9 stages or single register
sections of 10, 12, 13, 14, 16, 17 and 18 stages can be imple­mented using one CD4006BMS package. Longer shift register
sections can be assembled by using more than one
CD4006BMS.

To facilitate cascading stages when clock rise and fall times are
slow, an optional output (D1 + 4’) that is delayed one-half clock­cycle, is provided (see Truth Table for Output from Term. 2).

The CD4006BMS is supplied in these 14 lead outline pack­ages:

Braze Seal DIP H4Q
Frit Seal DIP H6D
Ceramic Flatpack H4F

D1

D2

CLOCK

D3

D4

VSS

131

D1 + 4

2

D1 + 4’

12

D2 + 5

11

D2 + 4

10

D3 + 4

9

D4 + 5

8

D4 + 4

7

4

STAGE

LATCH

4

3

5

6

4

STAGE

4

STAGE

4

STAGE

1

STAGE

1

STAGE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

7-658

File Number

3290

Specifications CD4006BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65

o

C to +125oC

o

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA

VDD = 18V, VIN = VDD or GND 3 -55

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

(Note 2)
Input Voltage High

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

(Note 2)
Input Voltage Low

(Note 2)
Input Voltage High

(Note 2)

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs

Thermal Resistance . . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55
For TA = +100

o

C

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

o

C to +100oC (Package Type D, F, K). . . . . .500mW

o

C to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

ja

o

C/W 20oC/W

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

LIMITS

SUBGROUPS TEMPERATURE

o

2 +125

C - 1000 µA

o

C-10µA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

VOL <

VDD/2

VDD/2

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.

θ

jc

UNITSMIN MAX

V

7-659

Specifications CD4006BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)

Propagation Delay TPHL

TPLH

Transition Time TTHL

TTLH

Maximum Clock Input
Frequency

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. 55oC and +125oC limits guaranteed, 100% testing being implemented.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

FCL VDD = 5V 9 +25oC 2.5 - MHz

VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

VIN = VDD or GND 10, 11 +125oC, -55oC 1.85 - MHz

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 540 ns

10, 11 +125oC, -55oC - 270 ns

+125oC - 150 µA

+125oC - 300 µA

+125oC - 600 µA

-55oC

-55oC

-55oC

-55oC

-55oC 0.64 - mA

-55oC 1.6 - mA

-55oC 4.2 - mA

-55oC - -0.64 mA

-55oC - -2.0 mA

-55oC - -1.6 mA

-55oC - -4.2 mA

-55oC

-55oC

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

-50mV

4.95 - V

9.95 - V

-3V

+7 - V

7-660

Specifications CD4006BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Propagation Delay TPHL

TPLH

Transition Time TTHL

TTLH

Maximum Clock Input

FCL VDD = 10V 1, 2, 3 +25

Frequency
Minimum Data Setup

Time

VDD = 10V 1, 2, 3 +25oC - 200 ns
VDD = 15V 1, 2, 3 +25oC - 160 ns
VDD = 10V 1, 2, 3 +25oC - 100 ns

o

VDD = 15V 1, 2, 3 +25

C - 80 ns

o

C 5 - MHz

VDD = 15V 1, 2, 3 +25oC 7 - MHz

o

TS VDD = 5V 1, 2, 3 +25

VDD = 10V 1, 2, 3 +25

C - 100 ns

o

C - 50 ns

VDD = 15V 1, 2, 3 +25oC - 40 ns

Minimum Clock Pulse
Width

TW VDD = 5V 1, 2, 3 +25oC - 180 ns

VDD = 10V 1, 2, 3 +25oC - 80 ns
VDD = 15V 1, 2, 3 +25oC - 50 ns

Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

UNITSMIN MAX

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage

∆VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

Delta
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage

∆VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

VDD/2

Propagation Delay Time TPHL

VDD = 3V, VIN = VDD or GND
VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

TPLH

VOL <
VDD/2

ns

+25oC

Limit

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

V

7-661

Specifications CD4006BMS

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

CONFORMANCE GROUPS

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

METHOD GROUP A SUBGROUPS READ AND RECORD

TABLE 7. TOTAL DOSE IRRADIATION

MIL-STD-883

METHOD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

TEST READ AND RECORD

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V ± -0.5V

Static Burn-In 1
Note 1

Static Burn-In 2
Note 1

Dynamic Burn­In Note 1

Irradiation
Note 2

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V

2, 8 - 13 1, 3 - 7 14

2, 8 - 13 7 1, 3 - 6, 14

2 7 14 8 - 13 3 1, 4 - 6

2, 8 - 13 7 1, 3 - 6, 14

50kHz 25kHz

7-662

CD4006BMS

Logic Diagram and Truth Table

CL

p

D

TG

n

CL

CL

TG

CL

p

n

LOGIC DIAGRAM AND TRUTH TABLE (ONE REGISTER STAGE)

CLOCK

D1

CL

TG

CL

p

n

CL

p

TG

n

CL

Q

Q

DQ

CL

CL

D + 1

Q

OUT IF
4th OR 5th
STAGE

DQ

CL

CL

TRUTH TABEL FOR SHIFT REGISTER STAGE

D CL* D + 1

00
11

XNC

TRUTH TABLE FOR OUTPUT FROM TERM 2

D1 + 4 CL* D1 + 4’

00
11

XNC

1 = HIGH X = DON’T CARE
0 = LOW * = LEVEL CHANGE
NC= NO CHANGE

D1 + 4

DQ

CL

CL

D

CL

CL

LATCH

Q

CL

CL

D1 + 4’

D1 + 4

D2

D3

D4

LATCH

CL

CL

CL

CL TO 14 MORE STAGES

Q

D1 + 4

=

DQ

CL

CL

DQ

CL

CL

DQ

CL

CL

CL

p
n

CL

2 STAGES

2 STAGES

2 STAGES

CL

p
n

DQ

Q

CL

CL

D

Q

CL

CL

DQ

Q

CL

CL

D

CL

D

CL

CL

CL

Q

Q

D2 + 5

D2 + 4

D3 + 4

D4 + 5

D4 + 4

DETAILED LOGIC OF LATCH

CL Q

LOGIC DIAGRAM WITH DETAIL OF LATCH

7-663

Typical Performance Characteristics

CD4006BMS

AMBIENT TEMPERATURE (TA) = +25oC

30

25

20

15

10

5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

AMBIENT TEMPERATURE (TA) = +25oC

15.0

12.5

10.0

7.5

5.0

2.5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 2. MIMIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

0-5-10-15

0

-5

-10

-15

-20

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

0-5-10-15

0

-5

-10

-25

-15V

-30

FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

200

150

100

50

TRANSITION TIME (tTHL, tTLH) (ns)

0

0 40 60 80 10020

SUPPLY VOLTAGE (VDD) = 5V

10V
15V

LOAD CAPACITANCE (CL) (pF)

-15V

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

350

300

250

200

150

100

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

SUPPLY VOLTAGE (VDD) = 5V

10V

15V

50

0

0 40 60 80 10020

LOAD CAPACITANCE (CL) (pF)

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 5. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

7-664

CD4006BMS

Typical Performance Characteristics

8

AMBIENT TEMPERATURE (TA) = +25oC

6
4

SUPPLY VOLTAGE (VDD) = 15V

2

4

10

8
6
4

2

3

10

8
6

4
2

2

10

8
6

POWER DISSIPATION (PD) (µW)

4
2

10

11010

FIGURE 7. TYPICAL DYANAMIC POWER DISSIPATION

AS A FUNCTION OF CLOCK FREQUENCY

Chip Dimensions and Pad Layout

(Continued)

10V

10V

5V

CL = 50pF
CL = 15pF

864286422

INPUT FREQUENCY (fCL) (kHz)

864

2

3

10

2864

264

4

10

Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10

-3

inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

665