Page 1
INTEGRATED CIRCUITS
FB2031
9-bit latched/registered/pass-thru
Futurebus+ transceiver
Product specification
IC19 Data Handbook
1995 May 25
Page 2
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
FEA TURES
•Latched, registered or straight through in
either A to B or B to A path
•Drives heavily loaded backplanes with
equivalent load impedances down to 10Ω.
•High drive 100mA BTL open collector
drivers on B-port
•Allows incident wave switching in heavily
loaded backplane buses
•Reduced BTL voltage swing produces less
noise and reduces power consumption
•Built-in precision band-gap reference
provides accurate receiver thresholds and
improved noise immunity
•Compatible with IEEE Futurebus+ or
proprietary BTL backplanes
•Each BTL driver has a dedicated Bus GND
for a signal return
•Controlled output ramp and multiple GND
pins minimize ground bounce
•Glitch-free power up/power down operation
•Low I
current
CC
•Tight output skew
•Supports live insertion
QUICK REFERENCE DATA
SYMBOL PARAMETER TYPICAL UNIT
t
PLH
t
PHL
t
PLH
t
PHL
C
I
I
O
OL
CC
Propagation delay
An to Bn
Propagation delay
Bn to An
2.7 ns
4.4
4.2
Output capacitance (B0 – Bn only) 6 pF
Output current (B0 – Bn only) 100 mA
Supply current
AIn to Bn
(outputs Low or High)
Bn to AOn (outputs Low) 50 mA
17 mA
Bn to AOn (outputs High) 25
ORDERING INFORMATION
PACKAGE
COMMERCIAL RANGE
VCC = 5V±10%; T
= 0°C to +70°C
amb
VCC = 5V±10%; T
52-pin Plastic Quad Flat Pack (QFP) FB2031BB CD3206BB SOT379-1
INDUSTRIAL RANGE
= –40°C to +85°C
amb
DRAWING
NUMBER
ns
PIN CONFIGURATION
LOGIC GND
LOGIC GND
LOGIC GND
LOGIC GND
LOGIC GND
LOGIC GND
LOGIC GND
CC
V
LOGIC GND
A1
A0
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
A2
3
4
A3
A4
A5
A6
A7
9-Bit latched/registered transceiver
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
A8
SEL1
LCBA
OEA
BIAS V
OEB0
FB2031
52-lead PQFP
CC
BG V
LCAB
SEL0
BG GND
CC
TCK (option)
V
OEB1
CC
V
TDI (option)
TDO (option)
TMS (option)
B0
BUS GND
39
38
37
36
35
34
33
32
31
30
29
28
27
B8
B7
BUS GND
BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND
B5
BUS GND
B6
BUS GND
SG00060
1995 May 25 853-1714 15279
2
Page 3
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
DESCRIPTION
The FB2031 is a 9-bit latched/registered
transceiver featuring a latched, registered or
pass-thru mode in either the A-to-B or B-to-A
direction. The FB2031 is intended to provide
the electrical interface to a high performance
wired-OR bus.
The TTL-level side (A port) has a common
I/O. The common I/O, open collector B port
operates at BTL signal levels. The logic
element for data flow in each direction is
controlled by two mode select inputs (SEL0
and SEL1). A “00” configures latches in both
directions. A “10” configures thru mode in
both directions. A “01” configures register
mode in both directions. A “11” configures
register mode in the A-to-B direction and
latch mode in the B-to-A direction.
When configured in the buffer mode, the
inverse of the input data appears at the
output port. In the register mode, data is
stored on the rising edge of the appropriate
clock input (LCAB or LCBA). In the latch
mode, clock pins serve as transparent-Low
latch enables. Regardless of the mode, data
is inverted from input to output.
The 3-State A port is enabled by asserting a
High level on OEA. The B port has two output
enables, OEB0 and OEB1
is High and OEB1
enabled.
. Only when OEB0
is Low is the output
When either OEB0 is Low or OEB1
the B port is inactive and is pulled to the level
of the pullup voltage. New data can be
entered in the register and latched modes or
can be retained while the associated outputs
are in 3-State (A port) or inactive (B port).
The B-port drivers are Low-capacitance open
collectors with controlled ramp and are
designed to sink 100mA. Precision band gap
references on the B-port insure very good
noise margins by limiting the switching
threshold to a narrow region centered at
1.55V.
The B-port interfaces to “Backplane
Transceiver Logic” (see the IEEE 1194.1 BTL
standard). BTL features low power
consumption by reducing voltage swing (1V
p-p, between 1V and 2V) and reduced
capacitive loading by placing an internal
series diode on the drivers. BTL also
provides incident wave switching, a necessity
for high performance backplanes.
Output clamps are provided on the BTL
outputs to further reduce switching noise.
The “V
effects during a Low-to-High transition. The
“V
clamp, the “trapped reflection” clamp, clamps
out ringing below the BTL 0.5V V
This clamp remains active for approximately
100ns after a High-to-Low transition.
” clamp reduces inductive ringing
OH
” clamp is always active. The other
OH
is High,
level.
OL
To support live insertion, OEB0 is held Low
during power on/off cycles to insure glitchfree B port drivers. Proper bias for B port
drivers during live insertion is provided by the
BIAS V pin when at a 5V level while V
Low. The BIAS V pin is a low current input
which will reverse-bias the BTL driver series
Schottky diode, and also bias the B port
output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with
IEEE BTL Standard 1194.1. If live insertion is
not a requirement, the BIAS V pin should be
tied to a V
The LOGIC GND and BUS GND pins are
isolated inside the package to minimize noise
coupling between the BTL and TTL sides.
These pins should be tied to a common
ground external to the package.
Each BTL driver has an associated BUS
GND pin that acts as a signal return path and
these BUS GND pins are internally isolated
from each other. In the event of a ground
return fault, a “hard” signal failure occurs
instead of a pattern dependent error that may
be infrequent and impossible to troubleshoot.
As with any high power device, thermal
considerations are critical. It is
recommended that airflow (300Ifpm)
and/or thermal mounting be used to
ensure proper junction temperature.
CC
pin.
CC
is
P ACKAGE THERMAL CHARACTERISTICS
PARAMETER CONDITION 52-PIN PLASTIC QFP
θja Still air 80°C/W
θja 300 Linear feet per minute air flow 58°C/W
θjc Thermally mounted on one side to heat sink 20°C/W
PIN DESCRIPTION
SYMBOL PIN NUMBER TYPE NAME AND FUNCTION
A0 – A8 50, 52, 2, 4, 6, 8, 10, 12, 14 I/O BiCMOS data inputs/3-State outputs (TTL)
B0 – B8
OEB0 46 Input Enables the B outputs when High
OEB1 45 Input Enables the B outputs when Low
OEA 47 Input Enables the A outputs when High
BUS GND
LOGIC GND 51, 1, 3, 5, 7, 9, 11, 13 GND Logic ground (0V)
V
CC
BIAS V 48 Power Live insertion pre-bias pin
BG V
CC
BG GND 19 GND Band Gap threshold voltage reference ground
SEL0 20 Input Mode select
SEL1 15 Input Mode select
LCAB 18 Input A to B clock/latch enable (transparent latch when Low)
LCBA 16 Input B to A clock/latch enable (transparent latch when Low)
TMS 42 Input Test Mode Select (optional, if not implemented then no connect)
TCK 44 Input Test Clock (optional, if not implemented then no connect)
TDI 22 Input Test Data In (optional, if not implemented then no connect)
TDO 21 Output Test Data Out (optional, if not implemented then shorted to TDI)
40, 38, 36, 34, 32,
30, 28, 26, 24
25, 27, 29, 31, 33,
35, 37, 39, 41
23, 43, 49 Power Positive supply voltage
17 Power Band Gap threshold voltage reference
I/O Data inputs/Open Collector outputs, High current drive (BTL)
GND Bus ground (0V)
1995 May 25
3
Page 4
Philips Semiconductors Product specification
MODE
An to Bn thru mode
An to Bn transparent latch
An to Bn latch and read
An to Bn register
Bn to An thru mode
Bn to An transparent latch
Bn to An latch and read
Bn to An register
Disable Bn outputs
Latch mode (Bn to An)
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
FUNCTION TABLE
INPUTS OUTPUTS
An Bn* OEB0 OEB1 OEA LCAB LCBA SEL0 SEL1 An Bn
L — H L L X X H L input H**
H — H L L X X H L input L
p
Bn outputs latched and read
(preconditioned latch)
p
An outputs latched and read
(preconditioned latch)
p
Disable An outputs X X X X L X X X X Z X
L — H L L L X L L input H**
H — H L L L X L L input L
l — H L L ↑ X L L input H**
h — H L L ↑ X L L input L
data
data
latched
data
X
X
X — H L X H X L L X
l — H L L ↑ X X H input H**
h — H L L ↑ X X H input L
— L Disable H X X H L H input
— H Disable H X X H L L input
— L Disable H X L L L H input
— H Disable H X L L L L input
— L Disable H X L H H H input
— H Disable H X L H H L input
— l Disable H X ↑ L L H input
— h Disable H X ↑ L L L input
— l Disable H X ↑ H H H input
— h Disable H X ↑ H H L input
— X X X H X H L L
— X X X H X H H H
— l Disable H X ↑ L H H input
— h Disable H X ↑ L H L input
X X L X X X X X X X H**
X X X H X X X X X X H**
latched
latched
FUNCTION SELECT TABLE
NOTES:
H = High voltage level
L = Low voltage level
l = Low voltage level one set-up time
prior to the Low-to-High LCXX transition
h = High voltage level one set-up time
prior to the Low-to-High LCXX transition
1995 May 25
MODE SELECTED SEL0 SEL1
Thru mode H L
Register mode (An to Bn) X H
Latch mode (An to Bn) L L
Register mode (Bn to An) L H
L L
H H
X = Don’t care
Z = High-impedance (OFF) state
— = Input not externally driven
↑ = Low-to-High transition
H** = Goes to level of pull-up voltage
4
Bn
* = Precaution should be taken to
ensure B inputs do not float. If they do, they
are equal to Low state.
Disable = OEB0 is Low or OEB1
is High.
Page 5
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
LOGIC DIAGRAM
46
OEB0
45
OEB1
47
OEA
DQ
E
DQ
14
A8
Clk
MUX
A ⇒ B
24
B8
TTL
MUX
A ⇐ B
DQ
E
DQ
12
A7
10
8
6
4
2
52
A1
50
A0
Clk
DQ
E
DQ
Clk
DQ
E
DQ
Clk
MUX
A ⇒ B
MUX
A ⇐ B
MUX
A ⇒ B
MUX
A ⇐ B
MUX
A ⇒ B
DQ
QD
E
DQ
Clk
DQ
E
DQ
Clk
DQ
E
DQ
Clk
26
B7
28
30
32
BTL
34
36
38
B1
40
B0
1995 May 25
LCAB
SEL0
SEL1
LCBA
TMS
TCK
TDI
TDO
18
20
15
16
42
(JTAG Boundary Scan pins)
44
22
21
Decode
OutIn
MUX
A ⇐ B
DQ
E
DQ
Clk
LOGIC GND = 1, 3, 5, 7, 9, 11, 13, 51
BUS GND = 25, 27, 29, 31, 33, 35, 37, 39, 41
BIAS V = 48
V
CC
BG V
BG GND = 19
CC
= 23, 43, 49
=17
SG00061
5
Page 6
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL
V
T
V
V
I
OUT
I
OUT
STG
CC
IN
IN
Supply voltage -0.5 to +7.0 V
Input voltage All inputs except B0 – B8 -1.2 to +7.0 V
Input current -40 to +5.0 mA
Voltage applied to output in High output state -0.5 to +V
Current applied to output in Low output state A0 – A8 48 mA
Storage temperature -65 to +150 °C
RECOMMENDED OPERATING CONDITIONS (Industrial)
SYMBOL PARAMETER LIMITS UNIT
V
C
T
V
V
I
I
OH
I
I
amb
CC
IH
IL
IK
OL
IA
OB
Supply voltage 4.5 5.0 5.5 V
High-level input voltage Except B0–B8 2.0 V
Low-level input voltage Except B0 – B8 0.8 V
Input clamp current Control inputs -40 mA
High-level output current A0 – A8 -3 mA
Low-level output current A0 – A8 24 mA
Off device input current Except B0 – B8,
Output capacitance of B port 6 7 pF
Operating free-air temperature range –40 +85 °C
PARAMETER RATING UNIT
B0 – B8 -1.2 to +3.5
CC
V
B0 – B8 200
MIN TYP MAX
B0 – B8 1.62 1.55
B0 – B8 1.47
B0 – B8 & A0 – A8 -18
B0 – B8 100
100 µA
VI = 0 to 5.5V, VCC = 0V
RECOMMENDED OPERATING CONDITIONS (Commercial)
SYMBOL PARAMETER LIMITS UNIT
MIN TYP MAX
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
I
IA
C
OB
T
amb
1995 May 25
Supply voltage 4.5 5.0 5.5 V
High-level input voltage Except B0–B8 2.0 V
B0 – B8 1.62 1.55
Low-level input voltage Except B0 – B8 0.8 V
B0 – B8 1.47
Input clamp current Control inputs -40 mA
B0 – B8 & A0 – A8 -18
High-level output current A0 – A8 -3 mA
Low-level output current A0 – A8 24 mA
B0 – B8 100
Off device input current Except B0 – B8,
100 µA
VI = 0 to 5.5V, VCC = 0V
Output capacitance of B port 6 7 pF
Operating free-air temperature range 0 +70 °C
6
Page 7
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
DC ELECTRICAL CHARACTERISTICS (Industrial)
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
I
OH
I
OFF
V
OH
High level output current B0 – B8 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA
Power-off output current B0 – B8 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V 200 µA
High-level output voltage A0 – A8
PARAMETER TEST CONDITIONS
4
VCC = MIN, VIL = MAX, VIH = MIN, IOH = -24mA 2.0 V
VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA 2.5 2.85
A0 – A8
V
Low-level output voltage B0 – B8 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA .75 1.0 1.1 V
OL
4
VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA 0.5
VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA 1.15
VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA 1.15
VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA 0.5
V
Input clamp voltage Control pins VCC = MIN, II = I
IK
A0 – A8
IK
VCC = MIN, II = -18mA -1.2 V
B0 – Bn
I
Input current at maximum
I
input voltage
I
High-level input current
IH
Except
B0–B8
Except
B0
–B8
VCC = MAX, VI = 0.5V or 5.5V ±50 µA
VCC = MAX, VI = 2.7V 20
B0 – B8 VCC = MAX, VI = 1.9V 100
5
I
Low-level input current
IL
Except
B0
–B8
VCC = MAX, VI = 3.5V
VCC = MAX, VI = 0.5V -20
B0 – B8 VCC = MAX, VI = 0.75V -100
IIH + I
IIL + I
I
Off-state I/O High current A0 – A8 VCC = MAX, VO = 2.7V 50 µA
OZH
Off-state I/O Low current A0 – A8 VCC = MAX, VO = 0.5V -50 µA
OZL
OS
Short-circuit output
3
current
A0 – A8
only
VCC = MAX, VO = 0.0V -45 -150 mA
An to Bn VCC = MAX, outputs Low or High 17 30
Bn to An VCC = MAX, outputs Low 50 78
I
Supply current (total) Bn to An VCC = MAX, outputs High 25 45 mA
CC
I
CCZ
VCC = MAX, outputs 3-State 28 50
Worst case VCC = MAX, all A and B outputs on 50 78
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
= 5V, T
CC
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
amb
= 25°C.
, the use of high-speed test apparatus and/or sample-and-hold
OS
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Due to test equipment limitations, actual test conditions are V
5. For B port input voltage between 3 and 5 volts I
6. B0
– B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.
will be greater than 100µA, but the parts will continue to function normally.
IH
= 1.8V and VIL = 1.3V for the B side.
IH
7. T emperature range: 0 to +85°C.
8. T emperature range: –40 to 0°C.
1
LIMITS UNIT
MIN TYP2MAX
-0.5
µA
100 mA
µA
1995 May 25
7
Page 8
Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
VOHHigh-level output voltage
A0
4
V
VOLLow-level output voltage
V
A
B0
B8
µ
IL
µ
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
DC ELECTRICAL CHARACTERISTICS (Commercial)
Over recommended operating free-air temperature range unless otherwise noted.
LIMITS
MIN TYP2MAX
I
I
OFF
V
I
IIH + I
IIL + I
I
I
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
4. Due to test equipment limitations, actual test conditions are V
5. For B port input voltage between 3 and 5 volts I
6. B0
High level output current B0 – B8 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA
OH
Power-off output current B0 – B8 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA
p
– A8
A0 – A8
p
B0 – B8 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA 1.15
VCC = MIN, VIL = MAX, VIH = MIN, IOH = -24mA 2.0
VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA 2.5 2.85
4
VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA 0.5
VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA .75 1.0 1.1
VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA 0.5
Input clamp voltage
IK
Input current at maximum
I
I
input voltage
High-level input current
IH
I
Low-level input current
IL
Control pins VCC = MIN, II = I
A0 – A8
B0 – Bn
Except
B0–B8
Except
B0–B8
–
Except
B0–B8
VCC = MIN, II = -18mA -1.2
VCC = MAX, VI = 0.0V or 5.5V ±50 µA
VCC = MAX, VI = 2.7V 20
VCC = MAX, VI = 1.9V 100
VCC = MAX, VI = 3.5V
VCC = MAX, VI = 0.5V -20
IK
5
100 mA
B0 – B8 VCC = MAX, VI = 0.75V -100
Off-state I/O High current A0 – A8 VCC = MAX, VO = 2.7V 50 µA
OZH
Off-state I/O Low current A0 – A8 VCC = MAX, VO = 0.5V -50 µA
OZL
OS
Short-circuit output
3
current
A0 – A8
only
VCC = MAX, VO = 0.0V -45 -150 mA
An to Bn VCC = MAX, outputs Low or High 17 30
Bn to An VCC = MAX, outputs Low 50 78
Supply current (total) Bn to An VCC = MAX, outputs High 25 45 mA
CC
I
CCZ
VCC = MAX, outputs 3-State 28 50
Worst case VCC = MAX, all A and B outputs on 50 78
= 5V, T
CC
OS
– B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.
= 25°C.
amb
tests should be performed last.
will be greater than 100µA, but the parts will continue to function normally.
IH
IH
, the use of high-speed test apparatus and/or sample-and-hold
OS
= 1.8V and VIL = 1.3V for the B side.
-0.5
V
µ
A
1995 May 25
8
Page 9
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
I
Bias in DC current
IOLOFF
Power u current
µA
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
LIVE INSERTION SPECIFICA TIONS
LIMITS
MIN NOM MAX
V
BIASV
BIASV
V
I
I
IBnPEAK
t
Bias pin voltage VCC = 0 to 5.25V, Bn = 0 to 2.0V 4.5 5.5 V
VCC = 0 to 4.75V, Bn = 0 to 2.0V,
p
Bias V = 4.5 to 5.5V
VCC = 4.5 to 5.5V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
Bus voltage during prebias B0 – B8 = 0V, Bias V = 5.0V 1.62 2.1 V
Bn
Fall current during prebias B0 – B8 = 2V, Bias V = 4.5 to 5.5V 1 µA
LM
Rise current during prebias B0 – B8 = 1V, Bias V = 4.5 to 5.5V -1 µA
HM
Peak bus current during
insertion
p
Input glitch rejection VCC = 5.0V 1.35 1.0 ns
GR
VCC = 0 to 5.25V, B0 – B8 = 0 to 2.0V,
Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns
V
= 0 to 5.25V, OEB0 = 0.8V 100
CC
V
= 0 to 2.2V, OEB0 = 0 to 5V 100
CC
1 mA
10 µA
10 mA
AC ELECTRICAL CHARACTERISTICS (Industrial)
A PORT LIMITS
T
= –40 to +85°C,
SYMBOL PARAMETER
TEST
CONDITION
T
= +25°C, VCC = 5V,
amb
CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
TLH
t
THL
tSK(o)
tSK(p)
Maximum clock frequency Waveform 4 120 150 100 MHz
Propagation delay (thru mode)
Bn to An
Propagation delay (transparent latch)
Bn to An
Propagation delay
LCBA to An
Propagation delay
SEL0 or SEL1 to An
Output enable time from High or Low
OEA to An
Output disable time to High or Low
OEA to An
Output transition time, An Port
10% to 90%, 90% to 10%
Output to output skew for multiple
channels
Pulse skew
t
PHL
– t
1
PLH
2
MAX
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 5, 6
Waveform 5, 6
Test Circuit and
Waveforms
Waveform 3 0.5 1.0 1.5 ns
Waveform 2 0.5 1.0 1.0 ns
2.5
2.4
2.9
2.8
2.6
2.4
1.5
1.7
2.1
2.0
1.9
1.7
4.4
4.2
4.6
4.3
4.1
4.7
3.8
3.9
3.5
3.8
3.4
3.2
5.9
5.5
6.2
5.9
5.5
6.1
5.2
6.0
4.8
5.3
4.8
4.8
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V
3. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
= 5V, T
CC
amb
= 25°C.
, the use of high-speed test apparatus and/or sample-and-hold
OS
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Due to test equipment limitations, actual test conditions are V
5. For B port input voltage between 3 and 5 volts I
6. B0
– B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.
will be greater than 100µA, but the parts will continue to function normally.
IH
= 1.8V and VIL = 1.3V for the B side.
IH
amb
VCC = 5V±10%,
CL = 50pF, RL = 500Ω
2.3
2.4
2.7
2.5
2.0
2.0
1.2
1.5
1.8
1.7
1.6
1.5
3.0
1.7
7.0
6.2
7.1
7.0
6.2
6.8
6.2
6.5
6.0
6.3
5.5
5.5
7.5
4.0
UNIT
ns
ns
ns
ns
ns
ns
ns
1995 May 25
9
Page 10
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
AC ELECTRICAL CHARACTERISTICS (Industrial)
B PORT LIMITS
T
= –40 to +85°C,
SYMBOL PARAMETER
TEST
CONDITION
T
= +25°C, VCC = 5V,
amb
CD = 30pF, RU = 16.5Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
TLH
t
THL
t
SK(o)
tSK(p)
Propagation delay (thru mode)
An to Bn
Propagation delay (transparent latch)
An to Bn
Propagation delay
LCAB to Bn
Propagation delay
SEL0 or SEL1 to Bn
Enable/disable time
OEB0 or OEB1 to Bn
Output transition time, Bn Port
(1.3V to 1.8V)
Output to output skew for multiple
channels
Pulse skew
t
PHL
– t
1
PLH
2
MAX
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Test Circuit and
Waveforms
1.0
1.0
1.0
1.0
2.0
1.5
2.0
1.5
1.5
1.2
1.0
0.6
3.0
2.7
3.2
3.1
4.0
4.0
3.5
2.3
3.0
2.4
5.0
4.0
5.0
4.2
5.5
5.5
5.5
4.5
5.0
4.5
2.0
3.0
Waveform 3 1.0 0.4 1.6 1.6 ns
Waveform 2 0.3 1.0 1.5 ns
NOTES:
actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or
1. t
PN
HL. Skew times are valid only under same test conditions (temperature, V
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
2. t
SK
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
, loading, etc.).
CC
amb
VCC = 5V±10%,
CD = 30pF, RU = 16.5Ω
1.5
1.5
1.5
1.5
1.5
1.5
2.0
1.0
1.0
1.0
0.9
0.6
5.7
4.5
5.5
5.0
6.5
6.0
6.1
5.5
5.7
5.5
3.0
3.0
UNIT
ns
ns
ns
ns
ns
ns
1995 May 25
10
Page 11
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
AC ELECTRICAL CHARACTERISTICS (Commercial)
A PORT LIMITS
T
= 0 to +70°C,
SYMBOL PARAMETER
TEST
CONDITION
T
= +25°C, VCC = 5V,
amb
CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
TLH
t
THL
tSK(o)
tSK(p)
Maximum clock frequency Waveform 4 120 150 100 MHz
Propagation delay (thru mode)
Bn to An
Propagation delay (transparent latch)
Bn to An
Propagation delay
LCBA to An
Propagation delay
SEL0 or SEL1 to An
Output enable time from High or Low
OEA to An
Output disable time to High or Low
OEA to An
Output transition time, An Port
10% to 90%, 90% to 10%
Output to output skew for multiple
channels
Pulse skew
t
PHL
– t
1
PLH
2
MAX
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 5, 6
Waveform 5, 6
Test Circuit and
Waveforms
Waveform 3 0.5 1.0 1.5 ns
Waveform 2 0.5 1.0 1.0 ns
2.5
2.4
2.9
2.8
2.6
2.4
1.5
1.7
2.1
2.0
1.9
1.7
4.4
4.2
4.6
4.3
4.1
4.7
3.8
3.9
3.5
3.8
3.4
3.2
5.9
5.5
6.2
5.9
5.5
6.1
5.2
6.0
4.8
5.3
4.8
4.8
NOTES:
actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL.
1. t
PN
Skew times are valid only under same test conditions (temperature, V
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
2. t
SK
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
, loading, etc.).
CC
amb
VCC = 5V±10%,
CL = 50pF, RL = 500Ω
2.3
2.4
2.7
2.5
2.0
2.0
1.2
1.5
1.8
1.7
1.6
1.5
2.0
1.0
6.6
5.9
7.0
6.5
6.0
6.5
6.0
6.5
5.8
6.0
5.4
5.4
7.5
3.5
UNIT
ns
ns
ns
ns
ns
ns
ns
1995 May 25
11
Page 12
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
AC ELECTRICAL CHARACTERISTICS (Commercial)
B PORT LIMITS
T
= 0 to +70°C,
SYMBOL PARAMETER
TEST
CONDITION
T
= +25°C, VCC = 5V,
amb
CD = 30pF, RU = 16.5Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
TLH
t
THL
t
SK(o)
tSK(p)
Propagation delay (thru mode)
An to Bn
Propagation delay (transparent latch)
An to Bn
Propagation delay
LCAB to Bn
Propagation delay
SEL0 or SEL1 to Bn
Enable/disable time
OEB0 or OEB1 to Bn
Output transition time, Bn Port
(1.3V to 1.8V)
Output to output skew for multiple
channels
Pulse skew
t
PHL
– t
1
PLH
2
MAX
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
Test Circuit and
Waveforms
1.0
1.0
1.0
1.0
2.0
1.5
2.0
1.5
1.5
1.5
1.0
0.6
3.0
2.7
3.2
3.1
4.0
4.0
3.5
2.3
3.0
2.4
5.0
4.0
5.0
4.2
5.5
5.5
5.5
4.5
5.0
4.5
2.0
3.0
Waveform 3 0.4 1.0 1.6 ns
Waveform 2 0.3 1.0 1.5 ns
NOTES:
actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or
1. t
PN
HL. Skew times are valid only under same test conditions (temperature, V
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
2. t
SK
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
, loading, etc.).
CC
amb
VCC = 5V±10%,
CD = 30pF, RU = 16.5Ω
1.0
0.5
1.0
0.8
1.5
1.0
2.0
1.0
1.0
0.8
1.0
0.6
5.5
4.5
5.5
4.5
6.0
6.0
6.0
5.0
5.5
5.5
2.3
2.3
UNIT
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS (Industrial)
SYMBOL PARAMETER
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
Setup time
An to LCAB
Hold time
An to LCAB
Setup time
Bn to LCBA
Hold time
Bn to LCBA
Pulse width, High or Low
LCAB or LCBA
TEST
CONDITION T
amb
MIN TYP MAX MIN MAX
Waveform 4 1.0
1.0
Waveform 4 1.0
1.0
Waveform 4 2.0
2.0
Waveform 4 0.0
0.0
Waveform 4 3.0
3.0
LIMITS
T
= –40 to +85°C,
= +25°C, VCC = 5V,
amb
VCC = 5V±10%, UNIT
CL = 50pF (A side) / CD = 30pF (B side)
RL = 500Ω (A side) / RU = 16.5Ω (B side)
1.5
1.0
2.0
1.0
3.0
3.0
0.0
0.0
3.0
3.0
ns
ns
ns
ns
ns
1995 May 25
12
Page 13
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
AC SETUP REQUIREMENTS (Commercial)
LIMITS
SYMBOL PARAMETER
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
Setup time
An to LCAB
Hold time
An to LCAB
Setup time
Bn to LCBA
Hold time
Bn to LCBA
Pulse width, High or Low
LCAB or LCBA
TEST
CONDITION T
Waveform 4 1.0
Waveform 4 1.0
Waveform 4 2.0
Waveform 4 0.0
Waveform 4 3.0
amb
MIN TYP MAX MIN MAX
1.0
1.0
2.0
0.0
3.0
= +25°C, VCC = 5V,
CL = 50pF (A side) / CD = 30pF (B side)
RL = 500Ω (A side) / RU = 16.5Ω (B side)
T
= 0 to +70°C,
amb
VCC = 5V±10%, UNIT
1.5
1.0
2.0
1.0
3.0
3.0
0.0
0.0
3.0
3.0
ns
ns
ns
ns
ns
1995 May 25
13
Page 14
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
AC WAVEFORMS
Input
Output
V
M
t
PLH
V
M
t
PHL
V
M
V
M
Waveform 1. Propagation Delay for Data
or Output Enable to Output
An, Bn
An, Bn
V
M
tSK(o)
V
M
Waveform 3. Output to Output Skew
OEA
V
M
t
PZH
An
V
M
t
PHZ
V
M
VOH -0.3V
OV
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
NOTE: V
= 1.55V for Bn, V
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
= 1.5V for all others.
M
Input
Output
V
M
t
(input)
w
t
PHL
V
M
t
(output)
w
V
M
t
PLH
V
M
Waveform 2. Propagation Delay for Data
or Output Enable to Output
V
An, Bn
LCAB, LCBA
M
t
t
s
h
V
M
t
(H)
w
1/f
MAX
tst
h
t
(L)
w
V
M
Waveform 4. Setup and Hold Times,
Pulse Widths and Maximum Frequency
OEA
V
M
t
PZL
An
V
M
t
PLZ
V
M
VOL +0.3V
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
SG00062
1995 May 25
14
Page 15
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
TEST CIRCUIT AND WAVEFORMS
V
CC
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
Test Circuit for 3-State Outputs on A Port
SWITCH POSITION
TEST SWITCH
t
PLZ,
All other
PULSE
GENERATOR
t
PZL
V
IN
Test Circuit for Outputs on B Port
BIAS
V
R
closed
open
D.U.T.
T
V
CC
V
OUT
R
L
R
C
L
L
2.0V (for RU = 9 Ω)
2.1V (for RU = 16.5 Ω)
R
U
C
D
7.0V
NEGATIVE
PULSE
POSITIVE
PULSE
Family
FB+
A Port
90%
10%
V
M
10%
t
THL
t
TLH
90%
V
M
VM = 1.55V for Bn, VM = 1.5V for all others.
INPUT PULSE REQUIREMENTS
Low V
0.0V
1.0VB Port
DEFINITIONS:
RL= Load Resistor; see AC CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
CD= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
RU= Pull up resistor; see AC CHARACTERISTICS for value.
t
W
10%
(tf)
(tr)
90%
t
W
Input Pulse Definitions
Rep. RateAmplitude t
1MHz3.0V
t
W
500ns
1MHz2.0V
OUT
AMP (V)
90%
V
M
LOW V
t
(tr)
TLH
t
(tf)
THL
AMP (V)
V
M
10%
LOW V
TLHtTHL
2.5ns
2.0ns500ns
2.5ns
2.0ns
of pulse generators.
SG00063
1995 May 25
15
Page 16
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm SOT379-1
1995 May 25
16
Page 17
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
NOTES
1995 May 25
17
Page 18
Philips Semiconductors Product specification
FB20319-bit latched/registered/pass-thru Futurebus+ transceiver
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 08-98
Document order number:
1995 May 25
18
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