Datasheet CB55000 Datasheet (SGS Thomson Microelectronics)

1/15

CB55000 Series

February 2002

FEATURE

■

0.25 micron drawn (0.20 micron effective
channel length process), six layers of metal
connected by fully stackable vias and contacts,
Shallow Trench Isolation, low resistance,
salicided active areas and gates. Deep UV
lithography.

■

2.5 V optimized transistor with 3.3 V I/O and
supply interface capabilit y .

■

Average gate density: 30 K/mm2, plus low
power consumption of 70 nanoWatt/Gate/MHz /
Stdload.

■

Two input NAND delay of 90 pS (typical) with
fanout=2.

■

Library available in commercial, industrial and
military temperature range with supply ranging
from 2.70 V down to 1.8 V for the core
according to EIA/JESD 8-5 specification.
Additional low voltage range down to 1.5 V for
very low voltage/low power applications
supported

■

Broad I/O functionality including:
– Low Voltage CMOS.
– Low Voltage TTL, PECL, HSTL, SSTL,

LVDS, PCI.

■

AGP 2X and 4X, USB to support 2.5 V and 3.3
V I/O interface according to EIA/JESD 8A
specification.

■

Drive capability up to 8 mA per buffer with slew
rate control, current spike suppression
impedance matching, and process
compensation capability to reduce delay
variation.

■

Designs easily portable from previous
generations of CB45000 through cell mapping
with an average factor 2 density increase, 1.7
speed increase and 2.5 power reduction at
respective nominal voltages.

■

Generators to support Single Port, Dual port
and multiple Port RAM, and ROMs with BIST
options.

■

Extensive embedded function library including
ST DSP and micro-cores, third-party IPs,
Synopsys and Mentor Inventra synthetic
libraries id ea lly su it e d for c omplete System On
Chip fast integration .

■

80µm pitch linear and 50µm staggered pad

libraries.

■

Fully independent power and ground
configuration for core and I/Os supported.

■

I/O ring capability up to 1500 pads.

■

Latch-up trigger current > +/- 500 mA. ESD
protection above 4 kV in H.B.M.

■

Oscillators and PLLs for wide frequency
spectrum.

■

Broad range of more than 600 SSI cells.

■

Design for test features including IEEE 1149.1
JTAG Boundary Scan architecture.

■

Synopsys, Cadence and Mentor based design
systems with interface from multiple
workstations.

■

Broad range of packaging solutions, including
BGA, LBGA, TQFP, PQFP, PLCC up to 1000
pins with enhanced power dissipation options.

■

1.25 GigaHertzGigabit DLL technique.

CB55000 Super Integration

Cost Effective Product

■

Architecture partitioning

■

Trouble-free integration

■

Application-specific

Your Product is Unique

■

User specified cell integration

■

Design confidentiality

■

IP fully re-usable

DPRAM ST20

ROM

DSP

HCMOS7 Standard Cells

CB55000 Series

2/15

Figure 1. Metal 1 perspective view

CMOS 0.25µm, Shallow Trench Isolation, M1: Tungsten

3/15

CB55000 Series

1 GENERAL DESCRIPTION

The CB55000 standard cell series uses a high performance, low -voltage, 0.25µm drawn (0.20µm effective),
six metal levels CMOS process HCMOS7 to a 90 pico-second internal delay while offering very low power dis­sipation and high noise immunity.

With an average routed gate density of 30,000 gates/mm

2

, the CB55000 family allows the integration of up to
15 million equivalent gates and is ideal for high-c omplexi ty or high-performance devices fo r computer, tel ecom­munication and consumer products.

With a typical gate delay of 70 ps (for a 2-input NAND gate at fan-out 1), the library meets the most demanding
speed requirements in telecommunication and computer application designs today.

Optimized for 2.5 V operation, the library features a power consumption of less than 70 nW/Gate/MHz (fan­out=1) and 30 nW/Gate/MHz (fan-out=1) at 1.8 V.

The I/O buffers can be fully configured for both 2.5 V and 3.3 V interface options, with several high speed buffer
types available. These include: low voltage differential (LVDS) I/Os, PCI/AGP, PECLs, and HSTL.

The pad pitch down to 50µm, in a staggered arrangement, meets the requirements of high pin-count devices
which tend to become pad-limited at such library densities. For very high pin-count ICs, advanced packaging
solutions such as Chip Scale Packaging in fine pitch BGA are available.

New packaging solutions using a flip-chip approach are currently being developed.

Figure 2. HCMOS7 Front end cross section

MOS gate length: 0.25µm, Shallow Trench Isolation, M1: Tungsten

CB55000 Series

4/15

2 TECHNOLOGY OVERVIEW

The advanced HCMOS7 transistor architecture: at 0.25µm drawn length and 0.20µm effective length, very thin
gate oxide: 5 nanometers, optimized threshold voltages and salicided source, drain, and gate leads to intrinsi­cally high performances in both N c hannel and P channel driving currents.

The major scaling factor is obtained through deep UV lithography at most masking levels, making sub-micron
pitch a reality.

Further integration in the process front-end comes from the use of the Shallow Trench Isolation process be­tween active regions, both improving density and planarity of transistors. In or der to allow full utiliz ation of such
transistor density, up to 6 levels of metal are made available for routing.

The first metal level is Tungsten for local interconnection, while the other five metal levels are of low resistivity
aluminum for long range interconnection and power distribution.

The thick inter-level dielectric is completely planarized by Chemical Mechanical Polishing, which provides de­fect-free isolation between stripes within the same as well as between different levels.

Usage of Tungsten plugs at contacts and vias allows extremely dense and reliable interconnection between
metal layers. These vias and contacts are fully stackable, providing a direct vertical electrical connection from
the active level up to the sixth metal level. This efficient interconnect scheme makes routing fast and easy, as
well as having a very positive impact on high gate count, random-logic blocks density and routability.

The combination of both high drive and dense transistors, easily interconnected with up to six fine-pitch metal
levels and isolated by thick dielectric leads to an optimum gate density, with low parasitic resi stance and capac­itance. This results in very short interconnected gate delay and minimized power consumption.

Figure 3. HCMOS7 Back end Cross Section

5/15

CB55000 Series

3 LIBRARY

The CB55000 library is organized into three categories:
– SSI cell libr ar y

– I/O cell library
– Macrofunctions

3.1 SSI Cell Library Overview

The design of the CB55000 family has been opti mized to allow e xtremely high density , high speed and low pow­er designs. For these reasons, a wide range of cells with different ranges of driving capabilities are available in
the library.

The library cells have been optimized in terms of functional and electrical parameters, in order to have:
– Good balancing

– Maximum speed
– Optimum threshold voltage
–Symmetric V

dd/Vss

noise margins

– Minimum power-speed value
The geometrical aspect of the cells was configured to allow an extremely dense design, fully exploiti ng the fea-

tures of the Place and Route tool in terms of horizontal and vertical routing grids. For Place and Route, up to
six layers of metal are utilized; the first metal layer is dedicated to intracell wiring, the second layer to power
distribution and routing, the third and forth layers to routing, and the fifth and sixth to power distribution, clock
bussing and routing.

Figure 4. ND2 f ig ure from C B 55000

CB55000 Series

6/15

3.2 Core Logic

The propagation delays shown in CB55000 data book are given for nominal processing, 2.5 V, 25°C tempera­ture. However, there are additional factors that affect the delay char ac teristics of the cells. These inc lude: load­ing due to fanout and interconnect routing, supply voltage, junction temperature of the device, processing
tolerance and input signal transition time.

Prior to physical layout, the design system can estimate the del ays associated with any criti cal path. The impact
of the placement and routing can be accur ately RC back -annotated from the lay out for fi nal simulati ons of critic al
timing. The median effects on the cells delay of junction temperature (Kt coefficient) and supply voltage (K v co­efficient) are summarized in the following tables at a fixed cell input slope. A third factor is related to process
variations and has a minimum median of 0.84 for best case process and a maximum median of 1.18 for worst
case process.

Table 1. Junction temperature multipliers

Table 2. Voltage multipliers

3.3 I/O Buffer Libraries

Two basic buffer libraries are offered with CB55000, one 80µm pad in line pitch library and one 50µm stag­gered pad library to support pad limited designs.

Apart from standard ESD and latch-up protections present in each I/O, a proprietary clamp within each power
supply provides proper paths to all types of E SD discharges, efficiently protecting the I/Os. As a result, the buff­ers withstand more than 4 kV ESD according to Mil 883C Human Body Model specification.

In order to limit switching noise and keep a fixed buffer delay, independent of process, supp ly voltage and tem­perature, compensated active slew rate buffers can be selected, providing a fixed and stable dI/dt at 8,16 or
32 mA/ns.

In order to interface with 3.3 V application (from 2.7 up to 3.6 V), a wide range of 3.3 V capable input/output
buffers (mixable with standard 2.5V ones) can be chosen. In this case the 3.3 V rail in the chip periphery must
be powered through a 3.3 V external supply.

True 5 volt tolerant input buffer is also available with process option.

Temperature (°C)

Kt

-55 .84

-40 .87
25 1.00
70 1.09
85 1.12

105 1.16
125 1.20

V

dd

(V)

Kv

1.80 1.33

2.00 1.21

2.25 1.09

2.50 1.00

2.75 0.94

7/15

CB55000 Series

3.4 I/O Test Interface

The I/O cells have a dedicated test interface to facilit ate parametric and lddq testing of devices. Th is te st i nterf ace
connects standard core signals or dedicated test signals to the I/O cells allowing all output buffers to be driven high,
low or put into tri-state regardless of the state of the internal logic.

This greatly simplifi es parametric testing of the dev ice and also ass isting customer s who wish to use thi s feature
during board testing. Note that all output buffers can be tri-stated by this func tion inc luding buffer s that normall y
do not tri-state.

This test function also turns off all pull down resistors

,

shuts down all differential receivers and converts them
into standard CMOS receivers. This allows lddq test methodologies to be employed in a very efficient way,
avoiding unneeded circuit overhead.

3.5 Macrocells

The CB55000 series has internal macrocells that are robust in variety and performance. The cell selection has
been driven by the need of Synthesis and HDL-based design techniques. This offering is rich in buffers, complex
combination cells and multi-power drive cells, which allow the Synthesis tool to create a netlist compatible with
the requirements of Place and Route tools.

Macrofunctions ar e a series of soft -macros f acil itating qui ck c apt ure of lar ge func tional bl ocks a nd ar e avail able
for such functions as counters, shift registers and adders. Macrofunctions are implemented at layout by utilizing
macrocells and interconnecting to create the logic function.

3.5.1 Module generator s

A series of module generators using compiled cell generation techniques are available to support a range of
megacells. These modules enable the designer to choose individual parameters in order to create a compiled
cell, which meets the specific application requirements. These include ROM, single and dual port RAM, multi­port RAM and FIFO.

For most of the above memories, two different generators are provided, one optimized for speed and one opti­mized for power. All memories h ave a compl ete standby mode where current consumptio n is li mited to pr ocess
leakage.

Table 3. List of module generators

Generator Description Bit (Min.) Kbit (Max)

Word width

(Max.)

Romd
Rom3

High speed Sync.
Diffusion ROM
Low power Sync.
Diffusion ROM

128
128

2000

256

64
32

SPS2
SPS3
SPS4

SPS5
SPS6

High speed Sync.
Single port RAM
Low power Sync.
Single Port RAM
Small cuts Sync.
Low power
Single Port Ram
Low power Sync.
Single Port RAM
High density
Low power & voltage
High density Sync.
Single Port Ram

64
16

2

1000
2000

512

32
16

512

2000

byte write

suppor t ed

64
32

128

64
32

CB55000 Series

8/15

Embedded Non Volatile Me m ories (OTP, Flash, ...) with specific process options are also under development .

3.5.2 Micro Li brary & I.P.s

MicroLibrary includes an extensive portfolio of microcores and application specific I.P.s; provided through both
internal developments and partners licensing agreements.

A short list of this portfolio consists of:

■

General purpose macro functions.
– Microcores (8,16,32 bits) like:8051,ST10,ST20, SH4 ,ARM 7TDM I ,
– DSP:D950,ST100,
– PLL, Frequency synthesizer, Comparato rs,
– DAC,ADC (8,10,16 bits).

■

Application specific I.P.s for:
– Data communications (10/100 ETH MAC & PHY, Gigabit,..),
– Telecommunication (622MHz phase aligner, clock recovery),
– Computer and peripherals (PCI,USB,SSCI,RAMD AC,IEEE1394,FiberChannel),
– Audio (CODEC,..).

SPS2HD High speed & density

High density Sync.
Single port RAM

64 512 64

DPR2
DPR3

High speed Sync.
Dual port RAM
Low power Sync.
Dual port RAM

64
16

256

32

64
32

DP7E Asynchronous Reg. file

Dual port RAM 1W + 1R

2 16 128

MP7A Multipor t RAM

High density Sync.
2W + 2R or 2W + 4R

2 32 128

FIFO High speed 8 4 32

Table 3. List of module generators

(continued)

Generator Description Bit (Min.) Kbit (Max)

Word width

(Max.)

9/15

CB55000 Series

4 DESIGN FOR TESTABILITY

The test time and cost for ASIC testing increases exponentially as the complexity and size of the ASIC grows.
Using a

design-for-testabili ty

methodology allows large, more complex ASICs to be efficiently and economically

tested.
At system level, STMicroelectronics fully supports IEEE 1149.1; the I/O structure utilized in this family is com-

pletely compatible. Several types of core scan cells are provided in the CB55000 Series library. Examples in­clude FDxS/FJKxS edge sensitive and LDxS level sensitive cel ls. Non-ove rlapping clock generator macros ar e
also available.

Test coverage and reliability are further supported by IDDQ (quiescent current) testing; all blocks are designed
to be “IDDQable” so that anomalous leakage due to metal bridging and dielectr ic defects can be screened us ing
proper set of vectors extracted from the test patterns.

For parametric and lddq testing, the I/O cells contain a dedicated test interface as described previously (see I/
O Test Interface’ on page 7).

5 EVALUATION DEVICE

As per STMicroelectronics’ standard policy, all cells and macro-blocks are fully validated and characterized on
silicon through dedicated test vehicules, before final release in the library. In addition, a 3 million-gates evalua­tion chip: CB55Q, has been designed and in order to demonstrate the performances and qualify the global
CB55000 library, as well as verify the effectiveness of the design system.

CB55Q is packaged in a 256 Ball Grid Array (BGA) and permits accurate characterisati on of most representative
cells from the libr ary i ncluding I/O buff ers, sin gle and mixed cell chains (I V, ND2, NR2...),Flip-flops and memory
cuts from various generators.

Typical result on ring SSI chain in ring oscillator mode show a mean between Thl and Tlh of around 37 ps for
an inverter with 1 standard load , and toggle frequency of above 1 GigaHertz for an FD2.

Figure 5. CB55Q Die View

CB55000 Series

10/15

Figure 6. CB55Q Silicon ring oscillator characterization

6 PACKAGE AVAILABILITY

The CB55000 Series is designed so that it can be made c ompatible with all t ypes of traditional (PLCCs, PQFPs)
surface mount packages and also more advanced BGAs and Low Profile BGAs. The main packaging options
include:

Plastic Leaded Chip Carriers (PLCC) up to 84 pins, Metric Q uad Flat Pack (xQFP) thi n and standard, up to 208
pins including high power dissipation versions with slug or spreader.

Ball Grid Array package family:

The diversity in pin count and package style gives the designer the opportunity to find the best compromise for
system size, cost and performances requirements.

Plastic BGA, 1.27mm ball pitch from 208 to 456 pins
High performance BGA, 1.27mm ball pitch from 168 to 640 pins
Flip-Chip BGA, 1.27 or 1mm ball pitch from 352 to1000 pins
Low profile BGA, 1mm ball pitch from 144 to 256 pins
Low profile Fine pitch BGA. 8mm ball pitch from 36 to 180 pins
Ultra Fine pitch BGA .5mm ball pitch from 40 to 304 pins

CB55Q Silicon

Ring Os cillator Characterization

3,00E+01

4,00E+01

5,00E+01

6,00E+01

7,00E+01

8,00E+01

9,00E+01

2,3 2,4 2,5 2,6 2,7

Vdd (Volt)

Cell delay (thl+tlh)/2 (ps)

ND2
NR2
IV

11/15

CB55000 Series

Table 4. Package / pin availability

7 DESIGN METHODOL OGY

STMicrolectronics (STM) ASIC design flow is intended for high performance, high complexity submicron ASIC
designs. 3rd parties tools from leading EDA vendors such as Synopsys, Cadence, Mentor Graphics and STM
proprietary systems are integrated into a framework free design environment that efficiently supports all design
phases.

A hierarchical design methodology with a FastLoop, between floorplanning timing-driven placement and syn­thesis/static timing analysis, guarantees a fast timing prediction and closure after routing.

Other features such as hierarchical Clock tree synthesis, advanced test methodology, formal verification, 3D
parasitic extraction, Crosstalk analysis, IP-reuse, qualifies the STM ASIC design flow as one of the industry's
leading solutions for today's and tomorrow's complex designs.

Pack a g e N a m e

PLCC

TQFP 7x7

TQFP 10x10

TQFP 14x14

TQFP 20x20

TQFP 24x24

PQFP 10x10

PQFP 14x14

PQFP 14x20

PQFP 28x28

PQFP 28x28

with slug

PQFP 28x28

with spreader

Pin Count

20

❍

28

❍

44

❍❍ ❍

48

❍

64

❍❍❍

68

❍

80

❍❍

84

❍

100

❍❍

120

❍ ❍ ❍

128

❍❍ ❍

144

❍ ❍ ❍ ❍

160

❍❍ ❍

176

❍

208

❍❍ ❍

CB55000 Series

12/15

8 ELECTRICAL SPECIFICATIONS

Table 5. Absolute Maximum Ratings

(refer to Notes 1 and 2)

Notes: 1. Referenced to Vss. Stresses above those listed under “absolute Maximum Ratings” may cause permanent damage to the device.

This is a str ess rating only and func tiona l operatio n of the devi ce at these or an y other co ndition s above tho se indica ted in the
operati on sections of this specifi cation is not implied. Exp osure to absolute maximu m rating condit i ons for exten ded periods m ay
affect the device reliability.

2. A dedicated 3.3 V power sup pl y is needed for 3.3 V inputs and ou tputs.

Table 6. Recommended DC Operating Conditions

Notes: 1. Commercial, Industrial, and Military Conditions.

2. Mandatory for 3.3 V buffers only.

3. 3 V buffer specifications are not applicable for main supply below 2.25 V.

4. All circuits will operate to full specifications with a junction temperature of -40 to +125 degrees centigrade. These junctio n temper­atures are compatibl e with the Co m m ercial and Industrial Te m perature Ran ges.

5. All circuits will be functional from -55 to +150 degrees centigrade junction temperature (military Ambient Temperature Range) but
will not necessary operate to published specifications. Only circuits specified as operational to extended temperature range may
be used when operating to Military temperature conditions.

Table 7. General Interface DC Electrical Characteristics

Symbol Parameters Value Unit

V

dd

2.5 V Power Supply Voltage -0.5 to 3.3 V

2.5 V Input or Output Voltage -0.5 to (V

dd

+ 0.5) V

V

dd

3.3 V Power Supply Voltage -0.5 to 4 V

3.3 V Input or Output Voltage -0.5 to (V

dd3

+ 0.5) V

Main Supply Normal Range Operating Voltage V

dd

(refer to note 1)

2.5 V +/- 10% (2.25 V to 2.75 V)

Additional Ring Supply Voltage (refer to notes 1 and 2) 3.3 V + 0.3V/-0.6 V (2.7 V to 3.6 V)
Main Supply Extended Range Operating Voltage

(refer to notes 1 and 3)

2.5 V +/- 10% -28% (1.8 V to 2.75 V)

Operating Ambient Temperature
Commercial (refer to note 4)
Industrial (refer to note 4)
Military (refer to note 5)

0 to 70 degrees Centigrade

-40 to +85 degrees Centigrade

-55 to +125 degrees Centigrade

Symbol Parameter Conditions Min. Type Max Unit

I

il

Low level input current
without pull-up device

Vi=0V

1

1

1) The leakage currents are generally very small (<1 an). The value given here, 1µA, is the maximum that can occur after an
electrostatic stress on the pin.

µA

I

ih

High level input current
without pull-down device

Vi=V

dd

1

1

µA

I

ox

Tri-state output leakage without pull up/
down device

Vo=0V or V

dd

1

1

µA

C

in

Input capacitance

C

out

Output capacitance

C

io

I/O capacitance

I

latchup

I/O latch-up current

V<0V; V>V

dd

2

2) V > V

dd3

for 3.3V buffers.

500

3

3) V > V

dd3

for 3.3V buffers.

mA

V

exd

Electrostatic protection

4

4) Human body model.

Leakage < 1 µA 4000 V

13/15

CB55000 Series

Table 8. Pull-Up and Pull-Down Characteristics

8.1 2.5 V Buffer Specifications

The buffers are called “CMOS” buffers. The nominal supply voltage is 2.25 V < Vdd< 2.75 V. However, the
specifications shown in are still valid for lower voltages.

Table 9. Low Voltage CMOS DC Input Specifications

2.5 V output buffers will be offered with passive slew rate control and process-compensated slew rate control.
In both cases, the typical output current is that shown in Table 10.

Table 10. Slew Rate Versus Drive

Symbol Parameter Conditions Min. Type Max Unit

I

pu

Pull-up current Vi=0V -50 µA

I

pd

Pull-down current

Vi=V

dd

1

1) Vi=V

dd3

for 3.3V buffer

50 µA

R

pu

Equivalent pull-up resistance Vi=0V 50 kΩ

R

pu

Equivalent pull-down
resistance

V

i=Vdd

1

50 kΩ

Symbol Parameter Conditions Min. Type Max Unit

V

il

Low level threshold
(input falling)

No Schmitt 0.5*V

dd

V

V

ih

High level threshold
(input rising)

No Schmitt 0.5*V

dd

V

V

il

Low level input voltage Schmitt input 0.26*V

dd

V

V

ih

High level input voltage Schmitt input 0.7*V

dd

V

V

hyst

Schmitt trigger hysteresis Schmitt input 0.23*V

dd

V

V

ol

Low level output voltage

1

1) Takes into acc ount 0.075*Vdd voltage drop in both supply lines.

I

ol

=XmA

2

2) “X” is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive
capability.

0.15*V

dd

V

V

oh

High level output voltage

(1)

I

oh

=-XmA

2

0.85*V

dd

V

Drive (mA): 2 4 8
Slew Rate

(mA/ns Typical)

81632

Active Slew Rate
(mA/ns Typical)

81632

Typical peak current
(mA)

25 50 100

CB55000 Series

14/15

8.2 3.3 V Buffer Specifications

The 3.3 V buffers comply with the JEDEC s tandard 8- A (June, 1994) . They are als o compati ble w ith the 74VCX
DC specifications for 2.7 V to 3.6 V operation. These buffers are called “TTL”, however they also comply with
Low Voltage CMOS levels. For all buffers, V

dd

(min) = 2.25 V and Vdd(max) = 2.75 V (core supply).

Table 11. LVTTL and LVCMOS DC Input Specifications (2.7 V < V

dd3

<3.6V)

Table 12. LVTTL DC Output Specifications (3.0 V < V

dd3

<3.6V)

Table 13. LVCMOS DC Output Specifications (2.7 V < V

dd3

<3.6V)

Table 14. Slew Rate Versus Drive

Symbol P arameter Conditions Min. Type Max Unit

V

il

Low level input voltage 0.8 V

V

ih

High level input voltage 2.0 V

V

ilhyst

Low level threshold
(input falling)

0.8 1.35 V

V

ihhyst

High level threshold
(input rising)

1.3 2.0 V

V

hyst

Schmitt trigger hysteresis 0.3 0.8 V

Symbol Parameter Conditions Min. Type Max Unit

V

ol

Low level input voltage

1,2

1) The output buffers are functional at V

dd3

= 2 . 7 V, but the above sp ecifications are not guaranteed at this voltage.

2) Takes into acc ount a 200 mV voltage drop in both supply lines.

I

ol

=XmA

3

3) “X” is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive
capability.

0.4 V

V

oh

High level input voltage

1,2

I

oh

=-XmA

3

2.4 V

Symbol Parameter Conditions Min. Type Max Unit

V

ol

Low level input voltage I

ol

= 100 µA 0.2 V

V

oh

High level input voltage I

oh

= -100 µAV

dd3

- 0.2 V

Drive (mA): 2 4 8
Slew Rate

(mA/ns Typical)

81632

Typical peak current
(mA)

25 50 100

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or oth erwise unde r any paten t or patent ri ghts of STMi croelectroni cs. Speci fications me ntioned in this publication are s ubj ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as critical components in life su pport device s or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

 2002 STMi croelectr oni cs - All Rights Reserved

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15/15

CB55000 Series