Page 1
1
GND
CLK
CS
DI
DO
DVD
PROG
RDY/BSY
V
REF
H1
1
2
3
4
5
6
7
10
9
8
20
19
18
17
14
13
12
11
16
15
V
REF
H4
V
REF
H4
V
REF
H3
V
REF
L1
V
REF
L2
V
REF
L4
V
REF
L3
V
OUT
1
V
OUT
2
V
OUT
3
V
OUT
4
GND
CLK
CS
DI
DO
DVD
PROG
RDY/BSY
V
REF
H1
1
2
3
4
5
6
7
10
9
8
20
19
18
17
14
13
12
11
16
15
V
REF
H4
V
REF
H4
V
REF
H3
V
REF
L1
V
REF
L2
V
REF
L4
V
REF
L3
V
OUT
1
V
OUT
2
V
OUT
3
V
OUT
4
CAT515
8-Bit Quad Digital POT with Independent Reference Inputs
FEATURES
■ Output settings retained without power
■ Independent Reference Inputs
■ Output range includes both supply rails
■ Programming voltage generated on-chip
■ 4 independently addressable outputs
■ Serial µP interface
■ Single supply operation: 2.7V-5.5V
APPLICATIONS
■ Automated product calibration.
■ Remote control adjustment of equipment
■ Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.
■ Tamper-proof calibrations.
DESCRIPTION
The CAT515 is a quad 8-Bit Memory DAC designed as
an electronic replacement for mechanical potentiometers and trim pots. Intended for final calibration of
products such as camcorders, fax machines and cellular
telephones on automated high volume production lines
and systems capable of self calibration, it is also well
suited for applications were equipment requiring periodic adjustment is either difficult to access or located in
a hazardous environment.
The CAT515 offers 4 independently programmable DACs
each having its own reference inputs and each capable
of rail to rail output swing. Output settings, stored nonvolatile EEPROM memory, are not lost when the device
is powered down and are automatically reinstated when
power is returned. Each output can be dithered to test
new output values without effecting the stored settings
and stored settings can be read back without disturbing
the DAC’s output.
GND
DAC 3
DAC 2
16
EEPROM
LATCH
EEPROM
LATCH
EEPROM
LATCH
EEPROM
LATCH
17
DAC 1
18
15
13
14
12
DAC 4
V 4
OUT
PROG
RDY/BSY
PROGRAM
CONTROL
H.V.
CHARGE
PUMP
SERIAL DATA OUTPUT
V L4
REF
V H4
REF
V 3
OUT
V L3
REF
V H3
REF
V 2
OUT
V L2
REF
V H2
REF
V 1
OUT
V L1
REF
V H1
REF
DO
V
DD
DATA
CONTROLLER
1
2
5
CLK
CS
DI
4
6
7
9
20
19
11
10
3
8
FUNCTIONAL DIAGRAM PIN CONFIGURATION
Control of the CAT515 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT515's to share a common serial interface and communications back to the host controller is via a single
serial data line thanks to the CAT515’s Tri-Stated Data
Output pin. A RDY/BSYoutput working in concert with
an internal low voltage detector signals proper operation
of EEPROM Erase/Write cycle.
The CAT515 operates from a single 3–5 volt power
supply. The high voltage required for EEPROM Erase/
Write operations is generated on-chip.
The CAT515 is available in the 0°C to 70°C Commercial
and –40°C to +85°C Industrial operating temperature
ranges and offered in 20-pin plastic DIP and Surface
mount packages.
DIP Package (P)
SOIC Package (J)
CAT515
CAT515
CAT515
© 2000 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25077-00 2/98 M-1
Page 2
CAT515
2
Doc. No. 25077-00 2/98 M-1
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
V
DD
to GND ......................................–0.5V to +7V
Inputs
CLK to GND............................–0.5V to V
DD
+0.5V
CS to GND..............................–0.5V to V
DD
+0.5V
DI to GND ...............................–0.5V to V
DD
+0.5V
RDY/BSY to GND...................–0.5V to V
DD
+0.5V
PROG to GND ........................–0.5V to V
DD
+0.5V
V
REF
H to GND ........................–0.5V to V
DD
+0.5V
V
REF
L to GND .........................–0.5V to V
DD
+0.5V
Outputs
D0 to GND...............................–0.5V to V
DD
+0.5V
V
OUT
1– 4 to GND...................–0.5V to V
DD
+0.5V
Operating Ambient Temperature
Commercial (‘C’ suffix) .................... 0°C to +70°C
Industrial (‘I’ suffix)...................... – 40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ....................... –65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
DC ELECTRICAL CHARACTERISTICS: V
DD
= +2.7V to +5.5V, V
REF
H = VDD, V
REF
L = 0V, unless otherwise specified
RELIABILITY CHARACTERISTICS
Symbol Parameter Min Max Units Test Method
V
ZAP
(1)
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
I
LTH
(1)(2)
Latch-Up 100 mA JEDEC Standard 17
Notes: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
Symbol Parameter Conditions Min Typ Max Units
Resolution 8 — — Bits
Accuracy
INL Integral Linearity Error I
LOAD
= 250 nA, TR = C — 0.6 ± 1LSB
TR = I — 0.6 ± 1LSB
I
LOAD
= 1 µA, TR = C — 1.2 — LSB
TR = I — 1.2 — LSB
DNL Differential Linearity Error I
LOAD
= 250 nA, TR = C — 0.25 ± 0.5 LSB
TR = I — 0.25 ± 0.5 LSB
I
LOAD
= 1 µA, TR = C — 0.5 — LSB
TR = I — 0.5 — LSB
Logic Inputs
I
IH
Input Leakage Current VIN = V
DD
——10µA
I
IL
Input Leakage Current VIN = 0V — — –10 µA
V
IH
High Level Input Voltage 2 — V
DD
V
V
IL
Low Level Input Voltage 0 — 0.8 V
References
V
RH
V
REF
H Input Voltage Range 2.7 — V
DD
V
V
RL
V
REF
L Input Voltage Range GND — VDD -2.7 V
Z
IN
V
REF
H–V
REF
L Resistance — 28K — Ω
∆V
IN
/ R
IN
Input Resistance Match — ± 0.5 ± 1%
Logic Outputs
V
OH
High Level Output Voltage IOH = – 40 µAV
DD
–0.3 — — V
V
OL
Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V
IOL = 0.4 mA, VDD = +3V — — 0.4 V
Page 3
CAT515
3
Doc. No. 25077-00 2/98 M-1
DC ELECTRICAL CHARACTERISTICS (Cont.):
VDD = +2.7V to +5.5V, V
REF
H = VDD, V
REF
L = 0V, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
Symbol Parameter Conditions Min Typ Max Units
Digital
t
CSMIN
Minimum CS Low Time 150 — — ns
t
CSS
CS Setup Time 100 — — ns
t
CSH
CS Hold Time 0 — — ns
t
DIS
DI Setup Time 50 — — ns
t
DIH
DI Hold Time 50 — — ns
t
DO1
Output Delay to 1 — — 150 ns
t
DO0
Output Delay to 0 — — 150 ns
t
HZ
Output Delay to High-Z — 400 — ns
t
LZ
Output Delay to Low-Z — 400 — ns
t
BUSY
Erase/Write Cycle Time — 4 5 ms
t
PS
PROG Setup Time 150 — — ns
t
PROG
Minimum Pulse Width 700 — — ns
t
CLK
H Minimum CLK High Time 500 — — ns
t
CLK
L Minimum CLK Low Time 300 — — ns
f
C
Clock Frequency DC — 1 MHz
Analog
t
DS
DAC Settling Time to 1 LSB C
LOAD
= 10 pF, VDD = +5V — 3 10 µs
C
LOAD
= 10 pF, VDD = +3V — 6 10 µs
Pin Capacitance
C
IN
Input Capacitance VIN = 0V, f = 1 MHz
(2)
—8—pF
C
OUT
Output Capacitance V
OUT
= 0V, f = 1 MHz
2)
— 6 — pFNotes
CL = 100 pF,
see note 1
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, V
REF
H = VDD, V
REF
L = 0V, unless otherwise specified
Analog Output
FSO Full-Scale Output Voltage VR = V
REF
H – V
REF
L 0.99 VR0.995 V
R
—V
ZSO Zero-Scale Output Voltage VR = V
REF
H – V
REF
L — 0.005 VR0.01 V
R
V
I
L
DAC Output Load Current — — 1 µA
R
OUT
DAC Output Impedance VDD = V
REF
H = +5V — — 100K Ω
VDD = V
REF
H = +3V — — 150K Ω
PSSR Power Supply Rejection I
LOAD
= 1 µA — — 1 LSB / V
Temperature
TC
O
V
OUT
Temperature Coefficient VDD = +5V, I
LOAD
= 250nA — — 200 µV/ °C
V
REF
H= +5V, V
REF
L = 0V
TC
REF
Temperature Coefficient of V
REF
H to V
REF
L — 700 — ppm / °C
V
REF
Resistance
Power Supply
I
DD1
Supply Current (Read) Normal Operating — 40 50 µA
I
DD2
Supply Current (Write) VDD = 5V — 1200 2000 µA
VDD = 3V — 600 1200 µA
V
DD
Operating Voltage Range 2.7 — 5.5 V
Notes: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
Page 4
CAT515
4
Doc. No. 25077-00 2/98 M-1
A. C. TIMING DIAGRAM
t
o
1 2 3 4 5
CLK
CS
DI
DO
PROG
t H
CLK
Rising CLK edge to falling CLK edge
t L
CLK
Falling CLK edge to CLK rising edge
t
CSH
Falling CLK edge for last data bit (DI)
to falling CS edge
t
CSS
Rising CS edge to next rising CLK edge
t
CSMIN
Falling CS edge to rising CS edge
t
DIS
Data valid to first rising CLK
edge after CS = high
t
DIH
Rising CLK edge to end of data valid
t
DO0
Rising CLK edge to D0 = low
tLZRising CS edge to D0 becoming high
low impedance (active output)
t
DO1
Rising CLK edge to D0 = high
t
HZ
Falling CS edge to D0 becoming high
impedance (Tri-State)
Rising PROG edge to next rising
CLK edge
Falling CLK edge after PROG=H
to
rising RDY/
BSY
edge
t H
CLK
t L
CLK
t
CSH
t
CSS
t
CSMIN
t
DIS
t
DIH
t
DO0
t
LZ
t
DO1
t
HZ
TIMING
FROM TO
MIN/MAX
Min
Min
Min
Min
Min
Min
Min
Max
(Max)
Max
(Max)
Min
Min
PARAM
NAME
RDY/BSY
t
BUSY
Rising PROG edge to falling
PROG edge
t
PS
t
PROG
t
PROG
Max
t
PS
t
o
1 2 3 4 5
t
BUSY
Page 5
CAT515
5
Doc. No. 25077-00 2/98 M-1
PIN DESCRIPTION
Pin Name Function
1V
REF
H2 Maximum DAC 2 output voltage
2V
REF
H1 Maximum DAC 1 output voltage
3V
DD
Power supply positive
4 CLK Clock input pin
5 RDY/BSY Ready/Busy output
6 CS Chip select
7 DI Serial data input pin
8 DO Serial data output pin
9 PROG EEPROM Programming Enable
Input
10 GND Power supply ground
11 V
REF
L1 Minimum DAC 1 output voltage
12 V
REF
L2 Minimum DAC 2 output voltage
13 V
REF
L3 Minimum DAC 3 output voltage
14 V
REF
L4 Minimum DAC 4 output voltage
15 V
OUT
4 DAC 4 output
16 V
OUT
3 DAC 3 output
17 V
OUT
2 DAC 2 output
18 V
OUT
1 DAC 1 output
19 V
REF
H4 Maximum DAC 4 output voltage
20 V
REF
H3 Maximum DAC 3 output voltage
DEVICE OPERATION
The CAT515 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be adjusted without altering the stored
output setting, which is useful for testing new output
settings before storing them in memory.
DIGITAL INTERFACE
The CAT515 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT515’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high impedance Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT515’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
No clock is necessary upon system power-up. The
CAT515’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
DAC addressing is as follows:
DAC OUTPUT A0 A1
V
OUT
100
V
OUT
210
V
OUT
301
V
OUT
411
Page 6
CAT515
6
Doc. No. 25077-00 2/98 M-1
As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
V
REF
V
REF
, the voltage applied between pins V
REFH &VREF
L,
sets the DAC’s Zero to Full Scale output range where
V
REF
L = Zero and V
REFH
= Full Scale. V
REF
can span the
full power supply range or just a fraction of it. In typical
applications V
REFH &VREF
L are connected across the
power supply rails. When using less than the full supply
voltage be mindfull of the limits placed on V
REF
H and
V
REF
L as specified in the "References" section of DC
"Electrical Characteristics".
READY/
BUSYBUSY
BUSYBUSY
BUSY
When saving data to non-volatile EEPROM memory, the
Ready/Busy ouput (RDY/BSY) signals the start and
duration of the EEPROM erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/
BSY goes low and remains low until the programming
cycle is complete. During this time the CAT515 will
ignore any data appearing at DI and no data will be
output on DO.
RDY/BSY is internally ANDed with a low voltage detector circuit monitoring V
DD.
If V
DD
is below the minimum
value required for EEPROM programming, RDY/BSY
will remain high following the program command indicating a failure to record the desired data in non-volatile
memory.
DATA OUTPUT
Data is output serially by the CAT515, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 515s to share a
single serial data line and simplifies interfacing multiple
515s to a microprocessor.
WRITING TO MEMORY
Programming the CAT515’s EEPROM memory is accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DAC address and eight data bits are
clocked into the DAC control register via the DI pin. Data
enters on the clock’s rising edge. The DAC output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry
takes care of generating and ramping up the programming voltage for data transfer to the EEPROM cells. The
CAT515’s EEPROM memory cells will endure over
100,000 write cycles and will retain data for a minimum
of 20 years without being refreshed.
READING DATA
Each time data is transferred into a DAC control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows µPs to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13th clock cycle completes. In doing so the EEPROM’s
Figure 1. Writing to Memory Figure 2. Reading from Memory
A0 A11
DO
DI
CS
PROG
DAC
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12
o
CURRENT
DAC VALUE
NON-VOLATILE
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DAC DATA
RDY/BSY
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DAC DATA
CURRENT DAC DATA
CURRENT
DAC VALUE
NON-VOLATILE
DAC
OUTPUT
PROG
DO
DI
CS
NEW
DAC VALUE
VOLATILE
NEW
DAC VALUE
NON-VOLATILE
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
RDY/BSY
Page 7
CAT515
7
Doc. No. 25077-00 2/98 M-1
Figure 3. Temporary Change in Output
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DAC DATA
CURRENT DAC DATA
DO
DI
CS
PROG
DAC
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
CURRENT
DAC VALUE
NON-VOLATILE
NEW
DAC VALUE
VOLATILE
CURRENT
DAC VALUE
NON-VOLATILE
RDY/BSY
setting is reloaded into the DAC control register. Since
this value is the same as that which had been there
previously no change in the DAC’s output is noticed.
Had the value held in the control register been different
from that stored in EEPROM then
a change would occur
at the read cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
The CAT515 allows temporary changes in DAC’s output
to be made without disturbing the settings retained in
EEPROM memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DAC settings may be
changed as many times as required and can be made to
any of the four DACs in any order or sequence. The
temporary setting(s) remain in effect long as CS remains
high. When CS returns low all four DACs will return to the
output values stored in EEPROM memory.
When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DAC control register prior to programming. This is because the CAT515’s internal control circuitry discards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.
Bipolar DAC Output
MSB LSB
1111 1111 —— (.98 V ) + .01 V = .990 V V = +4.90V
1000 0000 —— (.98 V ) + .01 V = .502 V V = +0.02V
0111 1111 —— (.98 V ) + .01 V = .498 V V = -0.02V
0000 0001 —— (.98 V ) + .01 V = .014 V V = -4.86V
0000 0000 —— (.98 V ) + .01 V = .010 V V = -4.90V
REF REF REF
IF
V = 5V
REF
255
255
OUT
DAC INPUT DAC OUTPUT ANALOG
R = R
OUTPUT
REF REF REF OUT
128
255
127
255
REF REF REF OUT
1
255 REF REF REF OUT
REF REF REF OUT
0
255
V = 0.99 V
FS REF
V = 0.01 V
ZERO REF
V = ——— (V - V ) + V
DAC
CODE
255
FS
ZERO ZERO
OPT 505
GND
V
DD
V H
REF
V L
REF
CONTROL
& DATA
+
–
OP 07
V = ( ) -V
OUT
R
F
R +
I
-15V
+15V
+5V
RR
I
F
R
I
IRF
V
DAC
For R =IR
F
V = 2V -V
OUT IDAC
V
i
V
OUT
Buffered DAC Output Amplified DAC Output
APPLICATION CIRCUITS
OPT 505
GND
V
DD
V H
REF
V L
REF
CONTROL
& DATA
+
–
OP 07
V
OUT
-15V
+15V
+5V
RR
I
F
V = (1 + –––) V
OUT DAC
R
F
R
I
OPT 505
GND
V
DD
V H
REF
V L
REF
CONTROL
& DATA
+
–
OP 07
V
OUT
-15V
+15V
+5V
V = V
OUT DAC
CAT515
CAT515
CAT515
Page 8
CAT515
8
Doc. No. 25077-00 2/98 M-1
APPLICATION CIRCUITS (Cont.)
Coarse-Fine Offset Control by Averaging DAC Outputs
for Single Power Supply Systems
Coarse-Fine Offset Control by Averaging DAC Outputs
for Dual Power Supply Systems
+
–
FINE ADJUST
DAC
COARSE ADJUST
DAC
GND V L
REF
V H
REF
V
DD
R
C
127R
C
+V
+5V +V
REF
-V
-V
REF
R
o
R = ———————————
C
1 µA
OFFSET
V
OFFSET
REF
(+V ) - (V )
R = ———————————
o
1 µA
OFFSETREF
(-V ) + (V )
+
+
+
–
FINE ADJUST
DAC
COARSE ADJUST
DAC
GND V L
REF
V H
REF
V
DD
R
C
127R
C
+V
+5V V
REF
R = —————
C
256 1 µA
V
REF
*
Fine adjust gives ± 1 LSB change in V
when V = ———
OFFSET
V
REF
2
OFFSET
V
OFFSET
OPT 505
LT 1029
I > 2 mA
V+
GND
V
DD
V = 5.000V
REF
V H
REF
V L
REF
CONTROL
& DATA
OPT 505
GND
V
DD
V H
REF
V L
REF
CONTROL
& DATA
+
–
15K
10 µF
5.1V
10K
4.02 K
1.00K
10 µF
35V
LM 324
1N5231B
MPT3055EL
28 - 32V
OUTPUT
0 - 25V
@ 1A
Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference
CAT515
CAT515
Page 9
CAT515
9
Doc. No. 25077-00 2/98 M-1
APPLICATION CIRCUITS (Cont.)
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
10K
+5V
WINDOW 2
10K
+5V
WINDOW 3
10K
+5V
WINDOW 4
10K
+5V
WINDOW 5
+
–
+
–
10K
+5V
WINDOW 1
GND
V L
REF
CS
DI
DO
PROG
CLK
V
PP
V
DD
V H
REF
V
REF
+5V
1.0 µF
LM 339
DAC 1
DAC 2
DAC 3
DAC 4
WINDOW 1
WINDOW 2
WINDOW 3
WINDOW 4
WINDOW 5
V
REF
V 1
OUT
V 2
OUT
V 3
OUT
V 4
OUT
GND
WINDOW STRUCTURE
OPT 505
V
IN
Staircase Window Comparator
+
–
+
–
+
–
10K
+5V
WINDOW 2
10K
+5V
WINDOW 3
+
–
+
–
10K
+5V
WINDOW 1
GND
V L
REF
CS
DI
DO
PROG
CLK
V
PP
V
DD
V H
REF
V
REF
+5V
1.0 µF
LM 339
DAC 1
DAC 2
DAC 3
DAC 4
WINDOW 1
WINDOW 2
V 1
OUT
V 2
OUT
V 3
OUT
V 4
OUT
GND
WINDOW STRUCTURE
OPT 505
V
IN
+
–
WINDOW 3
V H
REF
Overlapping Window Comparator
CAT515
CAT515
Page 10
CAT515
10
Doc. No. 25077-00 2/98 M-1
APPLICATION CIRCUITS (Cont.)
Current Sink with 4 Decades of Resolution
GND
V L
REF
V
DD
V
REF
+5V
DAC
+
–
OPT 505
CONTROL
& DATA
DAC
+
–
10K 10K
39Ω1W
LM385-2.5
5 µA steps
I = 2 - 255 mA
SINK
2N7000
10K
10K
TIP 30
39Ω 1W
5 meg
5 meg
3.9K
+
–
-15V
2N7000
+5V
+15V
4.7 µA
1 mA steps
2.2K
Current Source with 4 Decades of Resolution
GND
V L
REF
V
DD
V H
REF
+5V
DAC
+
–
OPT 505
CONTROL
& DATA
DAC
+
–
5 meg 5 meg
39Ω 1W
39Ω 1W
5 meg 5 meg
3.9K
LM385-2.5
-15V
5 µA steps
I = 2 - 255 mA
SOURCE
1 mA steps
+
–
10K
10K
+15V
TIP 29
BS170P
BS170P
51K
CAT515
CAT515
Page 11
CAT515
11
Doc. No. 25077-00 2/98 M-1
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT515JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
515 J
Product
Number
Package
P: PDIP
J: SOIC
CAT
Optional
Company ID
I
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
-TE13
Tape & Reel
TE13: 2000/Reel
Page 12
CAT515
12
Doc. No. 25077-00 2/98 M-1
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