Page 1
1
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PROG
PROGRAM
CONTROL
DI
CS
DATA
REGISTER
& EEPROM
13
CLK
SERIAL
CONTROL
DAC 2
DAC 3
DAC 4
11
10
6
V 1
OUT
V 2
OUT
V 3
OUT
V 4
OUT
DO
SERIAL
DATA
OUTPUT
REGISTER
89
GND
V L
REF
V H
REF
V
PP
V
DD
3114
7
5
2
4
DAC 1
12
FEATURES
■ Output settings retained without power
■ Output range includes both supply rails
■ 4 independently addressable outputs
■ 1 LSB Accuracy
■ Serial µP interface
■ Single supply operation: 2.7V-5.5V
■ Setting read-back without effecting outputs
APPLICATIONS
■ Automated product calibration.
■ Remote control adjustment of equipment
■ Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.
■ Tamper-proof calibrations.
DESCRIPTION
The CAT504 is a quad 8-Bit Memory DAC designed as
an electronic replacement for mechanical potentiometers and trim pots. Intended for final calibration of
products such as camcorders, fax machines and cellular
telephones on automated high volume production lines,
it is also well suited for systems capable of self calibration, and applications where equipment which is either
difficult to access or in a hazardous environment, requires periodic adjustment.
The 4 independently programmable DAC's have an
output range which includes both supply rails. Output
settings, stored in non-volatile EEPROM memory, are
not lost when the device is powered down and are
automatically reinstated when power is returned. Each
output can be dithered to test new output values without
effecting the stored settings and stored settings can be
read back without disturbing the DAC’s output.
Control of the CAT504 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT504s to share a common serial interface and communication back to the host controller is via a single
serial data line thanks to the CAT504’s Tri-Stated Data
Output pin.
The CAT504 operates from a single 3–5 volt power
supply drawing just a few milliwatts of power. When
storing data in EEPROM memory an additional 20 volt
low current supply is required.
The CAT504 is available in the 0 to 70° C Commercial
and –40° C to + 85° C Industrial operating temperature
ranges and offered in 14-pin plastic DIP and Surface
mount packages.
FUNCTIONAL DIAGRAM PIN CONFIGURATION
CAT504
8-Bit Quad DACpot
DIP Package (P) SOIC Package (J)
CAT504
V
PP
CLK
CS
PROG
DI
DO
V
DD
2
3
4
13
12
11
5
6
7
10
9
8
114
GND
V
REF
H
V
OUT
1
V
OUT
2
V
OUT
3
V
OUT
4
V
REF
L
V
PP
CLK
CS
PROG
DI
DO
V
DD
2
3
4
13
12
11
5
6
7
10
9
8
114
GND
V
REF
H
V
OUT
1
V
OUT
2
V
OUT
3
V
OUT
4
V
REF
L
CAT
504
CAT
504
Doc. No. 25048-0A 2/98 M-1
Page 2
CAT504
2Doc. No. 25048-0A 2/98 M-1
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage
VDD to GND ......................................–0.5V to +7V
VPP to GND.....................................–0.5V to +22V
Inputs
CLK to GND............................–0.5V to V
DD
+0.5V
CS to GND..............................–0.5V to V
DD
+0.5V
DI to GND ...............................–0.5V to V
DD
+0.5V
PROG to GND ........................–0.5V to V
DD
+0.5V
V
REF
H to GND ........................–0.5V to V
DD
+0.5V
V
REF
L to GND.........................–0.5V to V
DD
+0.5V
Outputs
D0 to GND...............................–0.5V to V
DD
+0.5V
V
OUT
1– 4 to GND...................–0.5V to V
DD
+0.5V
Operating Ambient Temperature
Commercial (‘C’ suffix) .................... 0°C to +70°C
Industrial (‘I’ suffix)...................... – 40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ....................... –65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol Parameter Min Max Units Test Method
V
ZAP
(1)
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
I
LTH
(1)(2)
Latch-Up 100 mA JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
Logic Inputs
I
IH
Input Leakage Current VIN = V
DD
——10µA
I
IL
Input Leakage Current VIN = 0V — — –10 µA
V
IH
High Level Input Voltage 2 — V
DD
V
V
IL
Low Level Input Voltage 0 — 0.8 V
References
V
RH
V
REF
H Input Voltage Range 2.7 — V
DD
V
V
RL
V
REF
L Input Voltage Range GND — V
DD
-2.7 V
Z
IN
V
REF
H–V
REF
L Resistance — 7k — Ω
Logic Outputs
V
OH
High Level Output Voltage IOH = – 40 µAV
DD
–0.3 — — V
V
OL
Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V
IOL = 0.4 mA, VDD = +3V — — 0.4 V
Symbol Parameter Conditions Min Typ Max Units
Resolution 8 — — Bits
Accuracy
INL Integral Linearity Error I
LOAD
= 250 nA, TR = C — — ± 1 LSB
TR = I — — ± 1 LSB
I
LOAD
= 1 µA, TR = C — — ± 2 LSB
TR = I — — ± 2 LSB
DNL Differential Linearity Error I
LOAD
= 250 nA, TR = C — — ± 0.5 LSB
TR = I — — ± 0.5 LSB
I
LOAD
= 1 µA, TR = C — — ± 1.5 LSB
TR = I — — ± 1.5 LSB
DC ELECTRICAL CHARACTERISTICS:
VDD = 2.7V to 5.5V, V
REF
H = VDD, V
REF
L = 0V, unless otherwise specified
Page 3
CAT504
3
Doc. No. 25048-0A 2/98 M-1
DC ELECTRICAL CHARACTERISTICS (Cont.):
VDD = 2.7V to 5.5V, V
REF
H = +VDD, V
REF
L = 0V, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
Symbol Parameter Conditions Min Typ Max Units
Digital
t
CSMIN
Minimum CS Low Time 150 — — ns
t
CSS
CS Setup Time 100 — — ns
t
CSH
CS Hold Time 0 — — ns
t
DIS
DI Setup Time 50 — — ns
t
DIH
DI Hold Time 50 — — ns
t
DO1
Output Delay to 1 — — 150 ns
t
DO0
Output Delay to 0 — — 150 ns
t
HZ
Output Delay to High-Z — 400 — ns
t
LZ
Output Delay to Low-Z — 400 — ns
t
PROG
Erase/Write Pulse Width 3 5 — ms
t
PS
PROG Setup Time 150 — — ns
t
CLK
H Minimum CLK High Time 500 — — ns
t
CLK
L Minimum CLK Low Time 300 — — ns
f
C
Clock Frequency DC — 1 MHz
Analog
t
DS
DAC Settling Time to 1/2 LSB C
LOAD
= 10 pF, VDD = +5V — 3 10 µs
C
LOAD
= 10 pF, VDD = +3V — 6 10 µs
Pin Capacitance
C
IN
Input Capacitance VIN = 0V, f = 1 MHz
(2)
—8—pF
C
OUT
Output Capacitance V
OUT
= 0V, f = 1 MHz
(2)
—6—pF
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
CL = 100 pF
see note 1
AC ELECTRICAL CHARACTERISTICS:
VDD = 2.7V to 5.5V, V
REF
H = +VDD, V
REF
L = 0V, unless otherwise specified
Analog Output
FSO Full-Scale Output Voltage VR = V
REF
H–V
REF
L 0.99 VR0.995 V
R
—V
ZSO Zero-Scale Output Voltage VR = V
REF
H–V
REF
L — 0.005 VR0.10 V
R
V
I
L
DAC Output Load Current — — 1 µA
R
OUT
DAC Output Impedance VDD = +5V — — 20k Ω
VDD = +3V — — 40k Ω
PSSR Power Supply Rejection I
LOAD
= 250 nA — — 1 LSB / V
Temperature
TC
O
V
OUT
Temperature Coefficient V
REF
H = +5V, V
REF
L = 0V — — 200 µV/ °C
VDD = +5V, I
LOAD
= 250nA
TC
REF
Temperature Coefficient of V
REF
H to V
REF
L — 700 — ppm / °C
V
REF
Resistance
Power Supply
I
DD
Supply Current Excludes V
REF
——50µA
I
PP
Programming Current VPP = +19V — 200 500 µA
V
DD
Operating Voltage Range 2.7 — 5.5 V
V
PP
Programing Voltage Range 18 19 20 V
Page 4
CAT504
4Doc. No. 25048-0A 2/98 M-1
t
o
1 2 3 4 5
t
o
1 2 3 4 5
CLK
CS
DI
DO
PROG
t H
CLK
Rising CLK edge to falling CLK edge
t L
CLK
Falling CLK edge to CLK rising edge
t
CSH
Falling CLK edge for last data bit (DI)
to falling CS edge
t
CSS
Rising CS edge to next rising CLK edge
t
CSMIN
Falling CS edge to rising CS edge
t
DIS
Data valid to first rising CLK
edge after CS = high
t
DIH
Rising CLK edge to end of data valid
t
DO0
Rising CLK edge to D0 = low
t
LZ
Rising CS edge to D0 becoming high
low impedance (active output)
t
DO1
Rising CLK edge to D0 = high
t
HZ
Falling CS edge to D0 becoming high
impedance (Tri-State)
t
PS
Rising PROG edge to next rising
CLK edge
t
PROG
Rising PROG edge to falling PROG
edge
t H
CLK
t L
CLK
t
CSH
t
CSS
t
CSMIN
t
DIS
t
DIH
t
DO0
t
LZ
t
DO1
t
PS
t
HZ
t
PROG
TIMING
FROM TO
MIN/MAX
Min
Min
Min
Min
Min
Min
Min
Max
(Max)
Max
(Max)
Min
Min
PARAM
NAME
A. C. TIMING DIAGRAM
Page 5
CAT504
5
Doc. No. 25048-0A 2/98 M-1
PIN DESCRIPTION
Pin Name Function
1VDDPower supply positive.
2 CLK Clock input pin
3VPPEEPROM Programming Voltage
4 CS Chip Select
5 DI Serial data input pin.
6 DO Serial data output pin.
7 PROG EEPROM Programming Enable
Input
8 GND Power supply ground.
9V
REF
L Minimum DAC output voltage.
10 V
OUT
4 DAC output channel 4.
11 V
OUT
3 DAC output channel 3.
12 V
OUT
2 DAC output channel 2.
13 V
OUT
1 DAC output channel 1.
14 V
REF
H Maximum DAC output voltage.
DEVICE OPERATION
The CAT504 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be temporarily adjusted without changing the stored output setting, which is useful for testing
new output settings before storing them in memory.
DIGITAL INTERFACE
The CAT504 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT504’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high impedance Tri-State mode.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT504’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
No clock is necessary upon system power-up. The
CAT504’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
DAC addressing is as follows:
DAC OUTPUT A0 A1
V
OUT
1 0 0
V
OUT
2 1 0
V
OUT
3 0 1
V
OUT
4 1 1
Page 6
CAT504
6Doc. No. 25048-0A 2/98 M-1
CS high, a start bit followed by a two bit DAC address
and eight data bits are clocked into the DAC control
register via the DI pin. Data enters on the clock’s rising
edge. The DAC output changes to its new setting on the
clock cycle following D7, the last data bit.
Programming is achieved by bringing PROG high for a
minimum of 3 ms while supplying 18 to 20 volts to the V
PP
pin. PROG must be brought high sometime after the
start bit and at least 150 ns prior to the rising edge of the
clock cycle immediately following the D7 bit. Two clock
cycles after the D7 bit the DAC control register will be
ready to receive the next set of address and data bits.
The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of
ramping the programming voltage for data transfer to the
EEPROM cells. The CAT504’s EEPROM memory cells
will endure over 100,000 write cycles and will retain data
for a minimum of 20 years without being refreshed.
READING DATA
Each time data is transferred into a DAC control register
currently held data is shifted out via the DI pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows µPs to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13th clock cycle completes. In doing so the EEPROM’s
setting is reloaded into the DAC control register. Since
this value is the same as that which had been there
previously no change in the DAC’s output is noticed.
Had the value held in the control register been different
from that stored in EEPROM then
a change would occur
at the read cycle’s conclusion.
V
REF
V
REF
, the voltage applied between pins V
REFH
andV
REF
L,
sets the DAC’s Zero to Full Scale output range where
V
REF
L = Zero and V
REFH
= Full Scale. V
REF
can span the
full power supply range or just a fraction of it. In typical
applications V
REFH
andV
REF
L are connected across the
power supply rails. When using less than the full supply
voltage V
REF
H is restricted to voltages between VDD and
VDD/2 and V
REF
L to voltages between GND and VDD/2.
V
PP
When saving data to non-volatile EEPROM memory an
external voltage of 18–20 volts must be applied to the
VPP pin. This voltage need only be present during the
programming cycle and may be removed or turned off
the remainder of the time. While it is not necessary to
remove or power down VPP between programming
cycles, some power sensitive applications may choose
to do so. In such cases, the VPP supply must be given
sufficient time to come up and stabilize before issuing
the PROG command.
DATA OUTPUT
Data is output serially by the CAT504, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 504s to share a
single serial data line and simplifies interfacing multiple
504s to a microprocessor.
WRITING TO MEMORY
Programming the CAT504’s EEPROM memory is accomplished through the application of an externally
generated programming voltage, VPP, and the control
signals: Chip Select (CS) and Program (PROG). With
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DAC DATA
CURRENT DAC DATA
CURRENT
DAC VALUE
NON-VOLATILE
DAC
OUTPUT
PROG
Vpp
DO
DI
CS
NEW
DAC VALUE
VOLATILE
NEW
DAC VALUE
NON-VOLATILE
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
DON'T CARE
o
A0 A11
DO
DI
CS
Vpp
PROG
DAC
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12
o
CURRENT
DAC VALUE
NON-VOLATILE
DON'T CARE
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DAC DATA
Figure 2. Reading from MemoryFigure 1. Writing to Memory
Page 7
CAT504
7
Doc. No. 25048-0A 2/98 M-1
APPLICATION CIRCUITS
Buffered DAC Output Amplified DAC Output
TEMPORARILY CHANGE OUTPUT
The CAT504 allows temporary changes in DAC’s output
to be made without disturbing the settings retained in
EEPROM memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DAC settings may be
changed as many times as required and can be made to
any of the four DACs in any order or sequence. The
temporary setting(s) remain in effect long as CS remains
high. When CS returns low all four DACs will return to the
output values stored in EEPROM memory.
When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DAC control register prior to programming. This is because the CAT504’s internal control circuitry discards
the new data from the programming register two clock
cycles after receiving it (after reception is complete) if no
PROG signal is received.
Bipolar DAC Output
OPT 504
GND
V
DD
V H
REF
V L
REF
CONTROL
& DATA
+
–
OP 07
V
OUT
-15V
+15V
+5V
V = V
OUT DAC
OPT 504
GND
V
DD
V H
REF
V L
REF
CONTROL
& DATA
+
–
OP 07
V
OUT
-15V
+15V
+5V
RR
i
F
V = (1 + –––) V
OUT DAC
R
F
R
I
OPT 504
GND
V
DD
V H
REF
V L
REF
CONTROL
& DATA
+
–
OP 07
V = ( ) -V
OUT
R
F
R +
i
-15V
+15V
+5V
RR
i
F
R
i
iRF
V
DAC
For R =iR
F
V = 2V -V
OUT iDAC
V
i
V
OUT
MSB LSB
1111 1111 —— (.98 V ) + .01 V = .990 V V = +4.90V
1000 0000 —— (.98 V ) + .01 V = .502 V V = +0.02V
0111 1111 —— (.98 V ) + .01 V = .498 V V = -0.02V
0000 0001 —— (.98 V ) + .01 V = .014 V V = -4.86V
0000 0000 —— (.98 V ) + .01 V = .010 V V = -4.90V
REF REF REF
IF
V = 5V
REF
255
255
OUT
DAC INPUT DAC OUTPUT ANALOG
R = R
OUTPUT
REF REF REF OUT
128
255
127
255
REF REF REF OUT
1
255 REF REF REF OUT
REF REF REF OUT
0
255
V = 0.99 V
FS REF
V = 0.01 V
ZERO REF
V = ——— (V - V ) + V
DAC
CODE
255
FS
ZERO ZERO
Figure 3. Temporary Change in Output
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DAC DATA
CURRENT DAC DATA
DO
DI
CS
Vpp
PROG
DAC
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
CURRENT
DAC VALUE
NON-VOLATILE
NEW
DAC VALUE
VOLATILE
CURRENT
DAC VALUE
NON-VOLATILE
DON'T CARE
CAT504
CAT504
CAT504
Page 8
CAT504
8Doc. No. 25048-0A 2/98 M-1
APPLICATION CIRCUITS (Cont.)
Coarse-Fine Offset Control by Averaging DAC Outputs
for Single Power Supply Systems
Coarse-Fine Offset Control by Averaging DAC Outputs
for Dual Power Supply Systems
+
–
FINE ADJUST
DAC
COARSE ADJUST
DAC
GND V L
REF
V H
REF
V
DD
R
C
127R
C
+V
+5V V
REF
R = —————
C
256 1 µA
V
REF
*
Fine adjust gives ± 1 LSB change in V
when V = ———
OFFSET
V
REF
2
OFFSET
V
OFFSET
+
–
FINE ADJUST
DAC
COARSE ADJUST
DAC
GND V L
REF
V H
REF
V
DD
R
C
127R
C
+V
+5V +V
REF
-V
-V
REF
R
o
R = ———————————
C
1 µA
OFFSET
V
OFFSET
REF
(+V ) - (V )
R = ———————————
o
1 µA
OFFSETREF
(-V ) + (V )
+
+
Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference
OPT 504
LT 1029
I > 2 mA
V+
GND
V
DD
V = 5.000V
REF
V H
REF
V L
REF
CONTROL
& DATA
OPT 504
GND
V
DD
V H
REF
V L
REF
CONTROL
& DATA
+
–
15K
10 µF
5.1V
10K
4.02 K
1.00K
10 µF
35V
LM 324
1N5231B
MPT3055EL
28 - 32V
OUTPUT
0 - 25V
@ 1A
CAT504 CAT504
Page 9
CAT504
9
Doc. No. 25048-0A 2/98 M-1
APPLICATION CIRCUITS (Cont.)
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
10K
+5V
WINDOW 2
10K
+5V
WINDOW 3
10K
+5V
WINDOW 4
10K
+5V
WINDOW 5
+
–
+
–
10K
+5V
WINDOW 1
GND
V L
REF
CS
DI
DO
PROG
CLK
V
PP
V
DD
V H
REF
V
REF
+5V
1.0 µF
LM 339
DAC 1
DAC 2
DAC 3
DAC 4
WINDOW 1
WINDOW 2
WINDOW 3
WINDOW 4
WINDOW 5
V
REF
V 1
OUT
V 2
OUT
V 3
OUT
V 4
OUT
GND
WINDOW STRUCTURE
OPT 504
V
IN
Staircase Window Comparator
Overlapping Window Comparator
+
–
+
–
+
–
10K
+5V
WINDOW 2
10K
+5V
WINDOW 3
+
–
+
–
10K
+5V
WINDOW 1
GND
V L
REF
CS
DI
DO
PROG
CLK
V
PP
V
DD
V H
REF
V
REF
+5V
1.0 µF
LM 339
DAC 1
DAC 2
DAC 3
DAC 4
WINDOW 1
WINDOW 2
V 1
OUT
V 2
OUT
V 3
OUT
V 4
OUT
GND
WINDOW STRUCTURE
OPT 504
V
IN
+
–
WINDOW 3
V H
REF
CAT504
CAT504
Page 10
CAT504
10Doc. No. 25048-0A 2/98 M-1
APPLICATION CIRCUITS (Cont.)
Current Sink with 4 Decades of Resolution
Current Source with 4 Decades of Resolution
GND
V L
REF
V
DD
V
REF
+5V
DAC
+
–
OPT 504
CONTROL
& DATA
DAC
+
–
10K 10K
39Ω1W
LM385-2.5
5 µA steps
I = 2 - 255 mA
SINK
2N7000
10K
10K
TIP 30
39Ω 1W
5 meg
5 meg
3.9K
+
–
-15V
2N7000
+5V
+15V
4.7 µA
1 mA steps
2.2K
GND
V L
REF
V
DD
V H
REF
+5V
DAC
+
–
OPT 504
CONTROL
& DATA
DAC
+
–
5 meg 5 meg
39Ω 1W
39Ω 1W
5 meg 5 meg
3.9K
LM385-2.5
-15V
5 µA steps
I = 2 - 255 mA
SOURCE
1 mA steps
+
–
10K
10K
+15V
TIP 29
BS170P
BS170P
51K
CAT504
CAT504
Page 11
CAT504
11
Doc. No. 25048-0A 2/98 M-1
APPLICATION CIRCUITS (Cont.)
V
pp
CS
PROG
DI
DO
CLK
V
DD
V H
REF
V L
REF
V 3
OUT
V 2
OUT
V 1
OUT
V 4
OUT
GND
14
1
13
12
11
10
9
8
4
7
5
6
2
3
47K
47K
47K
47K
1.0 µF
0.22µF0.22µF0.22µF0.22
µF
14
11
5
16
9
23
3
22
1
7
18
17
21
24
12
OUT 2
15
OUT 1
10
13
4
8
+12V
V
CC
TREB CAP
BASS CAP
OUTPUT 1
BYPASS
OUTPUT 2
TREB CAP
BASS CAP
GND
GND
STEREO
ENHANCE
IN 2
VOLUME
BALANCE
TREBLE
BASS
LOUDNESS
V
IN 1
Z
19
2
LM1040
OPT 504
CHIP SELECT.
PROGRAM
DATA IN
DATA OUT
CLOCK
INPUT 2
20V
IN5250B
2.5 µF
INPUT 1
1.0 µF
1N914
1N914
+12V
.005 µF
10K
74C14
0.47 µF
0.47 µF
0.1 µF
4.7K
0.1 µF
0.01 µF
0.39 µF
47 µF
10 µF
10 µF
0.39 µF
0.01 µF
Digital Stereo Control
CAT504
Page 12
CAT504
12Doc. No. 25048-0A 2/98 M-1
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT504JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
504 J
Product
Number
Package
P: PDIP
J: SOIC
CAT
Optional
Company ID
I
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
-TE13
Tape & Reel
TE13: 2000/Reel
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