Datasheet CAT34WC02U-1.8TE13, CAT34WC02PI-TE13, CAT34WC02PI-1.8TE13, CAT34WC02PA-TE13, CAT34WC02PA-1.8TE13 Datasheet (CTLST)

CAT34WC02

2K-Bit I2C Serial EEPROM, Serial Presence Detect

FEATURES

■ 400 KHz (5V) and 100 KHz (1.8V) I

2

C bus

compatible

■ 1.8 to 6.0 volt operation

■ Low power CMOS technology

– zero standby current

■ 16-byte page write buffer

■ Commercial, industrial and automotive

temperature ranges

DESCRIPTION

The CAT34WC02 is a 2K-bit Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de­vice power requirements. The CAT34WC02 features a

PIN CONFIGURATION

DIP Package (P)

A

0

A

1

A

2

V

SS

A

0

A

1

A

2

V

SS

1

8

V

2
3
4

CC

7

WP

6

SCL

5

SDA

TSSOP Package (U)

1
2
3
4

8
7
6
5

SOIC Package (J)

0
1
2

V
WP
SCL
SDA

1
2
3
4

CC

A
A
A

V

SS

8

V

CC

7

WP

6

SCL

5

SDA

■ Self-timed write cycle with auto-clear

■ Software write protection for lower 128 bytes

■ 1,000,000 program/erase cycles

■ 100 year data retention

■ 8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages

■ 256 x 8 memory organization

■ Hardware write protect

16-byte page write buffer. The device operates via the
I2C bus serial interface and is available in 8-pin DIP, 8­pin SOIC or 8-pin TSSOP packages.

BLOCK DIAGRAM

EXTERNAL LOAD

SENSE AMPS

SHIFT REGISTERS

COLUMN

DECODERS

E2PROM

V

CC

V

SS

SDA

WP

D

OUT

ACK

WORD ADDRESS

BUFFERS

START/STOP

LOGIC

CONTROL

LOGIC

XDEC

PIN FUNCTIONS

Pin Name Function

A0, A1, A2 Device Address Inputs
SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
V

CC

V

SS

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

+1.8V to +6.0V Power Supply
Ground

SCL

A

0

A1
A2

1

STATE COUNTERS
SLAVE

ADDRESS
COMPARATORS

DATA IN STORAGE

HIGH VOL TAGE/

TIMING CONTROL

24CXX F03

Doc No. 1003, Rev. A

CAT34WC02

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

(1)

Respect to Ground

........... –2.0V to +V

VCC with Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

CC

+ 2.0V

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and

reliability.

Lead Soldering Temperature (10 secs)............ 300°C

Output Short Circuit Current

(2)

........................ 100mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

(3)

N
T
V
I

LTH

END
DR
ZAP

(3)

(3)

(3)(4)

Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 100 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I

CC

I

CC

I

SB

I

LI

I

LO

V

IL

V

IH

V

OL1

V

OL2

Power Supply Current (Read) 1 mA f
Power Supply Current (Write) 3 mA f

(5)

Standby Current (VCC = 5.0V) 0 µAVIN = GND or V
Input Leakage Current 1 µAVIN = GND to V
Output Leakage Current 1 µAV
Input Low Voltage –1 VCC x 0.3 V
Input High Voltage VCC x 0.7 VCC + 1.0 V
Output Low Voltage (VCC = 3.0V) 0.4 V IOL = 3 mA
Output Low Voltage (VCC = 1.8V) 0.5 V IOL = 1.5 mA

= 100 KHz

SCL

= 100 KHz

SCL

= GND to V

OUT

CC
CC

CC

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Max. Units Conditions

(3)

C

I/O

(3)

C

IN

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby Current (ISB) = 0µA (<900nA).

Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (A0, A1, A2, SCL) 6 pF V

I/O

IN

= 0V

= 0V

Doc. No. 1003, Rev. A

2

A.C. CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Read & Write Cycle Limits

Symbol Parameter 1.8V, 2.5V 4.5V-5.5V

Min. Max. Min. Max. Units

CAT34WC02

F

SCL

(1)

T

I

t

AA

t

BUF

t

HD:STA

t

LOW

t

HIGH

t

SU:STA

t

HD:DAT

t

SU:DAT

(1)

t

R

(1)

t

F

t

SU:STO

t

DH

(1)

Clock Frequency 100 400 kHz
Noise Suppression Time 200 200 ns

Constant at SCL, SDA Inputs
SCL Low to SDA Data Out 3.5 1 µs

and ACK Out
Time the Bus Must be Free Before 4.7 1.2 µs

a New Transmission Can Start
Start Condition Hold Time 4 0.6 µs
Clock Low Period 4.7 1.2 µs
Clock High Period 4 0.6 µs
Start Condition Setup Time 4.7 0.6 µs

(for a Repeated Start Condition)
Data In Hold Time 0 0 ns
Data In Setup Time 50 50 ns
SDA and SCL Rise Time 1 0.3 µs
SDA and SCL Fall Time 300 300 ns
Stop Condition Setup Time 4 0.6 µs
Data Out Hold Time 100 100 ns

Power-Up Timing

(1)(2)

Symbol Parameter Max. Units

t

PUR

t

PUW

Power-up to Read Operation 1 ms
Power-up to Write Operation 1 ms

Write Cycle Limits

Symbol Parameter Min. Typ. Max Units

t

WR

The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t

PUR

and t

are the delays required from the time VCC is stable until the specified operation can be initiated.

PUW

Write Cycle Time 4 10 ms

interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.

3

Doc No. 1003, Rev. A

CAT34WC02

FUNCTIONAL DESCRIPTION

The CAT34WC02 supports the I2C Bus data transmis­sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re­ceiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT34WC02
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated. A
maximum of 8 devices may be connected to the bus as
determined by the device address inputs A0, A1, and A2.

PIN DESCRIPTIONS

SCL: Serial Clock

The CAT34WC02 serial clock input pin is used to clock

Figure 1. Bus Timing

SCL

t

SU:STA

t

F

t

LOW

t

HD:STA

t

HIGH

t

HD:DAT

all data transfers into or out of the device. This is an input
pin.

SDA: Serial Data/Address
The CAT34WC02 bidirectional serial data/address pin
is used to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.

A0, A1, A2: Device Address Inputs
These inputs set device address when cascading mul­tiple devices. A maximum of eight devices can be
cascaded when using the device.

WP: Write Protect
This input, when tied to GND, allows write operations to

the entire memory. For CAT34WC02 when this pin is
tied to VCC, the entire array of memory is write protected.
When left floating, memory is unprotected.

t

R

t

LOW

t

SU:DAT

t

SU:STO

SDA IN

SDA OUT

Figure 2. Write Cycle Timing

SCL

SDA

BYTE n

Figure 3. Start/Stop Timing

SDA

t

t

AA

ACK8TH BIT

STOP
CONDITION

t

DH

t

WR

START
CONDITION

BUF

5020 FHD F03

ADDRESS

5020 FHD F04

Doc. No. 1003, Rev. A

SCL

START BIT

STOP BIT

5020 FHD F05

4

CAT34WC02

I2C BUS PROTOCOL

The following defines the features of the I2C bus proto­col:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.

START Condition

The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT34WC02 monitor the
SDA and SCL lines and will not respond until this
condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed
(except when accessing the Write Protect Register) as
1010 for the CAT34WC02 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits

and define which device the Master is accessing. Up to
eight CAT34WC02 may be individually addressed by
the system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.

After the Master sends a START condition and the slave
address byte, the CAT34WC02 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT34WC02 then performs a Read or a Write operation
depending on the state of the R/W bit.

Acknowledge

After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg­ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.

The CAT34WC02 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.

When the CAT34WC02 begins a READ mode, it trans­mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac­knowledge, the CAT34WC02 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.

Figure 4. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 5. Slave Address Bits

1

0 1 1 0 A2 A1 A0 R/W

1

START

0 1 0 A2 A1 A0 R/W

DEVICE ADDRESS

5

89

ACKNOWLEDGE

Normal Read and Write

Programming the Write
Protect Register

5020 FHD F06

34WC02 F07

Doc No. 1003, Rev. A

CAT34WC02

WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT34WC02. After receiving another
acknowledge from the Slave, the Master device trans­mits the data byte to be written into the addressed
memory location. The CAT34WC02 acknowledges once
more and the Master generates the STOP condition, at
which time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.

Page Write

The CAT34WC02 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT34WC02 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain un­changed.

Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT34WC02 in a single write cycle.

Acknowledge Polling

The disabling of the inputs can be used to take advan­tage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT34WC02 initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT34WC02 is still
busy with the write operation, no ACK will be returned.
If the CAT34WC02 has completed the write operation,
an ACK will be returned and the host can then proceed
with the next read or write operation.

WRITE PROTECTION

The CAT34WC02 is designed with a hardware protect
pin that enables the user to protect the entire memory.
The CAT34WC02 also has a software write protection
feature. By programming the software write protection
register, the first 128 bytes are write protected. The
software and hardware protection features of the
CAT34WC02 are designed into the part to provide

added flexibility to the design engineers.

If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be overwrit­ten.

Figure 6. Byte Write Timing

BUS ACTIVITY:

MASTER

SDA LINE

S
T
A
R
T

S

SLAVE

ADDRESS

Figure 7. Page Write Timing

S
T

BUS ACTIVITY :

MASTER

SDA LINE

A
R
T

S

SLAVE

ADDRESS

BYTE

ADDRESS (n)

*

A

C

K

Hardware

The write protection feature of CAT34WC02 allows the
user to protect against inadvertent programming of the
memory array. If the WP pin is tied to Vcc, the entire

S
T
O
P

P

A
C
K

DATA n+P

A
C
K

A
C
K

A
C
K

BYTE

ADDRESS

DATA n

A
C
K

A
C
K

DATA

DATA n+1

5020 FHD F08

S
T
O
P

P

A
C
K

Doc. No. 1003, Rev. A

NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0

6

5020 FHD F09

CAT34WC02

K

memory array is protected and becomes read only. The
entire memory becomes write protected regardless of
whether the write protect register has been written or
not. When WP pin is tied to Vcc, the user cannot program
the write protect register. If the WP pin is left floating or
tied to Vss, the device can be written into (except the first
128 bytes if the write protect register is programmed).

Software

The software protection on the CAT34WC02 protects
the first 128 bytes of the memory array permanently.
Software write protect is implemented by programming
the write protect register.

A user can write only once to
the write protect register and once written it is irrevers­ible (even if you reset the CAT34WC02).

The write protection register is written by sending a
regular byte write command with the slave address set
to 0110 instead of 1010. After the initial acess to the
register, the device will not acknowledge any further
access to this register.

READ OPERATIONS

The READ operation for the CAT34WC02 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.

Immediate Address Read

The CAT34WC02’s address counter contains the ad­dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac­cess data from address N+1. If N = 255 for 34WC02,
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT34WC02 re-

ceives its slave address information (with the R/W bit set
to one), it issues an acknowledge, then transmits the 8­bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.

Selective Read

Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT34WC02 acknowledge the word
address, the Master device resends the START condi­tion and the slave address, this time with the R/W bit set
to one. The CAT34WC02 then responds with its ac­knowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT34WC02 sends the initial 8-bit
data requested, the Master will respond with an ac­knowledge which tells the device it requires more data.
The CAT34WC02 will continue to output a byte for each
acknowledge sent by the Master. The operation will
terminate operation when the Master fails to respond
with an acknowledge, thus sending the STOP condition.

The data being transmitted from the CAT34WC02 is
outputted sequentially with data from address N fol­lowed by data from address N+1. The READ operation
address counter increments all of the CAT34WC02
address bits so that the entire memory array can be read
during one operation. If more than the 256 bytes are read
out, the counter will “wrap around” and continue to clock
out data bytes.

Figure 8. Immediate Address Read Timing

BUS ACTIVITY:

SCL

SDA 8TH BIT

89

MASTER

SDA LINE

S
T
A
R
T

S

7

SLAVE

ADDRESS

S
T
O
P

P

A

DATA

C
K

N
O

A
C
K

STOPNO ACKDATA OUT

5020 FHD F10

Doc No. 1003, Rev. A

CAT34WC02

Figure 9. Memory Array

Figure 10. Software Write Protect

FFH

7FH

00H

Hardware Write Protectable
(by connecting WP pin to
Vcc)

Software Write Protectable
(by programming the write
protect register)

BUS ACTIVITY :

MASTER

SDA LINE

Figure 11. Selective Read Timing

S
T
A

BUS ACTIVITY:

MASTER

SDA LINE

R
T

S

SLAVE

ADDRESS

S
T
A
R
T

S

SLAVE

ADDRESS

ADDRESS (n)

*

A

C

K

BYTE

ADDRESS

XXXXXXX XXXXXXX

XX

A

C

K

BYTE

X = Don't Care

S
T
A

R

T

S

A
C
K

A
C
K

SLAVE

ADDRESS

DATA

A
C
K

S
T
O
P

P

A
C
K

DATA n

S
T

O

P

P

N
O

A

C

K

5020 FHD F11

Figure 12. Sequential Read Timing

BUS ACTIVITY:

MASTER

SDA LINE

Doc. No. 1003, Rev. A

SLAVE

ADDRESS

A
C
K

A

C

K

DATA n+1

8

A
C
K

DATA n+2

S
T

N
O

A
C
K

O
P

P

5020 FHD F12

DATA n+xDATA n

A
C
K

ORDERING INFORMATION

Prefix Device # Suffix

CAT34WC02

CAT

Optional
Company ID

34WC02

Product
Number

J

I

Temperature Range

Blank = Commercial (0˚C to +70˚C)

-1.8

TE13

Tape & Reel

TE13: 2000/Reel
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ - 105˚C)*

Package

P: PDIP
J: SOIC (JEDEC)

Operating V oltage

Blank: 2.5V - 6.0V

1.8: 1.8V - 6.0V

U: TSSOP

* -40˚ to +125˚C is available upon request

Notes:
(1) The device used in the above example is a 34WC02JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating

Voltage, Tape & Reel)

34WC02 F14

9

Doc No. 1003, Rev. A

Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: [phone]
Fax: [phone]
www.catsemi.com

Publication #: 1003
Revison: A
Issue date: 04/25/01
Type: Final