Datasheet CAT28F001TI-90TT, CAT28F001TI-90BT, CAT28F001TI-70TT, CAT28F001TI-70BT, CAT28F001TI-15TT Datasheet (CTLST)

CAT28F001

1 Megabit CMOS Boot Block Flash Memory

FEATURES

Licensed Intel

second source

■ Fast Read Access Time: 70/90/120/150 ns

■ On-Chip Address and Data Latches

■ Blocked Architecture

— One 8 KB Boot Block w/ Lock Out

• Top or Bottom Locations
— Two 4 KB Parameter Blocks
— One 112 KB Main Block

■ Low Power CMOS Operation

■ 12.0V ± 5% Programming and Erase Voltage

■ Automated Program & Erase Algorithms

■ High Speed Programming

■ Commercial, Industrial and Automotive

Temperature Ranges

DESCRIPTION

The CAT28F001 is a high speed 128K X 8 bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after sale
code updates.

The CAT28F001 has a blocked architecture with one 8
KB Boot Block, two 4 KB Parameter Blocks and one 112
KB Main Block. The Boot Block section can be at the top
or bottom of the memory map and includes a reprogram­ming write lock out feature to guarantee data integrity. It
is designed to contain secure code which will bring up
the system minimally and download code to other loca­tions of CAT28F001.

■ Deep Powerdown Mode

— 0.05 µA ICC Typical
— 0.8 µA IPP Typical

■ Hardware Data Protection

■ Electronic Signature

■ 100,000 Program/Erase Cycles and 10 Year

Data Retention

■ JEDEC Standard Pinouts:

— 32 pin DIP
— 32 pin PLCC
— 32 pin TSOP

■ Reset/Deep Power Down Mode

The CAT28F001 is designed with a signature mode
which allows the user to identify the IC manufacturer and
device type. The CAT28F001 is also designed with on­Chip Address Latches, Data Latches, Programming and
Erase Algorithms.

The CAT28F001 is manufactured using Catalyst’s ad­vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, PLCC or TSOP packages.

BLOCK DIAGRAM

RP

WE

CE
OE

A0–A

16

© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

WRITE STATE

MACHINE

COMMAND
REGISTER

VOLTAGE VERIFY

SWITCH

ADDRESS
COUNTER

ERASE VOLTAGE

SWITCH

PROGRAM VOLTAGE

SWITCH

Y-DECODER

X-DECODER

ADDRESS LATCH

1

CE, OE LOGIC

I/O0–I/O

7

I/O BUFFERS

COMPARATOR

Y-GATING

SENSE

AMP

DATA

LATCH

8K-BYTE BOOT BLOCK
4K-BYTE PARAMETER BLOCK
4K-BYTE PARAMETER BLOCK

112K-BYTE MAIN BLOCK

STATUS

REGISTER

28F001 F01

Doc. No. 25071-00 2/98 F-1

CAT28F001

PIN CONFIGURATION

V

V

A

A
A

RP

WE

CC

A
A
A

11

A
A

13
14

PP

16
15
12

A
A
A
A

DIP Package (P)

V

PP

A

16

A

15

A

12

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

I/O

0

I/O

1

I/O

2

V

SS

1
2

9

3

8

4
5
6
7
8
9
10
11
12
13

7

14

6

15

5

16

4

1

32

V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

WE

RP

A

A

A

A

A

OE

A

CE

I/O

I/O

I/O

I/O

I/O

CC

14
13
8
9
11

10

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

7
6
5
4
3

I/O

0
0

TSOP Package (Standard Pinout) (T)

PLCC Package (N)

A12A15A16VPPVCCWE

4321323130

5
6
7
8
9
10
11
12
13

14 15 16 17 18 19 20

2

SS

I/O1I/O

I/O3I/O4I/O5I/O

V

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

RP

29
28
27
26
25
24
23
22

28F001 F02

21

6

OE
A

10

CE
I/O
I/O
I/O
I/O
I/O
V

SS

I/O
I/O
I/O
A

0

A

1

A

2

A

3

A
A
A
A
A
OE
A
CE
I/O

7
6
5
4
3

2
1
0

14
13
8
9
11

10

7

PIN FUNCTIONS

Pin Name Type Function

A0–A

16

I/O0–I/O
CE Input Chip Enable
OE Input Output Enable
WE Input Write Enable
V

CC

V

SS

V

PP

RP Input Power Down

Doc. No. 25071-00 2/98 F-1

Input Address Inputs for

memory addressing

7

I/O Data Input/Output

Voltage Supply
Ground
Program/Erase

Voltage Supply

28F001 F03

2

CAT28F001

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................... –55°C to +95°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground
(Except A9, RP, OE, VCC and VPP)

Voltage on Pin A9, RP AND OE with

Respect to Ground

(1)

........... –2.0V to +VCC + 2.0V

(1)

................... –2.0V to +13.5V

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.

VPP with Respect to Ground

during Program/Erase

VCC with Respect to Ground

(1)

.............. –2.0V to +14.0V

(1)

............ –2.0V to +7.0V

Package Power Dissipation

Capability (TA = 25°C) .................................. 1.0 W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(2)

........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Test Method

(3)

N
T
V
I

END

DR
ZAP

LTH

(3)

(3)

(3)(4)

Endurance 100K Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 10 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17

CAPACITANCE TA = 25°C, f = 1.0 MHz

Limits

Symbol Test Min Max. Units Conditions

(3)

C

IN

(3)

C

OUT

(3)

C

VPP

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Input Pin Capacitance 8 pF V
Output Pin Capacitance 12 pF V

IN
OUT

= 0V

= 0V

VPP Supply Capacitance 25 pF VPP = 0V

3

Doc. No. 25071-00 2/98 F-1

CAT28F001

D.C. OPERATING CHARACTERISTICS

VCC = +5V ±10%, unless otherwise specified

Limits

Symbol Parameter Min. Max. Unit Test Conditions

I

LI

I

LO

I

SB1

I

SB2

I

PPD

I

CC1

I

CC2

I

CC3

I

PPS

Input Leakage Current ±1.0 µAVIN = VCC or V

Output Leakage Current ±10 µAV

VCC Standby Current CMOS 100 µA CE = VCC ±0.2V = RP

VCC Standby Current TTL 1.5 mA CE = RP = VIH, VCC = 5.5V
VPP Deep Powerdown Current 1.0 µA RP = GND±0.2V
VCC Active Read Current 30 mA VCC = 5.5V, CE = VIL,

(1)

VCC Programming Current 20 mA VCC = 5.5V,

(1)

VCC Erase Current 20 mA VCC = 5.5V,

VPP Standby Current ±10 µAVPP < V

200 µAVPP > V

I

PP1

I

PP2

I

PP3

V

IL

V

OL

V

IH

V

OH

V

ID

I

ID

I

CCD

I

CCES

I

PPES

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

VPP Read Current 200 µAVPP = V

(1)

VPP Programming Current 30 mA VPP = V

(1)

VPP Erase Current 30 mA VPP = V

Input Low Level –0.5 0.8 V
Output Low Level 0.45 V IOL = 5.8mA, VCC = 4.5V
Input High Level 2.0 VCC+0.5 V
Output High Level 2.4 V IOH = 2.5mA, VCC = 4.5V
A9 Signature Voltage 11.5 13.0 V A9 = V
A9 Signature Current 500 µAA
VCC Deep Powerdown Current 1.0 µA RP = GND±0.2V
VCC Erase Suspend Current 10 mA Erase Suspended CE = V
VPP Erase Suspend Current 300 µA Erase Suspended

SS

VCC = 5.5V

= VCC or VSS,

OUT

VCC = 5.5V

VCC = 5.5V

I

= 0mA, f = 8 MHz

OUT

Programming in Progress

Erase in Progress

CC
CC

PPH

,

PPH

Programming in Progress

,

PPH

Erase in Progress

ID

= V

9

ID

VPP=V

IH

PPH

Doc. No. 25071-00 2/98 F-1

4

SUPPLY CHARACTERISTICS

Limits

Symbol Parameter Min Max. Unit

CAT28F001

V
V
V
V
V

LKO
CC
PPL
PPH
HH

VCC Erase/Write Lock Voltage 2.5 V
VCC Supply Voltage 4.5 5.5 V
VPP During Read Operations 0 6.5 V
VPP During Erase/Program 11.4 12.6 V
RP, OE Unlock Voltage 11.4 12.6 V

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified

JEDEC Standard 28F001-90

Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

t

AVAV

t

ELQV

t

AVQV

t

GLQV

t

RC

t

CE

t

ACC

t

OE

Read Cycle Time 90 120 150 ns
CE Access Time 90 120 150 ns
Address Access Time 90 120 150 ns
OE Access Time 35 50 55 ns

-tOHOutput Hold from Address OE/CE Change 0 0 0 ns
t

GLQX

t

ELQX

t

GHQZ

t

EHQZ

t

PHQV

t

OLZ

t

LZ

t

DF

t

HZ

t

PWH

(1)(6)

(1)(6)

(1)(2)

(1)(2)

OE to Output in Low-Z 0 0 0 ns
CE to Output in Low-Z 0 0 0 ns
OE High to Output High-Z 30 30 30 ns
CE High to Output High-Z 35 55 55 ns

RP High to Output Delay 600 600 600 ns

28F001-70

Min.

70

0
0
0

(8)

Max.

70
70
27

30
55
600

(7)

28F001-12

(7)

28F001-15

(7)

Figure 1. A.C. Testing Input/Output Waveform

(3)(4)(5)

Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)

2.4 V

0.45 V

INPUT PULSE LEVELS REFERENCE POINTS

2.0 V

0.8 V

5108 FHD F03

Testing Load Circuit (example)

1.3V

1N914

3.3K

DEVICE
UNDER

TEST

CL = 100 pF

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
(8) For load and reference points, see Fig. 2

OUT

CL INCLUDES JIG CAPACITANCE

5108 FHD F04

3.0 V

0.0 V

INPUT PULSE LEVELS REFERENCE POINTS

1.5 V

Testing Load Circuit (example)

1.3V

1N914

3.3K

DEVICE
UNDER

TEST

CL = 30 pF

OUT

CL INCLUDES JIG CAPACITANCE

5108 FHD F03A

5108 FHD F05

5

Doc. No. 25071-00 2/98 F-1

CAT28F001

A.C. CHARACTERISTICS, Program/Erase Operation

VCC = +5V ±10%

JEDEC

Standard 28F001-70

Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

t

AVAV

t

AVWH

t

WHAX

t

DVWH

t

WHDX

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHGL

t

PHWL

t

PHHWH

t

VPWH

t

WHQV1

t

WHQV2

t

WHQV3

t

WHQV4

t

QVVL

t

QVPH

t

PHBR

t

GHHWL

t

WHGH

(1)

t

WC

t

AS

t

AH

t

DS

t

DH

t

CS

t

CH

t

WP

t

WPH

— Write Recovery Time Before Read 0 0 0 µs
t

PS

t

PHS

t

VPS

Write Cycle Time 70 90 120 150 ns
Address Setup to WE Going High 35 40 40 40 ns
Address Hold Time from WE Going High 10 10 10 10 ns
Data Setup Time to WE Going High 40 40 40 ns
Data Hold Time from WE Going High 10 10 10 ns
CE Setup Time to WE Going Low 0 0 0 ns
CE Hold Time from WE Going High 0 0 0 ns
WE Pulse Width 40 40 40 ns
WE High Pulse Width 10 10 10 ns

35
10
0
0
35

10
0

(1)

RP High Recovery to WE Going Low 480 480 480 ns

(1)

RP VHH Setup to WE Going High 100 100 100 ns

(1)

VPP Setup to WE Going High 100 100 100 ns

480
100
100

— Duration of Programming Operations 15 15 15 15 µs
— Duration of Erase Operations (Boot) 1.3 1.3 1.3 1.3 Sec
— Duration of Erase Operations (Parameter) 1.3 1.3 1.3 1.3 Sec
— Duration of Erase Operations (Main) 3 3 3 3 Sec

(1)

t

VPH

t

PHH

VPP Hold from Valid Status Reg Data 0 0 0 0 ns

(1)

RP VHH Hold from Status Reg Data 0 0 0 0 ns
— Boot Block Relock Delay 100 100 100 100 ns
— OE VHH Setup to WE Going Low 480 480 480 480 ns
— OE VHH Hold from WE High 480 480 480 480 ns

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

28F001-90 28F001-12 28F001-15

Doc. No. 25071-00 2/98 F-1

6

CAT28F001

ERASE AND PROGRAMMING PERFORMANCE

28F001-70 28F001-90 28F001-12 28F001-15
Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

Boot Block Erase Time 2.10 14.9 2.10 14.9 2.10 14.9 2.10 14.9 Sec
Boot Block Program Time 0.15 0.52 0.15 0.52 0.15 0.52 0.15 0.52 Sec
Parameter Block Erase Time 2.10 14.6 2.10 14.6 2.10 14.6 2.10 14.6 Sec
Parameter Block Program Time 0.07 0.26 0.07 0.26 0.07 0.26 0.07 0.26 Sec
Main Block Erase Time 3.80 20.9 3.80 20.9 3.80 20.9 3.80 20.9 Sec
Main Block Program Time 2.10
Chip Erase Time 10.10 65 10.10 65 10.10 65 10.10 65 Sec
Chip Program Time 2.39 8.38 2.39 8.38 2.39 8.38 2.39 8.38 Sec

7.34

2.10 7.34 2.10 7.34 2.10 7.34 Sec

FUNCTION TABLE

(1)

Pins

Mode

Read V
Output Disable V
Standby V
Signature (MFG) V
Signature (Device) V

RPRP

RP

RPRP

IH
IH
IH
IH
IH

CECE

CE

CECE

V
V
V
V
V

OEOE

OE

OEOE

IL
IL

IH

IL
IL

V

IL

V

IH

X X X High-Z

V

IL

V

IL

WEWE

WE V

WEWE

V

IH

V

IH

V

IH

V

IH

PP

XD

I/O Notes

OUT

X High-Z

X 31H A0 = VIL, A9 = 12V
X 94H-28F001T A0 = VIH, A9 = 12V

95H-28F001B
Write Cycle V
Deep Power Down V

IH
IL

V

IL

V

IH

V

IL

XDINDuring Write Cycle

XXXXHIGH-Z

WRITE COMMAND TABLE

Commands are written into the command register in one or two write cycles. Write cycles also internally latch
addresses and data required for programming and erase operations.

First Bus Cycle Second Bus Cycle

Mode Operation Address D

Operation Address D

IN

IN

D

OUT

Read Array/Reset Write X FFH
Program Setup/ Write A

IN

40H Write A

IN

D

IN

Program 10H
Read Status Reg. Write X 70H Read X St. Reg. Data
Clear Status Reg. Write X 50H

Erase Setup/Erase Write Block ad 20H Write Block ad D0H
Confirm

Erase Suspend/ Write X B0H Write X D0H
Erase Resume

Read Sig (Mfg) Write X 90H Read 0000H 31H
Read Sig (Dev) Write X 90H Read 0001H 94H-28F001T

95H-28F001B

Note:
(1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, V

PPL

, V

PPH

)

7

Doc. No. 25071-00 2/98 F-1

CAT28F001

READ OPERATIONS

Read Mode

The CAT28F001 memory can be read from any of its
Blocks (Boot Block, Main Block or Parameter Block),
Status Register and Signature Information by sending
the Read Command Mode to the Command Register.

CAT28F001 automatically resets to Read Array mode
upon initial device power up or after exit from deep
power down. A Read operation is performed with both
CE and OE low and with RP and OE high. Vpp can be
either high or low. The data retrieved from the I/O pins
reflects the contents of the memory location correspond­ing to the state of the 17 address pins. The respective
timing waveforms for the read operation are shown in
Figure 3. Refer to the AC Read characteristics for
specific timing parameters.

Signature Mode

The signature mode allows the user to identify the IC
manufacturer and the type of the device while the device
resides in the target system. This mode can be activated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9 or by
sending an instruction to the command register (see
Write Operations).

The conventional method is entered as a regular read
mode by driving the CE and OE low (with WE high), and

applying the required high voltage on address pin A9
while the other address line are held at VIL.

A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O7 to I/O0:

Catalyst Code = 0011 0001 (31H)
A Read cycle from address 0001H retrieves the binary

code for the device on outputs I/O7 to I/O0:
CAT28F001T = 1001 0100 (94H)
CAT28F001B = 1001 0101 (95H)

Standby Mode

With CE at a logic-high level, the CAT28F001 is placed
in a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power con­sumption. The outputs are placed in a high-impendance
state independent of the OE status.

Deep Power-Down

When RP is at logic-low level, the CAT28F001 is placed
in a Deep Power-Down mode where all the device
circuitry are disabled, thereby reducing the power con­sumption to 0.25µW.

Figure 3. A.C. Timing for Read Operation

STANDBY DEVICE AND

ADDRESS SELECTION

ADDRESSES

CE (E)

OE (G)

WE (W)

DATA (I/O)

RP (P)

POWER UP

HIGH-Z

t

PHQV

t

GLQX

(t

ADDRESS STABLE

(t

OLZ

t

ELQX

t

AVQV

)

PWH

)

(tLZ)

(t

ACC

t

AVAV

OUPUTS

ENABLED

(tRC)

t

GLQV

)

(tOE)

DATA VALID STANDBY

t

t

GHQZ

t

(tCE)

ELQV

OUTPUT VALID

EHQZ

(tDF)

t

OH

POWER DOWN

HIGH-Z

Doc. No. 25071-00 2/98 F-1

28F001 F05

8

CAT28F001

WRITE OPERATIONS

The following operations are initiated by observing the
sequence specified in the Write Command Table.

Read Array

The device can be put into a Read Array Mode by
initiating a write cycle with FFH on the data bus. The
device is also in a standard Read Array Mode after the
initial device power up and when comes out of the Deep
Power-Down mode.

Signature Mode

An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code 90H into the command register. A read cycle
from address 0000H with CE and OE low (and WE high)
will output the device signature.

Catalyst Code = Catalyst Code = 0011 0001 (31H)
A Read cycle from address 0001H retrieves the

binary code for the device on outputs I/O7 to I/O0:
CAT28F001T = 1001 0100 (94H)

CAT28F001B = 1001 0101 (95H)
To terminate the operations, it is necessary to write

another valid command into the register.

STATUS REGISTER

The 28F001 contains an 8-bit Status Register. The
Status Register is polled to check for write or erase
completion or any related errors. The Status Register
may be read at any time by issuing a Read Status
Register (70H) command. All subsequent read opera­tions output data from the Status Register, until another
valid command is issued. The contents of the Status
Register are latched on the falling edge of OE or CE ,
whichever occurs last in the read cycle. OE or CE must
be toggled to VIH before further reads to update the
status register latch.

The Erase Status (SR.5) and Program Status (SR.4) are
set to 1 by the WSM and can only be reset issuing Clear
Status Register (50H) These two bits can be polled for
failures, thus allowing more flexibility to the designer
when using the CAT28F001. Also, VPP Status (SR.3)
when set to 1 must be reset by system software before
any further byte programs or block erases are attempted.

ERASE SETUP/ERASE CONFIRM

Erase is executed one block at a time, initiated by a two
cycle command sequence. The two cycle command
sequence provides added security against accidental

block erasure. During the first write cycle, a Command
20H (Erase Setup) is first written to the Command
Register, followed by the Command D0H (Erase Con­firm). These commands require both appropriate com­mand data and an address within Block to be erased.
Also, Block erasure can only occur when VPP= VPPH.

Block preconditioning, erase and verify are all handled
internally by the Write State Machine, invisible to the
system. After receiving the two command erase se­quence the CAT28F001 automatically outputs Status
Register data when read (Fig.5). The CPU can detect
the completion of the erase event by checking if the
SR.7 of the Status Register is set.

SR.5 will indicate whether the erase was successful. If
an erase error is detected, the Status Register should be
cleared. The device will be in the Status Register Read
Mode until another command is issued.

ERASE SUSPEND/ERASE RESUME

The Erase Suspend Command allows erase sequence
interruption in order to read data from another block of
memory. Once the erase sequence is started, writing
the Erase Suspend command (B0H) to the Command
Register requests that the WSM suspend the erase
sequence at a predetermined point in the erase algo­rithm. The CAT28F001 continues to output Status Reg­ister data when read, after the Erase Suspend command
is written to it. Polling the WSM Status and Erase
Suspend Status bits will determine when the erase
operation has been suspended (both will be set to “1s”).

The device may now be given a Read ARRAY Com­mand, which allows any locations 'not within the block
being erased' to be read. Also, you can either perform
a Read Status Register or resume the Erase Operation
by sending Erase Resume (D0H), at which time the
WSM will continue with the erase sequence. The Erase
Suspend Status and WSM Status bits of the Status
Register will be cleared.

PROGRAM SETUP/PROGRAM COMMANDS

Programming is executed by a two-write sequence. The
program Setup command (40H) is written to the Com­mand Register, followed by a second write specifying
the address and data (latched on the rising edge of WE)
to be programmed. The WSM then takes over, control­ling the program and verify algorithms internally. After
the two-command program sequence is written to it, the
CAT28F001 automatically outputs Status Register data
when read (see figure 4; Byte Program Flowchart). The
CPU can detect the completion of the program event by
analyzing the WSM Status bit of the Status Register.
Only the Read Status Register Command is valid while
programming is active.

9

Doc. No. 25071-00 2/98 F-1

CAT28F001

WSMS ESS ES PS VPPS R R R

76543210

SR.7 = WRITE STATE MACHINE STATUS

1 = Ready
0 = Busy

SR.6 = ERASE SUSPEND STATUS

1 = Erase Suspended
0 = Erase in Progress/Completed

SR.5 = ERASE STATUS

1 = Error in Block Erasure
0 = Successful Block Erase

SR.4 = PROGRAM STATUS

1 = Error in Byte Program
0 = Successful Byte Program

SR.3 = VPP STATUS

1 = VPP Low Detect; Operation Abort

0 = VPP Okay
SR.2 -SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be masked

out when polling the Status Register.

When the Status Register indicates that programming is
complete, the Program Status bit should be checked. If
program error is detected, the Status Register should be
cleared. The internal WSM verify only detects errors for
“1s” that do not successfully program to “0s”. The
Command Register remains in Read Status Register
mode until further commands are issued to it.

If erase/byte program is attempted while VPP = V

PPL

, the
Status bit (SR.5/SR.4) will be set to “1”. Erase/Program
attempts while V

< VPP < V

PPL

produce spurious

PPH

results and should not be attempted.

EMBEDDED ALGORITHMS

The CAT28F001 integrates the Quick Pulse program­ming algorithm on-chip, using the Command Register,
Status Register and Write State Machine (WSM). On­chip integration dramatically simplifies system software
and provides processor-like interface timings to the
Command and Status Registers. WSM operation, inter­nal program verify, and VPP high voltage presence are
monitored and reported via appropriate Status Register
bits. Figure 4 shows a system software flowchart for
device programming.

As above, the Quick Erase algorithm is now imple­mented internally, including all preconditioning of block
data. WSM operation, erase verify and VPP high voltage
presence are monitored and reported through the Status
Register. Additionally, if a command other than Erase
Confirm is written to the device after Erase Setup has
been written, both the Erase Status and Program Status

NOTES:
The Write State Machine Status Bit must first be checked to

determine program or erase completion, before the
Program or Erase Status bits are checked for success.

If the Program AND Erase Status bits are set to “1s” during an

erase attempt, an improper command sequence was
entered. Attempt the operation again.

If VPP low status is detected, the Status Register must be

cleared before another program or erase operation is
attempted.

The VPP Status bit, unlike an A/D converter, does not provide

continuous indication of VPP level. The WSM interrogates
the VPP level only after the program or erase command
sequences have been entered and informs the system if
VPP has not been switched on. The VPP Status bit is not
guaranteed to report accurate feedback between V
V

.

PPH

PPL

and

bits will be set to “1”. When issuing the Erase Setup and
Erase Confirm commands, they should be written to an
address within the address range of the block to be
erased. Figure 5 shows a system software flowchart for
block erase.

The entire sequence is performed with VPP at V

PPH

Abort occurs when RP transitions to VIL, or VPP drops to
V

. Although the WSM is halted, byte data is partially

PPL

programmed or Block data is partially erased at the
location where it was aborted. Block erasure or a repeat
of byte programming will initialize this data to a known
value.

BOOT BLOCK PROGRAM AND ERASE

The boot block is intended to contain secure code which
will minimally bring up a system and control program­ming and erase of other blocks of the device, if needed.
Therefore, additional “lockout” protection is provided to
guarantee data integrity. Boot block program and erase
operations are enabled through high voltage VHH on
either RP or OE, and the normal program and erase
command sequences are used. Reference the AC
Waveforms for Program/Erase.

If boot block program or erase is attempted while RP is
at VIH, either the Program Status or Erase Status bit will
be set to “1”, reflective of the operation being attempted
and indicating boot block lock. Program/erase attempts
while VIH < RP < VHH produce spurious results and
should not be attempted.

.

Doc. No. 25071-00 2/98 F-1

10

IN-SYSTEM OPERATION

For on-board programming, the RP pin is the most
convenient means of altering the boot block. Before
issuing Program or Erase confirms commands, RP must
transition to VHH. Hold RP at this high voltage throughout
the program or erase interval (until after Status Register
confirm of successful completion). At this time, it can
return to VIH or VIL.

Figure 4 Byte Programming Flowchart

CAT28F001

START

WRITE 40H,

BYTE ADDRESS

WRITE BYTE

ADDRESS/DATA

READ STATUS

REGISTER

SR.7 = 1?

YES

FULL STATUS

CHECK IF DESIRED

BYTE PROGRAM

COMPLETED

NO

FULL STATUS CHECK PROCEDURE

Bus
Operation Command Comments

Write Program Data = 40H

Setup Address = Bytes to be Programmed

Write Program Data to be programmed

Address = Byte to be Programmed

Read Status Register Data.

Toggle OE or CE to update
Status Register
Check SR.7

Standby 1 = Ready, 0 = Busy

Repeat for subsequent bytes.

Full Status check can be done after each byte or after a sequence
of bytes.

Write FFH after the last byte programming operation to reset the
device to Read Array Mode.

STATUS REGISTER DATA

READ (SEE ABOVE)

SR.3 = 0?

YES

SR.4 = 0?

YES

BYTE PROGRAM

SUCCESSFUL

NO

BYTE PROGRAM

NO

V

PP

ERROR

ERROR

RANGE

Bus
Operation Command Comments

Standby Check SR.3

Standby Check SR.3

SR.3 MUST be cleared, if set during a program attempt, before
further attempts are allowed by the Write State Machine.

SR.3 is only cleared by the Clear Status Register Command, in
case where multiple bytes are programmed before full status is
checked.

If error is detected, clear the Status Register before attempting retry
or other error recovery.

11

1 = VPP Low Detect

1 = Byte Program Error

Doc. No. 25071-00 2/98 F-1

CAT28F001

Figure 5 Block Erase Flowchart

START

WRITE 20H,

BLOCK ADDRESS

WRITE D0H

BLOCK ADDRESS

READ STATUS

REGISTER

SR.7 = 1?

YES

FULL STATUS

CHECK IF DESIRED

BLOCK ERASE

COMPLETED

NO

FULL STATUS CHECK PROCEDURE

STATUS REGISTER DATA

READ (SEE ABOVE)

NO

SUSPEND

ERASE?

ERASE SUSPEND

LOOP

YES

Bus
Operation Command Comments

Write Erase Data = 20H

Setup Address = Within Block to be erased

Write Erase Data - D0H

Address = Within Block to be erased

Read Status Register Data.

Toggle OE or CE to update
Status Register

Standby Check SR.7

1 = Ready, 0 = Busy

Repeat for subsequent blocks.
Full Status check can be done after each block or after a sequence

of blocks.
Write FFH after the last block erase operation to reset the device to

Read Array Mode.

Bus
Operation Command Comments

SR.3 = 0?

YES

SR.4,5 = 1?

NO

SR.5 = 0?

BLOCK ERASE

SUCCESSFUL

RANGE

NO

YES

NO

V

PP

ERROR

COMMAND SEQUENCE

ERROR

BLOCK ERASE

ERROR

Standby Check SR.3

1 = VPP Low Detect

Standby Check SR.4

Both 1 = Command Sequence Error

Standby Check SR.5

1 = Block Erase Error

SR.3 MUST be cleared, if set during a erase attempt, before further
attempts are allowed by the Write State Machine.

SR.3 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erased before full status is
checked.

If error is detected, clear the Status Register before attempting retry
or other error recovery.

Doc. No. 25071-00 2/98 F-1

12

Figure 6 Block Erase Suspend/Resume Flowchart

CAT28F001

START

WRITE B0H

READ STATUS

REGISTER

SR.7 = 1?

YES

SR.6 = 1?

YES

WRITE FFH

DONE

READING?

NO

NO

NO

ERASE HAS

COMPLETED

Bus
Operation Command Comments

Write Erase Data = B0H

Suspend

Standby/ Read Status Register
Ready Check SR.7

1 = Ready, 0 = Busy
Toggle OE or CE to Update
Status Register

Standby Check SR.6

1 = Suspended

Write Read Array Data = FFH

Read Read array data from block other

than that being erased.

YES

WRITE D0H

CONTINUE

ERASE

Write Erase Resume Data = D0H

13

Doc. No. 25071-00 2/98 F-1

CAT28F001

Figure 7. A.C. Timing for Program/Erase Operation

ADDRESSES (A)

CE (E)

OE (G)

WE (W)

DATA (I/O)

RP (P)

VPP (V)

V

V

V

PPH

V

IH

V

V

IH

V

V

IH

V

V

IH

V

V

IH

V

HH

6.5V
V

IH

V

PPL

V

IH

V

V

IL

IL

IL

IL

IL

IL

IL

CC

POWER-UP

& STANDBY

HIGH Z

WRITE PROGRAM OR

ERASE SETUP COMMAND

t

ELWL

t

DVWH

t

PHWL

A

t

AVAV

t

AVWH

WRITE

A

IN

D

IN

t

PHHWH

t

VPWH

VALID ADDRESS & DATA (PROGRAM)

OR ERASE CONFIRM COMMAND

IN

t

WHEH

t

WHWL

t

WLWH

t

WHDX

D

IN

AUTOMATED PROGRAM

OR ERASE DELAY

t

WHAX

t

WHGL

t

1, 2, 3, 4

WHQV

READ STATUS

REGISTER DATA

VALID

SRD

t

QVPH

t

QVVL

WRITE READ ARRAY

COMMAND

D

IN

POWER UP/DOWN PROTECTION

The CAT28F001 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and V
may power up in any order. Additionally VPP may be
hardwired to V

independent of the state of VCC and

PPH

any power up/down cycling. The internal command
register of the CAT28F001 is reset to the Read Mode on
power up.

CC

28F001 F09

POWER SUPPLY DECOUPLING

To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitor between VCC and VSS and VPP and VSS. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.

Doc. No. 25071-00 2/98 F-1

14

ALTERNATE CE-CONTROLLED WRITES

VCC = +5V ±10%, unless otherwise specified

CAT28F001

JEDEC

Standard 28F001-70

28F001-90 28F001-12 28F001-15

Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

t

tWC Write Cycle Time 70 90 120 150 ns

AVAV

t

tAS Address Setup to CE Going High 35 40 40 40 ns

AVEH

t

tAH Address Hold Time from CE Going High 10 10 10 10 ns

EHAX

t

tDS Data Setup Time to CE Going High 35 40 40 40 ns

DVEH

t

tDH Data Hold Time from CE Going High 10 10 10 10 ns

EHDX

t

tWS WE Setup Time to CE Going Low 0 0 0 0 ns

WLEL

t

tWH WE Hold Time from CE Going High 0 0 0 0 ns

EHWH

t

tCP CE Pulse Width 35 40 40 40 ns

ELEH

t

t

EHEL

t

EHGL

t

t

PHEL

t

t

PHHEH

t

t

VPEH

t

— Duration of Programming Operations 15 15 15 15 µs

EHQV1

t

— Duration of Erase Operations (Boot) 1.3 1.3 1.3 1.3 Sec

EHQV2

t

— Duration of Erase Operations (Parameter) 1.3 1.3 1.3 1.3 Sec

EHQV3

t

— Duration of Erase Operations (Main) 3 3 3 3 Sec

EHQV4

t

t

QVVL

t

t

QVPH

(1)

t

— Boot Block Relock Delay 100 100 100 100 ns

PHBR

t

— OE VHH Setup to WE Going Low 480 480 480 480 ns

GHHWL

t

— OE VHH Hold from WE High 480 480 480 480 ns

WHGH

CE High Pulse Width 10 10 10 10 ns

EPH

— Write Recovery Time Before Read 0 0 0 0 µs

(1)

RP High Recovery to CE Going Low 480 480 480 480 ns

PS

(1)

RP VHH Setup to CE Going High 100 100 100 100 ns

PHS

(1)

VPP Setup to CE Going High 100 100 100 100 ns

VPS

(1)

VPP Hold from Valid Status Reg Data 0 0 0 0 ns

VPH

(1)

RP VHH Hold from Status Reg Data 0 0 0 0 ns

PHH

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

15

Doc. No. 25071-00 2/98 F-1

CAT28F001

Figure 8. Alternate Boot Block Access Method Using OE

WRITE

D

OE

WE

DATA

WRITE PROGRAM OR

ERASE SETUP COMMAND

V

HH

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

t

GHHWL

VALID ADDRESS AND DATA (PROGRAM)

OR ERASE CONFIRM COMMAND

D

IN

Figure 9. Alternate AC Waveform for Write Operations

t

AVEH

WRITE

A

IN

D

IN

t

PHHEH

t

VPEH

ADDRESSES

WE (W)

OE (a)

CE (E)

DATA I/O

RP (P)

VPP (V)

V

V

V

V

V

V

V

V

V

V

V

V

V

HH

6.5V
V

V

PPH

PPL

V

V

V

IH

IL

IH

IL

IH

IL

IH

IL

IH

IL

IH

IL

IH

IL

POWER-UP

CC

& STANDBY

HIGH Z

WRITE PROGRAM OR

ERASE SETUP COMMAND

t

WLEL

t

DVEH

t

PHEL

A

t

AVAV

VALID ADDRESS & DATA (PROGRAM)

OR ERASE CONFIRM COMMAND

IN

t

EHWH

t

EHEL

t

ELEH

t

EHDX

D

IN

t

WHGH

IN

AUTOMATED PROGRAM

OR ERASE DELAY

t

EHAX

t

EHGL

t

1, 2, 3, 4

EHQV

AUTOMATED PROGRAM

OR ERASE DELAY

READ STATUS

REGISTER DATA

VALID

SRD

t

QVPH

t

QVVL

READ STATUS

REGISTER DATA

VALID

SR DATA

WRITE READ ARRAY

COMMAND

D

IN

Doc. No. 25071-00 2/98 F-1

16

ORDERING INFORMATION

Prefix Device # Suffix

CAT28F001

Optional
Company ID

28F001

Product
Number

P

IT

Temperature Range

Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)

-90CAT B

Boot Block

B: Bottom
T: Top

Tape & Reel

T: 500/Reel

A = Automotive (-40˚ - 105˚C)*

Package

N: PLCC
P: PDIP
T: TSOP (8mmx20mm)

Speed

70: 70ns
90: 90 ns
12: 120 ns
15: 150 ns

28F001 F12

* -40˚ to +125˚C is available upon request

Note:
(1) The device used in the above example is a CAT28F001PI-90BT (PDIP, Industrial Temperature, 90ns access time, Bottom Boot Block,

Tape & Reel)

17

Doc. No. 25071-00 2/98 F-1

CAT28F001

Doc. No. 25071-00 2/98 F-1

18