Datasheet CAT28C17AK-20T, CAT28C17AJI-20T, CAT28C17AJA-20T, CAT28C17AJ-20T, CAT28C17API-20T Datasheet (CTLST)

CAT28C17A

16K-Bit CMOS PARALLEL E2PROM

FEATURES

■ Fast Read Access Times: 200 ns

■ Low Power CMOS Dissipation:

–Active: 25 mA Max.
–Standby: 100 µA Max.

■ Simple Write Operation:

–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear

■ Fast Write Cycle Time: 10ms Max

DESCRIPTION

The CAT28C17A is a fast, low power, 5V-only CMOS
parallel E2PROM organized as 2K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and a RDY/BSY pin signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C17A features hardware write protection.

■ End of Write Detection:

DATADATA

–

DATA Polling

DATADATA

BSYBSY

–RDY/

BSY Pin

BSYBSY

■ Hardware Write Protection

■ CMOS and TTL Compatible I/O

■ 10,000 Program/Erase Cycles

■ 10 Year Data Retention

■ Commercial,Industrial and Automotive

Temperature Ranges

The CAT28C17A is manufactured using Catalyst’s ad­vanced CMOS floating gate technology. It is designed to
endure 10,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 28-pin DIP and SOIC or 32-pin PLCC pack­ages.

BLOCK DIAGRAM

A4–A

10

V

CC

CE
OE

WE

A0–A

3

RDY/BUSY

© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

ADDR. BUFFER

& LATCHES

INADVERTENT

WRITE

PROTECTION

CONTROL

LOGIC

TIMER

ADDR. BUFFER

& LATCHES

1

ROW

DECODER

HIGH VOLTAGE

GENERATOR

DATA POLLING

& RDY/BUSY

COLUMN

DECODER

2,048 x 8

2

E

PROM

ARRAY

I/O BUFFERS

I/O0–I/O

7

Doc. No. 25034-00 2/98

5091 FHD F02

CAT28C17A

PIN CONFIGURATION

DIP Package (P) PLCC Package (N)SOIC Package (J,K)

1

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V
WE
NC
A
A
NC
OE
A
CE
I/O
I/O
I/O
I/O
I/O

CC

8
9

10

7
6
5
4
3

RDY/BUSY

NC

A
A
A
A
A
A
A
A

I/O
I/O

V

SS

2
3

7

4

6

5

5

6

4

7

3

8

2

9

1

10

0

11I/O

0

12

1

13

2

14

PIN FUNCTIONS

Pin Name Function

A0–A

10

Address Inputs

RDY/BUSY

NC

A
A
A
A
A
A
A
A

I/O
I/O

V

SS

1

28

V

CC

2

27

WE

3

26
25
24
23
22
21
20
19
1811I/O
17
16
15

NC
A
A
NC
OE
A
CE
I/O
I/O
I/O
I/O
I/O

8
9

10

RDY/BUSY

A7NC

4321323130

5

A

6

6

A

5

7

A

4

8

A

I/O

A
A
A

NC

3

9

2

10

1

11

0

12
13

0

14 15 16 17 18 19 20

I/O1I/O

7
6
5
4
3

NC

TOP VIEW

2

SS

NC

V

VCCWE

NC

29
28
27
26
25
24
23
22
21

5

I/O3I/O4I/O

5091 FHD F01

A
A
NC
NC
OE
A
CE
I/O
I/O

8
9

10

7
6

7

4

6

5

5

6

4

7

3

8

2

9

1

10

0
0

12

1

13

2

14

I/O0–I/O

7

Data Inputs/Outputs
RDY/BUSY Ready/BUSY Status
CE Chip Enable
OE Output Enable
WE Write Enable
V

CC

V

SS

5V Supply

Ground
NC No Connect

MODE SELECTION

Mode CE WE OE I/O Power

Read L H L D
Byte Write (WE Controlled) L H D
Byte Write (CE Controlled) L H D

OUT
IN
IN

ACTIVE
ACTIVE

ACTIVE
Standby, and Write Inhibit H X X High-Z STANDBY
Read and Write Inhibit X H H High-Z ACTIVE

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Max. Units Conditions

(1)

C

I/O

(1)

C

IN

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

Doc. No. 25034-00 2/98

Input/Output Capacitance 10 pF V
Input Capacitance 6 pF VIN = 0V

2

I/O

= 0V

CAT28C17A

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground

VCC with Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

(2)

........... –2.0V to +VCC + 2.0V

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica­tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor­mance and reliability.

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(3)

........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Test Method

(1)

N
T
V
I

LTH

END

DR

ZAP

(1)

(1)

(1)(4)

Endurance 10,000 Cycles/Byte MIL-STD-883, Test Method 1033
Data Retention 10 Years MIL-STD-883, Test Method 1008
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
Latch-Up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = 5V ±10%, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I

CC

VCC Current (Operating, TTL) 35 mA CE = OE = VIL,

f = 1/tRC min, All I/O’s Open

(5)

I

CCC

VCC Current (Operating, CMOS) 25 mA CE = OE = V

ILC

,

f = 1/tRC min, All I/O’s Open

I

SB

I

SBC

(6)

VCC Current (Standby, TTL) 1 mA CE = VIH, All I/O’s Open
VCC Current (Standby, CMOS) 100 µA CE = V

IHC

,

All I/O’s Open

I

LI

I

LO

(6)

V

IH

(5)

V

IL

V

OH

V

OL

V

WI

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
(5) V
(6) V

= –0.3V to +0.3V.

ILC

= VCC –0.3V to VCC +0.3V.

IHC

Input Leakage Current –10 10 µAVIN = GND to V
Output Leakage Current –10 10 µAV

= GND to VCC,

OUT

CE = V

IH

High Level Input Voltage 2 VCC +0.3 V
Low Level Input Voltage –0.3 0.8 V
High Level Output Voltage 2.4 V IOH = –400µA
Low Level Output Voltage 0.4 V IOL = 2.1mA
Write Inhibit Voltage 3.0 V

CC

3

Doc. No. 25034-00 2/98

CAT28C17A

A.C. CHARACTERISTICS, Read Cycle

VCC = 5V ±10%, unless otherwise specified.

28C17A-20

Symbol Parameter Min. Max. Units

t

RC

t

CE

t

AA

t

OE

t

LZ

t

OLZ

t

HZ

t

OHZ

t

OH

(1)

(1)

(1)(2)

(1)(2)

(1)

Read Cycle Time 200 ns
CE Access Time 200 ns
Address Access Time 200 ns
OE Access Time 80 ns
CE Low to Active Output 0 ns
OE Low to Active Output 0 ns
CE High to High-Z Output 55 ns
OE High to High-Z Output 55 ns
Output Hold from Address Change 0 ns

Figure 1. A.C. Testing Input/Output Waveform(3)

2.4 V
INPUT PULSE LEVELS REFERENCE POINTS

0.45 V

Figure 2. A.C. Testing Load Circuit (example)

2.0 V

0.8 V

5089 FHD F03

1.3V

1N914

3.3K

DEVICE

UNDER

TEST

CL INCLUDES JIG CAPACITANCE

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) Input rise and fall times (10% and 90%) < 10 ns.

Doc. No. 25034-00 2/98

CL = 100 pF

4

OUT

5089 FHD F04

CAT28C17A

A.C. CHARACTERISTICS, Write Cycle

VCC = 5V ±10%, unless otherwise specified.

28C17A-20

Symbol Parameter Min. Max. Units

t

WC

t

AS

t

AH

t

CS

t

CH

(2)

t

CW

t

OES

t

OEH

(2)

t

WP

t

DS

t

DH

t

DL

(1)

t

INIT

t

DB

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.

Write Cycle Time 10 ms
Address Setup Time 10 ns
Address Hold Time 100 ns
CE Setup Time 0 ns
CE Hold Time 0 ns
CE Pulse Time 150 ns
OE Setup Time 15 ns
OE Hold Time 15 ns
WE Pulse Width 150 ns
Data Setup Time 50 ns
Data Hold Time 10 ns
Data Latch Time 50 ns
Write Inhibit Period After Power-up 5 20 ms
Time to Device Busy 80 ns

5

Doc. No. 25034-00 2/98

CAT28C17A

DEVICE OPERATION

Read

Data stored in the CAT28C17A is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architec­ture can be used to eliminate bus contention in a system
environment.

Figure 3. Read Cycle

t

RC

ADDRESS

t

CE

CE

t

OE

OE

V

IH

t

WE

DATA OUT DA TA V ALIDDA TA V ALID

HIGH-Z

LZ

t

OLZ

Ready/BUSY (RDY/BUSY)

The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled
low during the write cycle and released at the end of
programming. Several devices may be OR-tied to the
same RDY/BUSY line.

t

OHZ

t

OH

t

AA

t

HZ

28C17A F05

Figure 4. Byte Write Cycle [WE Controlled]

ADDRESS

CE

OE

WE

RDY/BUSY

DATA OUT

DATA IN

t

AS

t

OES

t

CS

HIGH-Z

t

AH

t

WP

DATA VALID

t

DB

t

CH

t

OEH

t

DL

t

WC

Doc. No. 25034-00 2/98

t

DS

t

DH

5091 FHD F06

6

CAT28C17A

Byte Write

A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.

Figure 5. Byte Write Cycle [CE Controlled]

ADDRESS

CE

OE

WE

t

t

CS

AS

t

OES

t

AH

t

CW

DATA Polling

DATA polling is provided to indicate the completion of a
byte write cycle. Once a byte write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O7 (I/O0–I/O6 are indeter­minate) until the programming cycle is complete. Upon
completion of the self-timed byte write cycle, all I/O’s will
output true data during a read cycle.

t

WC

t

DL

t

OEH

t

CH

RDY/BUSY

DATA OUT

DATA IN

Figure 6. DATA Polling

ADDRESS

CE

WE

OE

HIGH-Z

t

OEH

DATA VALID

t

DS

t

OE

t

DB

t

DH

t

OES

5091 FHD F07

I/O

t

WC

D

7

= X D

IN

= X D

OUT

7

OUT

= X

28C17A F08

Doc. No. 25034-00 2/98

CAT28C17A

HARDWARE DATA PROTECTION

The following is a list of hardware data protection fea­tures that are incorporated into the CAT28C17A.

(1) VCC sense provides for write protection when V

CC

falls below 3.0V min.

(2) A power on delay mechanism, t

(see AC charac-

INIT

ORDERING INFORMATION

Prefix Device # Suffix

28C17A N I

Optional
Company ID

Product
Number

Temperature Range

Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*

teristics), provides a 5 to 20 ms delay before a write
sequence, after VCC has reached 3.0V min.

(3) Write inhibit is activated by holding any one of OE

low, CE high or WE high.

(4) Noise pulses of less than 20 ns on the WE or CE

inputs will not result in a write cycle.

-20CAT

T

Tape & Reel

T: 500/Reel

Package

P: PDIP

Speed

20: 200ns
N: PLCC
J: SOIC (JEDEC)
K: SOIC (EIAJ)

* -40˚C to +125˚C is available upon request

Notes:
(1) The device used in the above example is a CAT28C17ANI-20T (PLCC, Industrial temperature, 200 ns Access Time, Tape & Reel).

28C17A F09

Doc. No. 25034-00 2/98

8