Datasheet CAT24C02CWI-1.8, CAT24C02CWI, CAT24C02CWA-1.8, CAT24C02CWA, CAT24C02CW-1.8 Datasheet (CTLST)

1

CAT24C02C

2K-Bit Serial E2PROM

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

DIE PAD CONFIGURATION

BLOCK DIAGRAM

PIN FUNCTIONS

Pin Name Function

NC No Connect
SDA Serial Data/Address
SCL Serial Clock
V

CC

+1.8V to +6.0V Power Supply

V

SS

Ground

DC Don't Connect

FEATURES

■ 400 KHZ I

2

C Bus Compatible*

■ 1.8 to 6.0Volt Operation

■ Low Power CMOS Technology

■ Page Write Buffer

■ Self-Timed Write Cycle with Auto-Clear

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

DESCRIPTION

The CAT24C02C is a 2K-bit Serial CMOS E2PROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de­vice power requirements. The the CAT24C02C features

a 16-byte page write buffer. The device operates via the
I2C bus serial interface and has a ISO 7816 compatible
pinout.

© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

Doc. No. 25086 -00 8/99 S-1

D

OUT

ACK

SENSE AMPS

SHIFT REGISTERS

CONTROL

LOGIC

WORD ADDRESS

BUFFERS

STAR T/STOP

LOGIC

STATE COUNTERS
SLAVE

ADDRESS
COMPARATORS

E2PROM

V

CC

EXTERNAL LOAD

COLUMN

DECODERS

XDEC

DATA IN STORAGE

HIGH VOL TAGE/

TIMING CONTROL

V

SS

SCL

SDA

NC NC

DC

DCDC

V

SS

V

CC

SCL

SDA

CAT24C02C

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ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to V

SS

(1)

................. –2.0V to +V

CC

+ 2.0V

VCC with Respect to V

SS

................................

–2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(2)

........................ 100mA

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

N

END

(3)

Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033

T

DR

(3)

Data Retention 100 Years MIL-STD-883, Test Method 1008

V

ZAP

(3)

ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015

I

LTH

(3)(4)

Latch-up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I

CC

Power Supply Current 3 mA f

SCL

= 100 KHz

I

SB

(5)

Standby Current (VCC = 5.0V) 0 µAVIN = GND or V

CC

I

LI

Input Leakage Current 10 µAVIN = GND to V

CC

I

LO

Output Leakage Current 10 µAV

OUT

= GND to V

CC

V

IL

Input Low Voltage –1 VCC x 0.3 V

V

IH

Input High Voltage VCC x 0.7 VCC + 0.5 V

V

OL1

Output Low Voltage (VCC = 3.0V) 0.4 V IOL = 3 mA

V

OL2

Output Low Voltage (VCC = 1.8V) 0.5 V IOL = 1.5 mA

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby Current (ISB) = 0µA (<900nA).

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Max. Units Conditions

C

I/O

(3)

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

C

IN

(3)

Input Capacitance (SCL) 6 pF V

IN

= 0V

CAT24C02C

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Doc. No. 25086-00 8/99 S-1

A.C. CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Read & Write Cycle Limits

Symbol Parameter 1.8V, 2.5V 4.5V-5.5V

Min. Max. Min. Max. Units

F

SCL

Clock Frequency 100 400 kHz

T

I

(1)

Noise Suppression Time 200 200 ns
Constant at SCL, SDA Inputs

t

AA

SCL Low to SDA Data Out 3.5 1 µs
and ACK Out

t

BUF

(1)

Time the Bus Must be Free Before 4.7 1.2 µs
a New Transmission Can Start

t

HD:STA

Start Condition Hold Time 4 0.6 µs

t

LOW

Clock Low Period 4.7 1.2 µs

t

HIGH

Clock High Period 4 0.6 µs

t

SU:STA

Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)

t

HD:DAT

Data In Hold Time 0 0 ns

t

SU:DAT

Data In Setup Time 50 50 ns

t

R

(1)

SDA and SCL Rise Time 1 0.3 µs

t

F

(1)

SDA and SCL Fall Time 300 300 ns

t

SU:STO

Stop Condition Setup Time 4 0.6 µs

t

DH

Data Out Hold Time 100 100 ns

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t

PUR

and t

PUW

are the delays required from the time VCC is stable until the specified operation can be initiated.

The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus

interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.

Write Cycle Limits

Symbol Parameter Min. Typ. Max Units

t

WR

Write Cycle Time 10 ms

Power-Up Timing

(1)(2)

Symbol Parameter Max. Units

t

PUR

Power-up to Read Operation 1 ms

t

PUW

Power-up to Write Operation 1 ms

CAT24C02C

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FUNCTIONAL DESCRIPTION

The CAT24C02C supports the I2C Bus data transmis­sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re­ceiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24C02C
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated.

PIN DESCRIPTIONS

SCL: Serial Clock

The CAT24C02C serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.

SDA: Serial Data/Address
The CAT24C02C bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.

I2C BUS PROTOCOL

The following defines the features of the I2C bus proto­col:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.

Figure 2. Write Cycle Timing

Figure 1. Bus Timing

Figure 3. Start/Stop Timing

5020 FHD F05

5020 FHD F04

5020 FHD F03

t

HIGH

SCL

SDA IN

SDA OUT

t

LOW

t

F

t

LOW

t

R

t

BUF

t

SU:STO

t

SU:DAT

t

HD:DAT

t

HD:STA

t

SU:STA

t

AA

t

DH

t

WR

STOP
CONDITION

START
CONDITION

ADDRESS

ACK8TH BIT

BYTE n

SCL

SDA

START BIT

SDA

STOP BIT

SCL

CAT24C02C

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Doc. No. 25086-00 8/99 S-1

START Condition

The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C02C monitor the
SDA and SCL lines and will not respond until this
condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24C02C (see Fig. 5). The next three
significant bits are all zeros. The last bit of the slave
address specifies whether a Read or Write operation is
to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write opera­tion is selected.

After the Master sends a START condition and the slave
address byte, the CAT24C02C monitors the bus and
responds with an acknowledge (on the SDA line). The
CAT24C02C then performs a Read or Write operation
depending on the state of the R/W bit.

Acknowledge

After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledg­ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.

The CAT24C02C responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8­bit byte.

When the CAT24C02C is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this acknowl­edge, the CAT24C02C will continue to transmit data. If
no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.

WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24C02C. After receiving another
acknowledge from the Slave, the Master device trans­mits the data byte to be written into the addressed
memory location. The CAT24C02C acknowledge once
more and the Master generates the STOP condition, at
which time the device begins its internal programming
cycle to nonvolatile memory. While this internal cycle is
in progress, the device will not respond to any request
from the Master device.

Page Write

The CAT24C02C writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as
counter will ‘wrap around’ to address 0 and continue to

Figure 4. Acknowledge Timing

5020 FHD F06

ACKNOWLEDGE

1

START

SCL FROM

MASTER

89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

CAT24C02C

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Doc. No. 25086-00 8/99 S-1

the Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT24C02C will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain un­changed.

If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be overwrit­ten.

Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24C02C in a single write cycle.

Acknowledge Polling

The disabling of the inputs can be used to take advan­tage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24C02C initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24C02C is still
busy with the write operation, no ACK will be returned.
If the CAT24C02C has completed the write operation,
an ACK will be returned and the host can then proceed

with thenext read or write operation.

Selective Read

Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24C02C acknowledge the word
address, the Master device resends the START condi­tion and the slave address, this time with the R/W bit set
to one. The CAT24C02C then responds with its ac­knowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by
either the immediate Address READ or Selective READ
operations. After the 24C02C sends initial 8-bit byte
requested, the Master will respond with an acknowledge
which tells the device it requires more data. The
CAT24C02C will continue to output an 8-bit byte for each
acknowledge sent by the Master. The operation is
terminated when the Master fails to respond with an
acknowledge, thus sending the STOP condition.

The data being transmitted from the CAT24C02C is
outputted sequentially with data from address N fol­lowed by data from address N+1. The READ operation
address counter increments all of the CAT24C02C
address bits so that the entire memory array can be read
during one operation. If more than 255 bytes are read
out, the counter will “wrap around” and continue to clock
out data bytes.

Figure 5. Slave Address Bits

READ OPERATIONS

The READ operation for the CAT24C02C is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.

Immediate Address Read

The CAT24C02C’s address counter contains the ad­dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac­cess data from address N+1. If N=E (where E = 255 for
24WC02), then the clock out data. After the CAT24C02C
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8-bit byte requested. The master device does not send
an acknowledge but will generate a STOP condition.

1010000R/W

24C02C

CAT24C02C

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Figure 7. Page Write Timing

5020 FHD F08

Figure 6. Byte Write Timing

BUS ACTIVITY :

MASTER

SDA LINE

DATA n+P

BYTE

ADDRESS (n)

A
C
K

A
C
K

DATA n

A
C
K

S
T

O

P

S

A
C
K

DATA n+1

A
C
K

S
T
A
R
T

P

SLAVE

ADDRESS

NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0

*

BYTE

ADDRESS

SLAVE

ADDRESS

S

A
C
K

A
C
K

DATA

A
C
K

S
T
O
P

P

BUS ACTIVITY :

MASTER

SDA LINE

S
T
A
R
T

5020 FHD F10

Figure 8. Immediate Address Read Timing

SCL

SDA 8TH BIT

STOPNO ACKDATA OUT

89

SLAVE

ADDRESS

S

A
C
K

DATA

N
O

A
C
K

S
T

O

P

P

BUS ACTIVITY :

MASTER

SDA LINE

S
T
A

R

T

CAT24C02C

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Doc. No. 25086-00 8/99 S-1

ORDERING INFORMATION

5020 FHD F12

Figure 10. Sequential Read Timing

Figure 9. Selective Read Timing

SLAVE

ADDRESS

S

A

C

K

N
O

A
C
K

S
T
O
P

P

BUS ACTIVITY :

MASTER

SDA LINE

S
T
A
R
T

BYTE

ADDRESS (n)

S

A

C

K

DATA n

SLAVE

ADDRESS

A

C

K

S
T
A
R
T

*

BUS ACTIVITY :

MASTER

SDA LINE

DATA n+xDATA n

A
C
K

A
C
K

DATA n+1

A
C
K

S

T
O
P

N

O

A
C
K

DATA n+2

A
C
K

P

SLAVE

ADDRESS

Prefix Device # Suffix

24C02C

W

I

Product Number

24C02C: 2K

Package

W: Wafer Form

Operating V oltage

Blank: 2.5V - 6.0V

1.8: 1.8V - 6.0V

-1.8

CAT

Temperature Range

Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*

Optional
Company ID

CAT24C02C

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