Datasheet C2012NPO470JGTS Specification

MLCC NP0 Series approval sheet

Electronics Corp.

Multi-Layer Ceramic Capacitor C-G1-7-00

General Specification

 General introduction:

Ceramic capacitors (or condenser) are widely used in electronic circuitry for coupling, de-coupling and in filters.
These different functions require specific capacitor properties. Ceramic capacitors can be divided into two classes,

 Class 1

In these capacitors dielectric materials are used which have a very high specific resistance, very good Q and linear
temperature dependence.
They are used in such applications as oscillators and filters where low losses, capacitance drift compensation and
high stability are required.

 Class 2

These capacitors have higher losses and have non-linear characteristics. They are used for coupling and
de-coupling.

 Construction:

G 1

The capacitance of a ceramic capacitor depends on the area of the electrodes (A), the thickness of the ceramic
dielectric (t) and the dielectric constant of the ceramic material (ε
multi-layer ceramic capacitors :

C =ε

The standard capacitance unit is the “Farad”. A cap acitor has capacitance of one farad is when one coulomb charges
two parallel conductive plate to one volt potential.
The rated voltage is dependent on the dielectric strength, which is mainly governed by the thickness of the dielectric
layer and the ceramic structure. For this reason a reduction of the layer thickness is limited. Figure 1 shows the
construction of a multi-layer capacitor.
The electrodes are normally mixed palladium with silver since the electrodes are applied before the ceramic is fired
at a temperature where silver would oxidize.

r ε0

 A/t  n

) ; and on the number of dielectric layers (n) with

r

 Manufacturing of ceramic capacitors

The raw materials are finely milled and carefully mixed. Thereafter the powders are calcined at temperatures
between 1100℃ and 1300℃ to achieve the required chemical composition.
Then, the resultant mass is reground and dopes and/or sintering means are added.
The finely ground material is mixed with a solvent and binding matter. Casting or rolling obtains thin sheets. For
multi-layer capacitors electrode material is printed on the sheets and after stacking and pressing of the sheets
co-fired with the ceramic compact at temperatures between 1000℃ and 1400℃.
The totally enclosed electrodes of a multi-layer capacitor guarantee good life test behavior as well.

Darfon Product Specification 1

Electronics Corp.

Multi-Layer Ceramic Capacitor C-G1-7-00

 Operating Voltage

The operating voltage for the capacitors must always be lower than its rated voltage. If an AC voltage is applied, the
peak voltage should be lower than the rated voltage of the capacitor. And if both AC and a pulse voltage may be
presented, then the sum of the peak should also be lower than the rated voltage of the capacitor chosen.

 E Standard Number

E 3 1.0 2.2 4.7

E 6 1.0 1.5 2.2 3.3 4.7 6.8
E12 1.0 1.2 1.5 1.8 2.2 2.7 3.3 3.9 4.7 5.6 6.8 8.2
E24 1.0 1.1 1.2 1.3 1.5 1.6 1.8 2.0 2.2 2.4 2.7 3.0 3.3 3.6 3.9 4.3 4.7 5.1 5.6 6.2 6.8 7.5 8.2 9.1

* Non-standard capacitance is available on request.

 Available Tolerance

G 1

T. C. Capacitance * Standard Tolerance

Cap < 5pF

NP0 (C0G)

X5R
X7R

Y5V E3 Z = -20% to +80% M = ± 20%

5pF ≦ Cap < 10pF D = ± 0.5pF

Cap ≧ 10pF

E12

E6

* Non-standard capacitance is available on request.

C = ± 0.25pF

D = ± 0.5pF

J = ± 5%

K = ±10%

K = ± 10%

M = ± 20%

Available Tolerance

on Request

B = ± 0.1pF

B = ± 0.1pF

C = ± 0.25pF

F = ± 1%

G = ± 2%

J = ± 5%

Darfon Product Specification 2

Electronics Corp.

Multi-Layer Ceramic Capacitor C-G1-7-00

 Physical Outline

Termination

(2) Electrode, PdAg or Ni
(1) Dielectric

(3) Ag or Cu
(4) Ni
(5) Sn

G 1

Material Type

Code

Elements

1 Dielectric TiO2 CaZrO3 BaTiO3 BaTiO3
2 Electrode PdAg Ni PdAg Ni
3 Ag Cu Ag Cu

4 Ni
5

* NME (Nobel Metal Electrode), BME (Base Metal Electrode)

Termination**

Temperature Compensation

NME* BME* NME* BME*

Class I

Sn

** All Darfon’s MLCC products are produced under lead-free plating process and in compliance with the

lead-free requirement of Green Plan and ROHS.

High Permittivity

Class II

Darfon Product Specification 3

Electronics Corp.

A

Multi-Layer Ceramic Capacitor C-G1-7-00

 Dimensions

G 1

L

g

W

T

TYPICAL TOLERANCE

SIZE CODE L W T

(EIA) (Length) (Width) (Max Thickness) (Min) (Termination Min/Max)

0603 0.6+/-0.03 0.3+/-0.03 0.33 0.15 0.10/0.20 mm

(0201) (0.024+/-0.001) (0.012+/-0.001) (0.013) (0.006) (0.004/0.008) (inch)

1005 1.0 +/- 0.05 0.5 +/- 0.05 0.55 0.30 0.10 / 0.30 mm

(0402) (0.040 +/- 0.002) (0.020 +/- 0.002) (0.022) (0.012) (0.004 / 0.012) (inch)

1608 1.6 +/- 0.10 0.8 +/- 0.10 0.90 0.50 0.25 / 0.65 mm

(0603) (0.063 +/- 0.004) (0.031 +/- 0.004) (0.035) (0.020) (0.010 / 0.026) (inch)

2012 2.0 +/- 0.15 1.25 +/- 0.20 1.45 0.70 0.25 / 0.75 mm

(0805) (0.079 +/- 0.006) (0.049 +/- 0.008) (0.057) (0.028) (0.010 / 0.030) (inch)

3216 3.2 +/- 0.15 1.6 +/- 0.20 1.80 1.50 0.25 / 0.75 mm

(1206) (0.126 +/- 0.006) (0.063 +/- 0.008) (0.069) (0.060) (0.010 / 0.030) (inch)

3225 3.2 +/- 0.20 2.5 +/- 0.20 2.70 1.50 0.25 / 0.75 mm

(1210) (0.126 +/- 0.008) (0.098 +/- 0.008) (0.106) (0.060) (0.010 / 0.030) (inch)

g

A

UNIT

SPECIAL TOLERANCE

SIZE CODE L W T

(EIA) (Length) (Width) (Max Thickness) (Min) (Termination Min/Max)

1005* 1.0 +/- 0.15 0.5 +/- 0.15 0.65 0.30 0.10 / 0.30 mm

(0402) (0.040 +/- 0.006) (0.020 +/- 0.006) (0.026) (0.012) (0.004 / 0.012) (inch)

1608* 1.6 + 0.15/-0.1 0.8 + 0.15/-0.1 0.95 0.50 0.25 / 0.65 mm

(0603) (0.063 +0.006/- 0.004) (0.031 +0.006/-0.004) (0.037) (0.020) (0.010 / 0.026) (inch)

2012* 2.0 +/- 0.20 1.25 -0.20/+0.30 1.55 0.70 0.25 / 0.75 mm

(0805) (0.079 +/- 0.008) (0.049 -0.008/+0.012) (0.061) (0.028) (0.010 / 0.030) (inch)

3216* 3.2 +/- 0.20 1.6 -0.20/+0.30 1.90 1.50 0.25 / 0.75 mm

(1206) (0.126 +/- 0.008) (0.063 -0.008/+0.012) (0.075) (0.060) (0.010 / 0.030) (inch)

3225* 3.2 +/- 0.30 2.5 +/- 0.30 2.80 1.50 0.25 / 0.75 mm

(1210) (0.126 +/- 0.012) (0.098 +/- 0.012) (0.11) (0.060) (0.010 / 0.030) (inch)

g

A

UNIT

Darfon Product Specification 4

Electronics Corp.

Multi-Layer Ceramic Capacitor C-G1-7-00

DARFON Part Number

C

1005 NP0 101 J G T S

PRODUCT CODE

C = Capacitor SMD

SIZE in mm (EIA CODE, in inch)

0402(01005) 0603(0201) 1005 (0402) 1608 (0603) 2012 (0805)
3216 (1206) 3225(1210) 4520 (1808) 4532 (1812)

T. C.

NP0: 0 ± 30ppm/℃ -55℃ to +125℃
X7R: ±15% -55℃ to +125℃
X5R: ±15% -55℃ to +85℃
Y5V: +22%/-82% -30℃ to +85℃

CAPACITANCE CODE

Expressed in pico-farads and identified by a three-digit number.
First two digits represent significant figures.
Last digit specifies the number of zeros.
(Use 9 for 1.0 through 9.9pF； Use 8 for 0.2 through 0.99pF)
(Example: 2.2pF=229 or 0.47pF=478)

TOLERANCE CODE

A: ± 0.05pF B: ± 0.1pF C: ± 0.25pF D: ± 0.5pF F: ±1% G: ±2%
J: ±5% K: ±10% M: ±20% Z: +80/-20%

VOL TAGE CODE

B: 4V C: 6.3V D: 10V E: 16V F: 25V N: 35V G: 50V H: 100V
J: 200V K: 250V L: 500V M: 630V P: 1KV Q: 2KV R: 3KV S: 4KV

PACKAGING CODE

T: Paper tape reel Ø180mm (7”) P: Embossed tape reel Ø180mm (7”)
N: Paper tape reel Ø250mm (10”) D: Embossed tape reel Ø250mm (10”)
A: Paper tape reel Ø330mm (13”) E: Embossed tape reel Ø330mm (13”)
B: Bulk, loosed in bag C: Bulk cassette
W: Special Packing

Product Type

S: Standard Ceramic Capacitor
Q: High Q/Low ESR

G 1

Darfon Product Specification 5

Electronics Corp.

Multi-Layer Ceramic Capacitor C-G1-7-00

 Product Range

 NP0 (Class I)

Type Size

T.C. RV 0603 (0201) 1005 (0402) 1608 (0603) 2012 (0805) 3216 (1206)

NPO

Class I

 X7R (Class II)

Type

T.C. RV 0603 (0201) 1005 (0402) 1608 (0603) 2012 (0805) 3216 (1206) 3225 (1210)

X7R

Class II

16V 2.7nF~3.3nF 12nF~39nF
25V 0.20pF~100pF 0.20pF~22pF
50V 0.20pF~18pF 0.20pF~470pF/1nF 0.20pF~2.2nF 0.50pF~10nF 1.50pF~10nF

100V 0.20pF~220pF 0.20pF~1nF 0.50pF~3.3nF 1.50pF~4.7nF

Size

6.3V 4.7uF~10uF
10V 3.3nF/4.7nF/10nF 100pF~100nF 100pF~1uF 1uF/2.2uF/4.7uF/10uF 2.2uF
16V 100pF~100nF 100pF~1uF 330nF/470nF/1uF/ 2.2uF 470nF~10uF 10uF
25V 100pF~2.2nF 100pF~22nF 100pF~1uF 1nF~1uF 220nF~4.7uF 4.7uF/10uF
50V 100pF~2.2nF 100pF~10nF 100pF~100nF 150pF~470nF 1nF~1uF

100V 100pF~10nF 150pF~22nF 1nF~100nF

G 1

 X5R (Class II)

Type Size

T.C. RV 0603 (0201) 1005 (0402) 1608 (0603) 2012 (0805) 3216 (1206) 3225 (1210)

6.3V 2.2nF~220nF 470nF~4.7uF 2.2uF/ 4.7uF/10uF 4.7uF~22uF 22uF/47uF 47uF/100uF

X5R

Class

10V 2.2nF~100nF 15nF~1uF 220nF~4.7uF 2.2uF~10uF 2.2uF~10uF 22uF
16V 15nF~1uF 220nF~2.2uF 1uF~10uF 2.2uF~10uF 4.7uF~22uF

II

25V 100nF 220nF/1uF 1uF~4.7uF 2.2uF~10uF 4.7uF/ 10uF

 Y5V (Class II)

Type Size

T.C. RV 0603 (0201) 1005 (0402) 1608 (0603) 2012 (0805)

6.3V

22nF~100nF 10nF~1uF 10nF~2.2uF

Y5V

Class II

Note：(1) Other size, capacitance, and voltage are available upon customer’s request.

10V 10nF~1uF 10nF~2.2uF
16V 10nF~220nF 10nF~2.2uF 100nF~2.2uF

25V
50V

10nF~100nF 10nF~330nF 100nF ~2.2uF
10nF~33nF 10nF~220nF 100nF~1uF

(2) Product range might be extended due to technology improvement or new product released；for up-to-dat e information,

please contact our sales.

(3) Part of Y5V product will be phased out.

Darfon Product Specification 6

Electronics Corp.



Multi-Layer Ceramic Capacitor C-G1-7-00

 Packaging

 Tape and Reel Packaging

Tape and reel packaging is currently the most promising system for high-speed production. A typical 180mm (7
inch) diameter reel contains 1,500 to 15,000 capacitors, 250mm (10 inch) contains 10,000 capacitors, and
330mm(13 inch) contains 10,000 to 50,000 capacitors. Three standard sizes are available in taped and reeled
package either with paper carrier tapes or embossed tapes.

 Reel Specifications

13.0+/-0.5

2.0+/-0.5

21.0+/-0.8

10.0+/-1.5 for 8mm wide tape

14.0+/-1.5 for 12mm wide tape

T

D

50 min.

G

TAPE WIDTH

(mm)

8

8

G

(mm)

10.0 +/- 1.5 14.5 180

10.0 +/- 1.5 14.5 250

T max.

(mm)

D

(mm)

8

12

10.0 +/- 1.5 14.5 330

14.0 +/- 1.5 18.5 180

Darfon Product Specification 7

Electronics Corp.

A

Multi-Layer Ceramic Capacitor C-G1-7-00

 Paper Tape Specifications

2mm and 4mm pitch tape

4.0+/-0.1

P

1.5

+0.1

- 0.0

2.0+/-0.05

B

1.75+/-0.1

F

1.1 max.

W

G 1

SYMBOL

A

B

F

P

W

Direction of feed

PRODUCT SIZE CODE

0603 (0201) 1005 (0402) 1608 (0603) 2012 (0805) 3216 (1206)

SIZE TOL. SIZE TOL. SIZE TOL. SIZE TOL. SIZE TOL.

Cardboard

UNIT

0.38 +/- 0.04 0.60 +/- 0.04 1.0 +/- 0.2 1.5 +/- 0.2 1.9 +/- 0.2 mm

0.68 +/- 0.04 1.12 +/- 0.04 1.8 +/- 0.2 2.3 +/- 0.2 3.6 +/- 0.2 mm

3.50 +/- 0.05 3.50 +/- 0.05 3.5 +/- 0.05 3.5 +/- 0.05 3.5 +/- 0.05 mm

2.00 +/- 0.10 2.00 +/- 0.10 4.0 +/- 0.1 4.0 +/- 0.1 4.0 +/- 0.1 mm

8.00 +/- 0.20 8.00 +/- 0.20 8.0 +/- 0.2 8.0 +/- 0.2 8.0 +/- 0.2 mm

Darfon Product Specification 8

Electronics Corp.

A

Multi-Layer Ceramic Capacitor C-G1-7-00

 Embossed Tape Specifications

4mm and 8mm pitch tape

D

P

1

0

P

0

K

P

2

E

0

T

G 1

0

B

0

D

1

Direction of feed

ko: so chosen that the orientation of the component cannot change.
For W= 8mm: T
For W= 12mm: T

=2.5mm max.

2

= 4.5mm

2

PRODUCT SIZE CODE

DIMENSION

(mm)

P1
PO
P2

A0 nominal clearance*
B0 nominal clearance*

2012 (0805) 3216 (1206) 3225 (1210) 4520 (1808) 4532 (1812)

4 4 4 8 8 +/- 0.10
4 4 4 4 4 +/- 0.10
2 2 2 2 2 +/- 0.05

0.2 0.3 0.3 0.4 0.4 -

0.2 0.3 0.3 0.4 0.4 -

4 mm tape 8 mm tape

Top tape

F

W

T

1

T

2

TOLERANCE

(mm)

K0 minimum clearance*

W

E

F
D0
D1

T

T1
T2

0.05 0.05 0.05 0.05 0.05 -

8.0 8.0 8.0 12.0 12.0 +/- 0.20

1.75 1.75 1.75 1.75 1.75 +/- 0.10

3.5 3.5 3.5 5.5 5.5 +/- 0.05

1.5 1.5 1.5 1.5 1.5 +0.1/-0.0

1 min 1 min 1 min 1.5 min 1.5 min +0.1/-0.0

0.25 0.25 0.25 0.25 0.25 +/- 0.10

0.05 0.05 0.05 0.05 0.05 +/- 0.01

2.5 max. 2.5 max. 2.5 max. 4.5 4.5

* Typical capacitors displace in pocket.

Darfon Product Specification 9

-

Electronics Corp.

Multi-Layer Ceramic Capacitor C-G1-7-00

 Thickness and Taping Amount

G 1

Thickness

Code Spec Size(EIA) Paper Embossed Paper Embossed Paper Embossed

A 0.30+/-0.03 0603 (0201) 15K
B 0.50+/-0.05 1005 (0402) 10K 50K
B 0.50+/-0.15 1005 (0402) 10K 50K
Q 0.45+/-0.05 1005 (0402) 10K 50K

C 0.60+/-0.15
Q 0.45+/-0.05 1608(0603) 4K 10K 15K

D 0.80+/-0.10 1608(0603) 4K 10K 15K
D 0.80+0.15/ -0.10 1608 (0603) 4K 10K 15K

E 0.85+/-0.15

I 0.95+/-0.15

F 1.15+/-0.20

G 1.25 +/-0.20

G 1.25+0.3/-0.2

L 1.60+/-0.20

L 1.60+0.30/-0.20

N 2.00+/-0.20

N 2.00+/-0.30 3225 (1210) 2K
P 2.50+/-0.20 3225(1210) 500pcs/1K
P 2.50+/-0.30 3225(1210) 500pcs/1K

2012 (0805) 4K 10K 15K

3216(1206) 4K 10K 15K

2012 (0805) 4K 10K 15K
3216 (1206) 4K 10K 15K
3225 (1210) 3K 10K
4532 (1812) 1K

2012(0805) 3K

3216(1206) 3K
3216 (1206) 3K 10K
4520 (1808) 3K
2012 (0805) 2K/3K 10K
3216 (1206) 3K 10K
3225 (1210) 3K

4520(1808) 3K

4532(1812) 1K

2012(0805) 2K/3K 10K

3216(1206) 3K 10K

3225(1210) 3K

3216(1206) 2K

3225(1210) 2K

4520(1808) 2K

4532(1812) 1K

3216(1206) 2K

3225(1210) 2K

4520(1808) 2K

45321812) 1K
3216 (1206) 2K/3K
3225 (1210) 2K
4520 (1808) 1K

4532(1812) 1K

180 mm (7”) 250 mm (10”) 330 mm (13”)

Amount per reel

Darfon Product Specification 10

Electronics Corp.

Multi-Layer Ceramic Capacitor C-G1-7-00

 Peeling Off Force

Peeling off force: 0.1N to 1.0N in the direction shown below.
The peeling speed: 300+/-10 mm/min

165 ° to 180°

1. The taped tape on reel is wound clock wise. The sprocket holes are to the right as the tape is pulled toward the
user.

2. There are minimum 150 mm as the leader and minimum 40 mm empty tape as the tail be attached to the end of
the tape.

Peeling force

Top tape

Base tape

Darfon Product Specification 11

Electronics Corp.

Multi-Layer Ceramic Capacitor C-S1-7-00

C0G (NP0) Dielectrics

 Features

 A monolithic structure ensures high reliability and mechanical strength.

 High capacitance density.

 A wide range of capacitance values in standard case size.

 Suitable for high speed SMT placement on PCBs.

 Ni barrier termination highly resistance to migration.

 Lead-free termination is in compliance with the requirement of green plan and ROHS.

 Applications

 General electronic equipment.

 Custom Application

S 1

 C0G (NP0) Dielectric Characteristics

Capacitance Range 0.20pF to 39nF

Size (mm)

(EIA inch)

Test Voltage 1.0 ± 0.2Vrms

Test Frequency

Capacitance Tolerance

Operating Temperature Range

Maximum Capacitance Change

Rated Voltage 16, 25, 50, 100 VDC

Dissipation Factor (DF)

Insulation Resistance (+25℃, RVDC)

Insulation Resistance (+125℃, RVDC)

0603 1005 1608 2012 3216

(0201) (0402) (0603) (0805) (1206)

1.0 ± 0.2MHz for cap≦1,000pF, 1.0 ± 0.2KHz for cap＞1,000pF

± 0.25pF, ± 0.50pF for cap＜5pF (± 0.1pF available on request)

± 0.50pF for 5pF≦cap＜10pF (± 0.1pF, ± 0.25pF available on request)

± 5%, ± 10% for cap≧10pF (± 1%, ± 2% available on request)

-55℃ to +125℃

0 ± 30 ppm/℃ (EIA C0G)

1/(400 + 20 x C) for cap≦30pF, C in pF ；0.1% max. for cap＞30pF

10,000 M min. or 500-F min., whichever is smaller

1,000 M min. or 50-F min., whichever is smaller

Darfon Product Specification 1

Electronics Corp.

Multi-Layer Ceramic Capacitor C-S1-7-00

 Product Range and Thickness

CLASS Class I

TYPE Standard

T.C. C0G (NP0)
SIZE 0603 1005 1608 2012 3216
(EIA) 0201 0402 0603 0805 1206

RV 25V 50V 50V 100V 16V 50V 100V 50V 100V 16V 50V 100V

0.20 p B B D D

0.50 p A A B B D D C C

0.75 p A A B B D D C C

1.0 p A A B B D D C C

1.2 p A A B B D D C C

1.5 p A A B B D D C C E E

1.8 p A A B B D D C C E E

2.2 p A A B B D D C C E E

2.7 p A A B B D D C C E E

3.3 p A A B B D D C C E E

3.9 p A A B B D D C C E E

4.7 p A A B B D D C C E E

5.6 p A A B B D D C C E E

6.8 p A A B B D D C C E E

8.2 p A A B B D D C C E E

10 p A A B B D D C C E E

12 p A A B B D D C C E E

15 p A A B B D D C C E E

18 p A A B B D D C C E E

22 p A B B D D C C E E

27 p A B B D D C C E E

33 p A B B D D C C E E

39 p A B B D D C C E E

47 p A B B D D C C E E

56 p A B B D D C C E E

68 p A B B D D C C E E

82 p A B B D D C C E E

 Non-standard capacitance or thickness is available on request
 The thickness might be changed due to technology improvement.
 * Special length/width tolerance

S 1

Thickness Tolerance

Thickness (mm) Thickness (mm) Thickness (mm) Thickness (mm) Thickness (mm) Thickness (mm)

Code Class Code Class Code Class Code Class Code Code Code Code

A 0.30+/-0.03 C 0.60+/-0.15 E 0.85+/-0.15 G 1.25 -0.20/+0.30 L 1.60+0.3/-0.20 P 2.50+/-0.20
B 0.50+/-0.05 D 0.80+/-0.10 F 1.15+/-0.20 I 0.95+/-0.15 N 2.00+/-0.20 Q 0.45+/-0.05
B 0.50+/-0.15 D 0.8+0.15/-0.1 G 1.25+/-0.20 L 1.60+/-0.20 N 2.00+/-0.30

Special Length/Width Tolerance

Size Code(EIA) 1005(0402) 1608(0603) 2012(0805) 3216(1206) 3225(1210)

Length(mm) 1.0 ± 0.15 1.6 ± 0.15 2.0 ± 0.20 3.2 ± 0.20 3.2 ± 0.30

Width(mm) 0.5 ± 0.15 0.8 ± 0.15 1.25 ± 0.30 1.6 ± 0.30 2.5 ± 0.30

Darfon Product Specification 2

Electronics Corp.

Multi-Layer Ceramic Capacitor C-S1-7-00

Continued from previous page.

 Product Range and Thickness

CLASS Class I

TYPE Standard

T.C. C0G (NP0)

SIZE 0603 1005 1608 2012 3216
(EIA) 0201 0402 0603 0805 1206

RV 25V 50V 50V 100V 16V 50V 100V 50V 100V 16V 50V 100V

100 p A B B D D C C E E
120 p B B D D C C E E
150 p B B D D C C E E
180 p B B D D C C E E
220 p B B D D C C E E
270 p B D D C C E E
330 p B D D C C E E
390 p B D D C E E E
470 p B D D C E E E
560 p D D C E E E
680 p D D C E E E
820 p D D C E E E

1.0 n B D D C E E E

1.2 n D* E E E E

1.5 n D* E E E E

1.8 n D* E E E E

2.2 n D* E E E E

2.7 n D* G G E E

3.3 n D* G G E E

3.9 n G E E

4.7 n G E E

5.6 n G E

6.8 n G F

8.2 n G F

10 n G G

12 n G

15 n G

18 n G

22 n G

27 n G

33 n G

39 n L

 Non-standard capacitance or thickness is available on request
 The thickness might be changed due to technology improvement.
 * Special length/width tolerance

Thickness Tolerance

Thickness (mm) Thickness (mm) Thickness (mm) Thickness (mm) Thickness (mm) Thickness (mm)

Code Class Code Class Code Class Code Class Code Code Code Code

A 0.30+/-0.03 C 0.60+/-0.15 E 0.85+/-0.15 G 1.25 -0.20/+0.30 L 1.60+0.3/-0.20 P 2.50+/-0.20
B 0.50+/-0.05 D 0.80+/-0.10 F 1.15+/-0.20 I 0.95+/-0.15 N 2.00+/-0.20 Q 0.45+/-0.05
B 0.50+/-0.15 D 0.8+0.15/-0.1 G 1.25+/-0.20 L 1.60+/-0.20 N 2.00+/-0.30

Special Length/Width Tolerance

Size Code(EIA) 1005(0402) 1608(0603) 2012(0805) 3216(1206) 3225(1210)

Length(mm) 1.0 ± 0.15 1.6 ± 0.15 2.0 ± 0.20 3.2 ± 0.20 3.2 ± 0.30

Width(mm) 0.5 ± 0.15 0.8 ± 0.15 1.25 ± 0.30 1.6 ± 0.30 2.5 ± 0.30

S 1

Darfon Product Specification 3

Electronics Corp.

Multi-Layer Ceramic Capacitor C-S1-7-00

T aping Amount

Thickness

Code Spec Size(EIA) Paper Embossed Paper Embossed Paper Embossed

A 0.30+/-0.03 0603 (0201) 15K
B 0.50+/-0.05 1005 (0402) 10K 50K
B 0.50+/-0.15 1005 (0402) 10K 50K
Q 0.45+/-0.05 1005 (0402) 10K 50K

C 0.60+/-0.15
Q 0.45+/-0.05 1608(0603) 4K 10K 15K

D 0.80+/-0.10 1608(0603) 4K 10K 15K
D 0.80+0.15/ -0.10 1608 (0603) 4K 10K 15K

E 0.85+/-0.15

I 0.95+/-0.15

F 1.15+/-0.20

G 1.25 +/-0.20

G 1.25+0.3/-0.2

L 1.60+/-0.20

L 1.60+0.30/-0.20

N 2.00+/-0.20

N 2.00+/-0.30 3225 (1210) 2K
P 2.50+/-0.20 3225(1210) 500pcs/1K
P 2.50+/-0.30 3225(1210) 500pcs/1K

2012 (0805) 4K 10K 15K

3216(1206) 4K 10K 15K

2012 (0805) 4K 10K 15K
3216 (1206) 4K 10K 15K
3225 (1210) 3K 10K
4532 (1812) 1K

2012(0805) 3K

3216(1206) 3K
3216 (1206) 3K 10K
4520 (1808) 3K
2012 (0805) 2K/3K 10K
3216 (1206) 3K 10K
3225 (1210) 3K

4520(1808) 3K

4532(1812) 1K

2012(0805) 2K/3K 10K

3216(1206) 3K 10K

3225(1210) 3K

3216(1206) 2K

3225(1210) 2K

4520(1808) 2K

4532(1812) 1K

3216(1206) 2K

3225(1210) 2K

4520(1808) 2K

45321812) 1K
3216 (1206) 2K/3K
3225 (1210) 2K
4520 (1808) 1K

4532(1812) 1K

180 mm (7”) 250 mm (10”) 330 mm (13”)

Amount per reel

Darfon Product Specification 4

Electronics Corp.

0



Multi-Layer Ceramic Capacitor C-S1-7-00

C0G (NP0) Specifications

1 Operating Temperature Range NP0: -55 to 125 degree C ---

2 Rated Voltage 16VDC, 25VDC, 50VDC, 100VDC, The rated voltage is defined as the maximum voltage, which

3 Appearance No defects or abnormalities. Visual inspection
4 Dimensions Within the specified dimension. Using calipers
5 Dielectric Strength No defects or abnormalities. No failure shall be observed when 250% of the rated voltage is

6 Insulation Resistance ( I.R.)

7 Capacitance Within the specified tolerance

8 Q/Dissipation Factor ( D.F.) NP0:

9 Capacitance Temperature

Characteristics

10 Termination Strength No removal of the terminations or marking defect. Apply a parallel force of 5N to a PCB mounted sample for

11 Deflection (Bending Strength)

Item Specification Test Method

may be applied continuously to the capacitor.

applied between the terminations for 1 to 5 seconds. The

Rated Voltage: <500V To apply rated

Rated Voltage: ≧500V To apply 500V.

If C≦30pF, DF≦1/(400+20C), C in pF

If C >30pF, DF≦0.1%.

Capacitance change within 0±30ppm/ ℃ under operating

temperature range.

No cracking or marking defects shall occur at 1mm deflection.

Capacitance change:

NPO: within ±5% or ± 0.5pF. (whichever is larger)

(Unit in mm)

t :1.6mm(0.8mm for 0603&1005 size)

Fig. a.

100

voltage.

b

c

a

4.5

I.R. ≧10G or

RiCR≧500Ω-F

(whichever is
smaller)

Size a b C

0603 0.3 0.9 0.3

4

1005 0.4 1.5 0.5

1608 1.0 3.0 1.2

2012 1.2 4.0 1.65

3216 2.2 5.0 2.0

charge and discharge current is less than 50mA.

The insulation resistance shall be measured with a DC voltage
not exceeding the rated voltage at 25℃ and 75%RH max, and

within 1 minute of charging.

The capacitance / D.F. shall be measured at 25℃ at the

frequency and voltage shown in the tables.

Item Class I

Frequency 1.0±0.2MHz 1.0±0.2kHz

Voltage 1.0±0.2Vrms 1.0±0.2Vrms

Temperature compensating type:

The capacitance value at 25 ℃ and 85 ℃ shall be

measured and calculated from the formula given below.

T.C . =( C85-C25)/C25*ΔT*106(PPM/℃)

10±1sec. *2N for 0603 (EIA 0201).

Solder the capacitor to the test jig (glass epoxy boards) shown

in Fig.a using a SAC305(Sn96.5Ag3.0Cu0.5) solder (then let sit

for 48±4 hours for X7R X5R and Y5V).

Then apply a force in the direction shown in Fig.b. The

soldering shall be done with the reflow method and shall be

conducted with care so that the soldering is uniform and free of

defects such as heat shock.

C≦1,000pF

R230

Capacitance Meter

45

Fig. b.

20

Class I

＞1,000pF

50

Pressurizing speed : 1.0mm/sec.

Pressurize

45

Flexure : 1mm

12 Solderability of Termination 90% of the terminations are to be soldered evenly and

continuously.

Immerse the test capacitor into a methanol solution containing
rosin for 3 to 5 seconds, preheat it 150 to 180℃ for 2 to 3

minutes and immerse it into Sn-3.0Ag-0.5Cu solder of 245 ± 5
℃ for 3±1seconds.

Darfon Product Specification 5

Electronics Corp.

Multi-Layer Ceramic Capacitor C-S1-7-00

Continued from previous page.

Specification

Temp. compensating type

Test Method

*Preheat the capacitor at 120 to 150 for 1 minute. ℃

Immerse the capacitor in a SAC305(Sn96.5Ag3.0Cu0.5)

solder solution at 270±5 for 10±1 seconds. Let sit at room ℃

temperature for 24±2 hours (temperature compensating type)

or 48±4 hours (high dielectric constant type), then measure.

* Preheat 150 to 200 for size℃≧3216.

Initial measurement : perform a heat treatment at 150+0/-10 ℃

for one hour and then let sit for 48±4 hours at room

temperature. Perform the initial measurement.

Solder the capacitor to supporting jig (glass epoxy board) and

perform the five cycles according to the four heat treatments

listed in the following table. Let sit for 24±2hrs at room

temperature, then measure.

Step 1: Minimum operating temperature 30±3min

Step 2: Room temperature 2~3 min

Step 3: Maximum operating temperature 30±3min

Step 4: Room temperature 2~3min

13 Resistance to

Soldering Heat

14 Temperature cycle

(Thermal shock)

Item

Appearance No marking defects

Cap. Change NP0 within ±2.5% or 0.25pF ( whichever is larger )

Q/D.F. If C≦30pF, DF≦1/(400+20C)

If C >30pF, DF≦0.1%

I.R. I.R.≧10,000M or RiCR≧500-F.

(whichever is smaller)

Appearance No marking defects

Cap. Change NP0 within ±2.5% or 0.25pF ( whichever is larger )

Q/D.F. If C≦30pF, DF≦1/(400+20C)

If C >30pF, DF≦0.1%

I.R. I.R.≧10,000M or RiCR≧500-F.

(whichever is smaller)

15 Humidity load

16 High temperature

load life test

Appearance No marking defects

Cap. Change NP0 within ±7.5% or 0.75pF ( whichever is larger )

Q/D.F.

I.R. I.R.≧500M or RiCR≧25-F.

Appearance No marking defects

Cap. Change NP0 within ±7.5% or 0.75pF ( whichever is larger )

Q/D.F.

I.R. More than 1GΩ or RiCr≧50 -F (whichever is less.)

If C＞30pF, DF≦0.5%

If C≦30pF,D≦1/(100+10xC/3) C in pF

(whichever is smaller)

If C＞30pF, DF≦0.3%

If 10pF<C≦30pF, DF≦1/(275+5xC/2)

If C≦10pF, DF≦1/(200+10C), C in pF

Apply the rated voltage a t 40±2℃ and 90 to 95% humidity for

500±12 hours. Remove and let sit for 24±2 hours (temperature

compensating type) or 48±4 hours (high dielectric constant

type) at room temperature, then measure.

The charge / discharge current is less than 50mA.

Apply 200% of the rated voltage for 1000±12 hours at the

maximum operating temperature ± 3℃. Let sit for 24± 2 hours

(temperature compensating type) or 48±4 hours (high dielectric

constant type) at room temperature, then measure.

The charge/discharge current is less than 50mA.

Darfon Product Specification 6

Electronics Corp.

Multi-Layer Ceramic Capacitor C-C1-1-00

Typical Characteristic Curves

 Temperature Coefficient

 Class 1 (Temperature Compensation series)

Temperature Coefficient of Temperature Compensation Series

0.40

0.30

0.20

C/C (%)



0.10

0.00

-0.10

Capacitance Change,

-0.20

-0.30

-0.40

-80 -60 -40 -20 0 20 40 60 80 100 120 140

HP 4278A at 1MHz, 1Vrms

C 1

NP0

Temperature (℃)

Darfon Product Specification 1 Rev.: 0

Electronics Corp.

X7RX

X

R

Multi-Layer Ceramic Capacitor C-C1-1-00

 Class 2 (High Dielectric Constant Series)

Temperature Coefficient of High Dielectric Constant Series

40

HP 4278A at 1KHz, 1Vrms

20

0

C/C (%)



-20

-40

-60

Capacitance Change,

-80

-100

-80 -60 -40 -20 0 20 40 60 80 100 120 140

 Capacitance Change vs. DC bias Voltage

Temperature (

℃

C 1

5R

Y5V

)

C/C (%)

ٛ

Capacitance Change,

-100%

Capacitance Change vs. DC Bias

20%

0%

-20%

-40%

-60%

-80%

HP 4284A, 1MHz for NP0
HP 4284A, 1KHz for X5R,X7R,Y5V

NP0

7R / X5

Y5V

0 2 4 6 8 10 12 14 16 18 20

DC Bias (Volt)

Darfon Product Specification 2 Rev.: 0

Electronics Corp.

X

X

pF

Multi-Layer Ceramic Capacitor C-C1-1-00

Impedance vs. Frequency

Typical Impedance |Z| vs. Frequency

1000.00

100.00

10.00

Impedance (Ω)

1.00

7R 0603 1nF

7R 0603 10nF

Y5V 0603 0.1uF

NP0 0603 10

NP0 0603 1pFNP0 0603 100pF

HP 4287A+16196A, 0.5V

C 1

0.10

0.01

1 10 100 1000 10000

Frequency (MHz)

Darfon Product Specification 3 Rev.: 0

Electronics Corp.

X

Multi-Layer Ceramic Capacitor C-C1-1-00

■ Aging Rate

10.0

5.0

0.0

-5.0

-10.0

-15.0

Capacitance Change Percent (%)

-20.0

-25.0

-30.0
1 10 100 1000 10000 100000

Typical Curve of Aging Rate of Different Dielectric Material

C 1

NP0

7R, X5R

Y5V

Tim e (Hou rs )

Darfon Product Specification 4 Rev.: 0

Electronics Corp.

Multi-Layer Ceramic Capacitor C-A1-4-00

Application Note

 Circuit Design

1. Once application and assembly environments have been checked, the capacitor may be used in conformance
with the rating and performance, which are provided in both the catalog and the specifications. E xceeding the
specifications listed may result in inferior performance. It may also cause a short, open, smoking, or flaming to
occur, etc.

2. Please use the capacitors in conformance with the operating temperature provided in both the catalog and the
specifications. Be especially cautious not to exceed the maximum temperature. In the situation the maximum
temperature set forth in both the catalog and specifications is exceeded, the capacitor’s insulation resistance
may deteriorate, power may suddenly surge and short-circuit may occur. The loss of capacitance will occur, and
may self-heat due to equivalent series resistance when alternating electric current is passed through. As this
effect becomes critical in high frequency circuits, please exercise with caution. When using the capacitor in a
(self-heating) circuit, please make sure the surface of the capacitor remains under the maximum temperature for
usage. Also, please make certain temperature rise remain below 20 .℃

3. Please keep voltage under the rated voltage, which is applied to the capacitor. Also, please make certain the
peak voltage remains below the rated voltage when AC voltage is super-imposed to the DC voltage. In the
situation where AC or pulse voltage is employed, ensure average peak voltage does not exceed the rated
voltage. Exceeding the rated voltage provided in both catalog and specifications may lead to defective
withstanding voltage or, in worse case situations, may cause the capacitor to burn out.

4. It’s is a common phenomenon of high-dielectric products to have a deteriorated amount of static electricity due to
the application of DC voltage.

 Storage

1. The chip capacitors shall be packaged in carrier tapes or bulk cases.

2. Keep storage place temperatures from + 5℃ to +35℃, humidity from 45 to 70% RH.

3. The storage atmosphere mus t be free of gas containing sulfur and chlorine. Also, avoid exposing the product to
saline moisture. If the product is exposed to such atmospheres, the terminations will oxidize and solderability will
be affected.

4. The solderability is assured for 12 months from our final inspection date if the above storage condition is
followed.

Darfon Product Specification 1 Rev.: 3

Electronics Corp.

A

Multi-Layer Ceramic Capacitor C-A1-4-00

 Handling

Chip capacitors should be handled with care to avoid contamination or damage. The use of vacuum pick-up or
plastic tweezers is recommended for manual placement. Tape and reeled packages are suitable for automatic pick
and placement machine.

 Flux

1. An excessive amount of flux or too rapid temperature rise can causes solvent burst, solder can generate a large
quantity of gas. The gas can spreads small solder particles to cause solder balling effect or bridging problem.

2. Flux containing too high of a percentage of halide may cause corrosion of termination unless sufficient cleaning
is applied.

3. Use rosin-type flux. Highly acidic flux (halide content less than 0.2wt%) is not recommended.

4. The water soluble flux causes deteriorated in sulation resistance between outer terminations unless sufficiently
cleaned.

 Component Spacing

For wave soldering components, the spacing must be sufficient far apart to prevent bridging or shadowing. This is
not so important for reflow process but sufficient space for rework should be considered. The suggested spacing for
reflow soldering and wave soldering is 0.5mm and 1.0mm, respectively.

 Solder Fillet

Too much solder amount may increase solder stress and cause crack risk. Insufficient solder amount may reduce
adhesive strength and cause parts falling off PCB. When soldering, confirm that the solder is placed over 0.2mm of
the surface of the terminations.

Joint

Land

Resist

Max. buildup

Min. buildup

0.20mm Min.

PCB

dhesive

Darfon Product Specification 2 Rev.: 3

Electronics Corp.

Multi-Layer Ceramic Capacitor C-A1-4-00

 Recommended Land Pattern Dimensions

When mounting the capacitor to substrate, it’s important to consider carefully that the amount of solder (size of fillet)
used has a direct effect upon the capacitor once it’s mounted.

1. The greater the amount of solder, the greater the stress to the elements. As this may cause the substrate to
break or crack.

2. In the situation where two or more dev ices are mounted onto a common land separate the device into exclusive
pads by using soldering resist.

3. Land width equal to or less than component. It is permissible to reduce land width to 80% of component width.

Land Pattern

b

Size mm (EIA) L x W (mm) a (mm) b (mm) c (mm)

0603 (0201) 0.6*0.3 0.15 to 0.35 0.2 to 0.3 0.25 to 0.3
1005 (0402) 1.0*0.5 0.3 to 0.5 0.35 to 0.45 0.4 to 0.5
1608 (0603) 1.6*0.8 0.7 to 1.0 0.6 to 0.8 0.7 to 0.8
2012 (0805) 2.0*1.25 1.0 to 1.3 0.7 to 0.9 1.0 to 1.2
3216 (1206) 3.2*1.6 2.1 to 2.5 1.0 to 1.2 1.3 to 1.6
3225 (1210) 3.2*2.5 2.1 to 2.5 1.0 to 1.2 2.0 to 2.5
4520 (1808) 4.5*2.0 3.2 to 3.8 1.2 to 1.4 1.7 to 2.0
4532 (1812) 4.5*3.2 3.2 to 3.8 1.2 to 1.4 2.7 to 3.2

Soldering resist

SMD capacitor

c

a

Darfon Product Specification 3 Rev.: 3

Electronics Corp.

0

Multi-Layer Ceramic Capacitor C-A1-4-00

 Resin Mold

If a large amount of resin is used for molding the chip, cracks may occur due to contraction stress during curing. To
avoid such cracks, use a low shrinkage resin. The insulation resistance of the chip will degrade due to moisture
absorption. Use a low moisture absorption resin. Check carefully that the resin does not generate a decomposition
gas or reaction gas during the curing process or during normal storage. Such gases may crack the chip capacitor or
damage the device itself.

 Soldering Profile for SMT Process with SnPb Solder Paste

 Reflow Soldering

300

250

200

T

Soldering

220℃ to 230℃

Within 10 sec.

200℃

Gradual
Natural Cooling

Temperature (℃)

Preheating

60 sec. min.

120 sec. max.

The difference between solder and chip surface should be controlled as following table. The rate of preheat should
not exceed 4℃/sec and a target of 2℃/sec is preferred.

Chip Size 3216 and smaller 3225 and above

Preheating T150℃ T130℃

Within 40 sec.

Time (sec.)

Darfon Product Specification 4 Rev.: 3

Electronics Corp.





Multi-Layer Ceramic Capacitor C-A1-4-00

 Wave Soldering

300

250

T

Temperature (℃)

Preheating

0

60 sec. ~ 120 sec.

Soldering

230℃ to 260℃

Gradual
Natural Cooling

Time (sec.)

5 sec. max.

 Soldering Iron

Chip Size 3216 and smaller 3225 and above

Preheating T150℃ -

1. Soldering iron wattage 20W maximum.

2. Iron-tip diameter  3.0mm maximum.

300
270

Temperature (℃)

Preheating

0

60 sec. ~ 120 sec.

270℃ to 300℃

T

Soldering

Gradual
Natural Cooling

Time (sec.)

3 sec. max.

Chip Size 3216 and smaller 3225 and above

Preheating T190℃ T130℃

Darfon Product Specification 5 Rev.: 3

Electronics Corp.

Multi-Layer Ceramic Capacitor C-A1-4-00

 Soldering

 Reflow Soldering for Lead free T ermination

Soldering

300

240℃ to 260℃

Within 10 sec.

250

200

Temperature (℃)

The difference between solder and chip surface should be controlled as following table. The rate of preheat should
not exceed 4℃/sec and a target of 2℃/sec is preferred.

Preheating T150℃ T130℃

T

Preheating

0

60 sec. min.

120 sec. max.

Chip Size 3216 and smaller 3225 and above

Over 200℃
Within 90 sec.

Gradual
Natural Cooling

Time (sec.)

 Flow Soldering for Lead free Termination

300

250

200

T

Soldering

240℃ to 260℃

Gradual
Natural Cooling

Temperature (℃)

Preheating

60 sec. ~ 120 sec.

3 ~ 5 sec.

Time (sec.)

Chip Size 3216 and smaller 3225 and above

Preheating T150℃ -

Darfon Product Specification 6 Rev.: 3

Electronics Corp.



Multi-Layer Ceramic Capacitor C-A1-4-00

 Soldering Iron

300
270

1. Soldering iron wattage 20W maximum.

2. Iron-tip diameter 3.0mm maximum.

Soldering

270℃ to 300℃

Gradual

T

Natural Cooling

Temperature (℃)

Preheating

0

Time (sec.)

60 sec. ~ 120 sec.

3 sec. max.

Chip Size 3216 and smaller 3225 and above

Preheating T190℃ T130℃

Darfon Product Specification 7 Rev.: 3

Electronics Corp.

Multi-Layer Ceramic Capacitor C-A1-4-00

 Chip Layout and Breaking PCB

1. To layout the SMD capacitors for reducing bend stress from board deflection of PCB. The following are

examples of good and bad layout.

Recommended Not Recommended

2. When breaking PCB, the layout should be noted that the mechanical stresses are depending on the position of

capacitors. The following example shows recommendation for better design.

Perforation

E

D

C

Slit

A

B

Magnitude of stresses A > B = C > D > E

Darfon Product Specification 8 Rev.: 3

Electronics Corp.

X

Multi-Layer Ceramic Capacitor C-A1-4-00

 Aging

The capacitance and dissipation factor of class 2 capacitors decreases with time. It is known as ‘aging’ that follows a
logarithmic low and expressed in terms of an aging constant. Aging is caused by a gradual re-alignment of the
crystalline structure of the ceramic. The aging constant is defined as the percentage loss of capacitance at a ‘time
decade’. The law of capacitance aging is expressed as following equation:

Ct2 = Ct1 x (1 – k x log10(t2/t1))
Ct1: Capacitance after t1 hours of start aging.
Ct2: Capacitance after t2 hours of start aging.
k: aging constant (capacitance decrease per decade)
t1, t2: time in hours from start of aging.

A typical curve of aging rate is shown in following figure.

Typical Curve of Aging Rate of Different Dielectric Material

10.0

5.0

NP0

0.0

-5.0

-10.0

-15.0

Capacitance Change Percent (%)

-20.0

-25.0

-30.0
1 10 100 1000 10000 100000

Time (Hours)

7R, X5R

Y5V

When heating the capacitors above Curie temperature (130℃~150℃) the capacitance can be re-new. So
capacitance of class 2 capacitors will be complete de-aged by soldering process; subsequently a new aging process
begins.
Because of aging, it is specified an age for measurement to meet the prescribed tolerance for class 2 capacitors.
Normally, 1000 hours (t2=1000 hrs) is defined.

Darfon Product Specification 9 Rev.: 3