Datasheet C161K, C161O Datasheet (Amphenol)

Data Sheet, V2.0, Jan. 2001

C161K C161O

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2001-01 Published by Infineon Technologies AG,

St.-Martin-Strasse 53, D-81541 München, Germany

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The information herein is given to describe certain components and shall not be considered as warranted characteristics.

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Data Sheet, V2.0, Jan. 2001

C161K C161O

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C161K/O

Revision History: 2001-01 V2.0

Previous Version: 03.97 (Preliminary)

09.96 (Advance Information)

Page Subjects (major changes since last revision)

All Converted to Infineon layout All C161V removed

2 Ordering Codes and Cross-Reference replaced with Derivative Synopsis 5 - 8 Open drain functionality described for P2, P3, P6 8 Bidirectional reset introduced 19 Figure updated 28, 29 Revised description of Absolute Max. Ratings and Operating Conditions 32 - 56 Specifications for reduced supply voltage introduced 35 Reduced power consumption 36, 37 Clock Generation Modes added 38, 39 Description of External Clock Drive improved 41 - 56 Standard 25-MHz timing introduced (timing granularity 2 ns)

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Data Sheet 1 V2.0, 2001-01

C161K

C161O

This document describes several derivatives of the C161 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product.

Table 1 C161K/O Derivative Synopsis Derivative

1)

Max. Oper. Frequency

Operating Voltage

IRAM [KB]

Nr of CS

SAF-C161K-LM 20 MHz 4.5 to 5.5 V124--SAB-C161K-LM 20 MHz 4.5 to 5.5 V 124--SAF-C161K-L25M 25 MHz 4.5 to 5.5 V124--SAB-C161K-L25M 25 MHz 4.5 to 5.5 V 124--SAF-C161K-LM3V 20 MHz 3.0 to 3.6 V124---

Ext.

s

Intr.

CAP IN

SAB-C161K-LM3V 20 MHz 3.0 to 3.6 V 124--SAF-C161O-LM 20 MHz 4.5 to 5.5 V247Yes SAB-C161O-LM 20 MHz 4.5 to 5.5 V 247Yes SAF-C161O-L25M 25 MHz 4.5 to 5.5 V247Yes SAB-C161O-L25M 25 MHz 4.5 to 5.5 V 247Yes SAF-C161O-LM3V 20 MHz 3.0 to 3.6 V247Yes SAB-C161O-LM3V 20 MHz 3.0 to 3.6 V 247Yes

1)

This Data Sheet is valid for devices starting with and including design step HA.

For simplicity all versions are referred to by the term C161K/O throughout this document.

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C161K/O please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet 2 V2.0, 2001-01

C161K

C161O

Data Sheet 3 V2.0, 2001-01

Pin Configuration MQFP Package

(top view)

C161K

C161O

V

XTAL1 XTAL2

V

P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD

P3.5/T4IN P3.6/T3IN

P3.7/T2IN P3.8/MRST P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19

SS

DD

P5.15/T2EUD

P5.14/T4EUD

80

79

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21

22

P2.14/EX6IN

P2.15/EX7IN

78

23

P2.12/EX4IN

P2.13/EX5IN

77

76

75

24

26

25

P2.11/EX3IN

74

P6.3/CS3

P2.9/EX1IN

P2.10/EX2IN

73

71

72

C161K/O

29

28

30

27

P6.0/CS0

P6.2/CS2

P6.1/CS1

70

68

69

33

31

32

NMI

RSTOUT

67

66

34

35

DD

RSTIN

65

646362

36

37

VSSV

P1H.7/A15

39

38

P1H.6/A14

61

60 P1H.5/A13 59 P1H.4/A12

P1H.3/A1158 P1H.2/A1057

56

P1H.1/A9 P1H.0/A855 P1L.7/A754

53

P1L.6/A6 P1L.5/A552 P1L.4/A451 P1L.3/A3

50

P1L.2/A249 P1L.1/A148

47

P1L.0/A0 P0H.7/AD1546 P0H.6/AD1445 P0H.5/AD13

44 43

P0H.4/AD12 P0H.3/AD1142 P0H.2/AD10

41

40

V

SS

DD

V

P4.4/A20

RD

P4.5/A21

WR/WRL

ALE

EA

P0L.0/AD0

P0L.1/AD1

P0L.2/AD2

P0L.3/AD3

P0L.4/AD4

P0L.5/AD5

P0L.6/AD6

SS

DD

V

P0L.7/AD7

P0H.0/AD8

P0H.1/AD9

MCP04858

Figure 2

Note: The marked signals are only available in the C161O.

Please also refer to the detailed description below (shaded lines).

Data Sheet 4 V2.0, 2001-01

Table 2 Pin Definitions and Functions

C161K

C161O

Symbol Pin

Num

XTAL1

XTAL223

P3 IO Port 3 is a 12-bit bidirectional I/O port. It is bit-wise

P3.2

P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12

P3.13

5 I CAPIN GPT2 Register CAPREL Capture Input

6

7

8

9

10

11

12

13

14

15

16

Input Outp.

I

O

O I I I I I/O I/O O I/O O O I/O

Function

XTAL1: Input to the oscillator amplifier and input

to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The Port 3 pins serve for following alternate functions:

This alternate input is only available in the C161O. T3OUT GPT1 Timer T3 Toggle Latch Output

T3EUD GPT1 Timer T3 External Up/Down Control Input T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp MRST SSC Master-Receive/Slave-Transmit Inp./Outp. MTSR SSC Master-Transmit/Slave-Receive Outp./Inp. TxD0 ASC0 Clock/Data Output (Async./Sync.) RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.) BHE WRH SCLK SSC Master Clock Output / Slave Clock Input

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe

P4

P4.0 P4.1 P4.2 P4.3 P4.4 P4.5

Data Sheet 5 V2.0, 2001-01

17 18 19 20 23 24

IO

O O O O O O

Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 4 can be used to output the segment address lines: A16 Least Significant Segment Address Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line A21 Most Significant Segment Address Line

Table 2 Pin Definitions and Functions (cont’d)

C161K

C161O

Symbol Pin

Num

RD 25 O External Memory Read Strobe. RD is activated for every

WR

/

WRL

ALE 27 O Address Latch Enable Output. Can be used for latching the

EA

PORT0

P0L.0-7

P0H.0-7

26 O External Memory Write Strobe. In WR-mode this pin is

28 I External Access Enable pin. A low level at this pin during and

29-36

39-46

Input Outp.

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L

Function

external instruction or data read access.

activated for every external data write access. In WRL this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.

address into external memory or an address latch in the multiplexed bus modes.

after Reset forces the C161K/O to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. “ROMless” versions must have this pin tied to ‘0’.

and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 – D7 P0H.0 – P0H.7: I/O D8 – D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 – AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15

-mode

PORT1

P1L.0-7

P1H.0-7

Data Sheet 6 V2.0, 2001-01

47-54

55-62

IO PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.

C161K

C161O

Data Sheet 7 V2.0, 2001-01

Table 2 Pin Definitions and Functions (cont’d)

C161K

C161O

Symbol Pin

Num

P2

P2.9 P2.10 P2.11 P2.12

72 73 74 75

76 77 78

P5

P5.14 P5.157980

Input Outp.

IO

I I I I

I I I

I

I I

Function

Port 2 is a 7-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The following Port 2 pins serve for alternate functions: EX1IN Fast External Interrupt 1 Input EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input EX4IN Fast External Interrupt 4 Input

EX5IN Fast External Interrupt 5 Input EX6IN Fast External Interrupt 6 Input EX7IN Fast External Interrupt 7 Input These external interrupts are only available in the C161O.

Port 5 is a 2-bit input-only port with Schmitt-Trigger char. The pins of Port 5 also serve as timer inputs: T4EUD GPT1 Timer T4 External Up/Down Control Input T2EUD GPT1 Timer T2 External Up/Down Control Input

V

DD

4, 22, 37, 64

– Digital Supply Voltage:

+ 5 V or + 3 V during normal operation and idle mode.

≥ 2.5 V during power down mode.

V

SS

1, 21,

– Digital Ground.

38, 63

Note: The following behavioral differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap

loader may be activated when P0L.4 is low.

• Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 8 V2.0, 2001-01

C161K

C161O

Functional Description

The architecture of the C161K/O combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161K/O.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

8

ProgMem

Internal

ROM

Area

Port 4

XBUS Control

External Bus

Control

Port 6

Port 0

16

EBC

Instr. / Data

x) u

m e

it D

-B 6

(1 S U B

X ip h

-C n O

16

Port 1

32

16

External Instr. / Data

Interrupt Controller

ASC0

(USART)

BRGen

C166-Core

CPU

SSC

(SPI)

BRGen

15

PEC

16-Level

Priority

GPT1

T2 T3 T4

Interrupt Bus

Peripheral Data Bus

GPT2

T5 T6

Data

16

IRAM

Internal

Dual Port

1/2 Kbyte

Osc

RAM

XTAL

WDT

8

Port 2

Port 5Port 3

6

MCB04323_1ko

Figure 3 Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourth bus, the XBUS, connects external resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).

Data Sheet 9 V2.0, 2001-01

C161K

C161O

Memory Organization

The memory space of the C161K/O is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.

The C161K/O is prepared to incorporate on-chip program memory (not in the ROM-less derivatives, of course) for code or constant data. The internal ROM area can be mapped either to segment 0 or segment 1.

On-chip Internal RAM (IRAM) is provided (1 KByte in the C161K, 2 KBytes in the C161O) as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family.

In order to meet the needs of designs where more memory is required than is provided on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller.

× 512 bytes) of the address space are reserved for the Special Function

Data Sheet 10 V2.0, 2001-01

C161K

C161O

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows:

– 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed – 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed – 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed – 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/ output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which control the access to different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 2 or 4 external CS signals (1 or 3 windows plus default, depending on the device) can be generated in order to save external glue logic. The C161K/O offers the possibility to switch the CS switched off and the CS

mode is enabled by setting CSCFG (SYSCON.6).

CS For applications which require less than 4 MBytes of external memory space, this

address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an address space of 4 MBytes is used.

outputs to an unlatched mode. In this mode the internal filter logic is

signals are directly generated from the address. The unlatched

Data Sheet 11 V2.0, 2001-01

C161K

C161O

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C161K/O’s instructions can be executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

× 16

ROM

32

CPU

SP STKOV STKUN

Exec. Unit

Instr. Ptr.

Instr. Reg.

4-Stage

Pipeline

PSW

SYSCON

BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 4

Data Page Ptr. Code Seg. Ptr.

MDH MDL

Mul/Div-HW

Bit-Mask Gen

ALU

(16-bit)

Barrel - Shifter

Context Ptr.

ADDRSEL 1 ADDRSEL 2 ADDRSEL 3

R15

General

Purpose

Registers

R0

16

Internal

RAM

R15

R0

16

MCB02147

Figure 4 CPU Block Diagram

Data Sheet 12 V2.0, 2001-01

C161K

C161O

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C161K/O instruction set which includes the following instruction classes:

– Arithmetic Instructions – Logical Instructions – Boolean Bit Manipulation Instructions – Compare and Loop Control Instructions – Shift and Rotate Instructions – Prioritize Instruction – Data Movement Instructions – System Stack Instructions – Jump and Call Instructions – Return Instructions – System Control Instructions – Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

Data Sheet 13 V2.0, 2001-01

C161K

C161O

Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C161K/O is capable of reacting very fast to the occurrence of non-deterministic events.

The architecture of the C161K/O supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C161K/O has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.

Table 3 shows all of the possible C161K/O interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).

Data Sheet 14 V2.0, 2001-01

Table 3 C161K/O Interrupt Nodes

C161K

C161O

Source of Interrupt or PEC Service Request

Request Flag

Enable Flag

Interrupt Vector

Vector Location

External Interrupt 1 CC9IR CC9IE CC9INT 00’0064 External Interrupt 2 CC10IR CC10IE CC10INT 00’0068 External Interrupt 3 CC11IR CC11IE CC11INT 00’006C External Interrupt 4 CC12IR CC12IE CC12INT 00’0070 External Interrupt 5 CC13IR CC13IE CC13INT 00’0074 External Interrupt 6 CC14IR CC14IE CC14INT 00’0078 External Interrupt 7 CC15IR CC15IE CC15INT 00’007C GPT1 Timer 2 T2IR T2IE T2INT 00’0088 GPT1 Timer 3 T3IR T3IE T3INT 00’008C GPT1 Timer 4 T4IR T4IE T4INT 00’0090 GPT2 Timer 5 T5IR T5IE T5INT 00’0094 GPT2 Timer 6 T6IR T6IE T6INT 00’0098 GPT2 CAPREL Reg. CRIR CRIE CRINT 00’009C

H

Trap Number

19

H

1A

H

1B

H

1C

H

1D

H

1E

H

1F

H

22

H

23

H

24

H

25

H

26

H

27

H

ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8 ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C ASC0 Receive S0RIR S0RIE S0RINT 00’00AC ASC0 Error S0EIR S0EIE S0EINT 00’00B0 SSC Transmit SCTIR SCTIE SCTINT 00’00B4 SSC Receive SCRIR SCRIE SCRINT 00’00B8 SSC Error SCEIR SCEIE SCEINT 00’00BC

2A

H

47 2B 2C 2D 2E 2F

H

Note: The shaded interrupt nodes are only available in the C161O, not in the C161K.

Data Sheet 15 V2.0, 2001-01

C161K

C161O

The C161K/O also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4 Hardware Trap Summary Exception Condition Trap

Flag

Reset Functions:

–

– Hardware Reset – Software Reset – W-dog Timer Overflow

Class A Hardware Traps:

– Non-Maskable Interrupt – Stack Overflow – Stack Underflow

NMI STKOF STKUF

Class B Hardware Traps:

– Undefined Opcode – Protected Instruction

UNDOPC PRTFLT

Fault

– Illegal Word Operand

ILLOPA

Access

– Illegal Instruction

ILLINA

Access

– Illegal External Bus

ILLBUS

Access

Trap Vector

RESET RESET RESET

NMITRAP STOTRAP STUTRAP

BTRAP BTRAP

BTRAP

Vector Location

00’0000 00’0000 00’0000

00’0008 00’0010 00’0018

00’0028 00’0028

00’0028

H H H

H H

H

Trap Number

00

H

00

H

00

H

02

H

04

H

06

H

0A

H

0A

H

0A

H

0A

H

0A

H

Trap Priority

III III III

II II II

I I

I

Reserved –– [2C

Software Traps

–– Any

– TRAP Instruction

–

H

3C

]

H

[00’0000 00’01FC

–

[0B

H

0F

]

H

Any

–

H

]

H

[00 7F

–

H

]

H

–

Current CPU

Priority in steps of 4

H

Data Sheet 16 V2.0, 2001-01

C161K

C161O

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.

Data Sheet 17 V2.0, 2001-01

C161K

C161O

T2EUD

T2IN

T3IN

T3EUD

T4IN

CPU

U/D

2n : 1f

T2

Mode

Control

T3

Mode

Control

T4

Mode

Control

GPT1 Timer T2

Reload Capture

Toggle FF

GPT1 Timer T3 T3OTL

U/D

Capture Reload

GPT1 Timer T4

Interrupt Request

T3OUT

Other Timers

Interrupt Request

T4EUD

U/D

MCT02141

n = 3 … 10

Figure 5 Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows the C161K/O to measure absolute time differences or to perform pulse multiplication without software overhead.

Data Sheet 18 V2.0, 2001-01

C161K

C161O

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.

Note: Block GPT2 is only available in the C161O, not in the C161K.

f

CPU

CAPIN

f

CPU

2n : 1

T3

2n : 1

T5

Mode

Control

MUX

CT3

T6

Mode

Control

Clear

Capture

U/D

GPT2 Timer T5

GPT2 CAPREL

GPT2 Timer T6

U/D

T6OTL

Interrupt Request

T6OUT

Other Timers

MCB02938

n = 2 … 9

Figure 6 Block Diagram of GPT2

Data Sheet 19 V2.0, 2001-01

C161K

C161O

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 781 kBaud and half-duplex synchronous communication at up to 3.1 MBaud (@ 25 MHz CPU clock). A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 6.25 MBaud (@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception, and error handling three separate interrupt vectors are provided. The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data.

Data Sheet 20 V2.0, 2001-01

C161K

C161O

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 20 (@ 25 MHz). The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).

µs and 336 ms can be monitored

Parallel Ports

The C161K/O provides up to 63 I/O lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A21/19/17 … A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional chip select signals. Port 3 includes alternate functions of timers, serial interfaces, and the optional bus control signal BHE Port 5 is used for timer control signals.

/WRH.

Data Sheet 21 V2.0, 2001-01

C161K

C161O

Instruction Set Summary

Table 5 lists the instructions of the C161K/O in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailed description of each instruction.

Table 5 Instruction Set Summary Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2 / 4 OR(B) Bitwise OR, (word/byte operands) 2 / 4 XOR(B) Bitwise XOR, (word/byte operands) 2 / 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR,

AND/OR/XOR direct bit with direct bit 4

BXOR BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable

4

direct word memory with immediate data CMP(B) Compare word (byte) operands 2 / 4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4 PRIOR Determine number of shift cycles to normalize direct

2

word GPR and store result in direct word GPR SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2

Data Sheet 22 V2.0, 2001-01

C161K

C161O

Table 5 Instruction Set Summary (cont’d) Mnemonic Description Bytes

MOV(B) Move word (byte) data 2 / 4 MOVBS Move byte operand to word operand with sign extension 2 / 4 MOVBZ Move byte operand to word operand. with zero extension 2 / 4 JMPA, JMPI,

JMPR JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI,

CALLR CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call

TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update

RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2

Jump absolute/indirect/relative if condition is met 4

Call absolute/indirect/relative subroutine if condition is met 4

absolute subroutine

register with word operand

4

RETP Return from intra-segment subroutine and pop direct

word register from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4 EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4 NOP Null operation 2

Data Sheet 23 V2.0, 2001-01

-pin being low) 4

2

C161K

C161O

Special Function Registers Overview

The following table lists all SFRs which are implemented in the C161K/O in alphabetical order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical

Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Note: The shaded registers are only available in the C161O, not in the C161K.

Table 6 C161K/O Registers, Ordered by Name Name Physical

Address ADDRSEL1 FE18 ADDRSEL2 FE1A ADDRSEL3 FE1C ADDRSEL4 FE1E BUSCON0 b FF0C BUSCON1 b FF14 BUSCON2 b FF16 BUSCON3 b FF18 BUSCON4 b FF1A CAPREL FE4A CC10IC b FF8C CC11IC b FF8E CC12IC b FF90

H

8-Bit Addr.

0C

H

0D

H

0E

H

0F

H

86

H

8A

H

8B

H

8C

H

8D

H

25

H

C6

H

C7

H

C8

H

Description Reset

Value

Address Select Register 1 0000 Address Select Register 2 0000 Address Select Register 3 0000 Address Select Register 4 0000 Bus Configuration Register 0 0XX0 Bus Configuration Register 1 0000 Bus Configuration Register 2 0000 Bus Configuration Register 3 0000 Bus Configuration Register 4 0000 GPT2 Capture/Reload Register 0000 EX2IN Interrupt Control Register 0000 EX3IN Interrupt Control Register 0000 EX4IN Interrupt Control Register 0000

H

CC13IC b FF92 CC14IC b FF94 CC15IC b FF96 CC9IC b FF8A CP FE10 CRIC b FF6A CSP FE08

Data Sheet 24 V2.0, 2001-01

H

C9 CA CB C5 08 B5 04

EX5IN Interrupt Control Register 0000

H

EX6IN Interrupt Control Register 0000

H

EX7IN Interrupt Control Register 0000

H

EX1IN Interrupt Control Register 0000

H

CPU Context Pointer Register FC00

H

GPT2 CAPREL Interrupt Ctrl. Reg. 0000

H

CPU Code Seg. Pointer Reg. (read only) 0000

H

Table 6 C161K/O Registers, Ordered by Name (cont’d)

C161K

C161O

Name Physical

Address DP0H b F102 DP0L b F100 DP1H b F106 DP1L b F104 DP2 b FFC2 DP3 b FFC6 DP4 b FFCA DP6 b FFCE DPP0 FE00 DPP1 FE02 DPP2 FE04 DPP3 FE06 EXICON b F1C0

H

8-Bit

Addr. E 81 E 80 E 83 E 82

E1

E3

E5

E7

00

01

02

03

E E0

Description Reset

P0H Direction Control Register 00

H

P0L Direction Control Register 00

H

P1H Direction Control Register 00

H

P1L Direction Control Register 00

H

Port 2 Direction Control Register 0000

H

Port 3 Direction Control Register 0000

H

Port 4 Direction Control Register 00

H

Port 6 Direction Control Register 00

H

CPU Data Page Pointer 0 Reg. (10 bits) 0000

H

CPU Data Page Pointer 1 Reg. (10 bits) 0001

H

CPU Data Page Pointer 2 Reg. (10 bits) 0002

H

CPU Data Page Pointer 3 Reg. (10 bits) 0003

H

External Interrupt Control Register 0000

H

Value

H

IDCHIP F07C IDMANUF F07E IDMEM F07A IDMEM2 F076 IDPROG F078 MDC b FF0E MDH FE0C MDL FE0E ODP2 b F1C2 ODP3 b F1C6

H

E 3E E 3F E 3D E 3B E 3C

87

06

07

E E1 E E3

ODP6 b F1CEHE E7 ONES b FF1E P0H b FF02 P0L b FF00 P1H b FF06

H

8F

81

80

83

Identifier 05XX

H

Identifier 1820

H

Identifier 0000

H

Identifier 0000

H

Identifier 0000

H

CPU Multiply Divide Control Register 0000

H

CPU Multiply Divide Reg. – High Word 0000

H

CPU Multiply Divide Reg. – Low Word 0000

H

Port 2 Open Drain Control Register 0000

H

Port 3 Open Drain Control Register 0000

H

Port 6 Open Drain Control Register 00

H

Constant Value 1’s Register (read only) FFFF

H

Port 0 High Reg. (Upper half of PORT0) 00

H

Port 0 Low Reg. (Lower half of PORT0) 00

H

Port 1 High Reg. (Upper half of PORT1) 00

H

P1L b FF04 P2 b FFC0

Data Sheet 25 V2.0, 2001-01

H

82

E0

Port 1 Low Reg.(Lower half of PORT1) 00

H

Port 2 Register 0000

H

Table 6 C161K/O Registers, Ordered by Name (cont’d)

C161K

C161O

Name Physical

Address P3 b FFC4 P4 b FFC8 P5 b FFA2 P6 b FFCC PECC0 FEC0 PECC1 FEC2 PECC2 FEC4 PECC3 FEC6 PECC4 FEC8 PECC5 FECA PECC6 FECC PECC7 FECE PSW b FF10

H

8-Bit Addr.

E2

H

E4

H

D1

H

E6

H

60

H

61

H

62

H

63

H

64

H

65

H

66

H

67

H

88

H

Description Reset

Value

Port 3 Register 0000 Port 4 Register (8 bits) 00 Port 5 Register (read only) XXXX Port 6 Register (8 bits) 00 PEC Channel 0 Control Register 0000 PEC Channel 1 Control Register 0000 PEC Channel 2 Control Register 0000 PEC Channel 3 Control Register 0000 PEC Channel 4 Control Register 0000 PEC Channel 5 Control Register 0000 PEC Channel 6 Control Register 0000 PEC Channel 7 Control Register 0000 CPU Program Status Word 0000

H

RP0H b F108 S0BG FEB4

S0CON b FFB0 S0EIC b FF70 S0RBUF FEB2

S0RIC b FF6E

S0TBIC b F19C

S0TBUF FEB0

S0TIC b FF6C

SP FE12

H

E 84

5A

D8 B8 59

B7

E CE

58

B6

09

System Startup Config. Reg. (Rd. only) XX

H

Serial Channel 0 Baud Rate Generator

H

Reload Register Serial Channel 0 Control Register 0000

H

Serial Channel 0 Error Interrupt Ctrl. Reg 0000

H

Serial Channel 0 Receive Buffer Reg.

H

(read only) Serial Channel 0 Receive Interrupt

H

Control Register Serial Channel 0 Transmit Buffer

H

Interrupt Control Register Serial Channel 0 Transmit Buffer

H

Register (write only) Serial Channel 0 Transmit Interrupt

H

Control Register CPU System Stack Pointer Register FC00

H

0000

XX

0000

00

0000

H

SSCBR F0B4 SSCCON b FFB2

Data Sheet 26 V2.0, 2001-01

H

E 5A

D9

SSC Baudrate Register 0000

H

SSC Control Register 0000

H

Table 6 C161K/O Registers, Ordered by Name (cont’d)

C161K

C161O

Name Physical

Address SSCEIC b FF76 SSCRB F0B2 SSCRIC b FF74 SSCTB F0B0 SSCTIC b FF72 STKOV FE14 STKUN FE16 SYSCON b FF12 T2 FE40 T2CON b FF40 T2IC b FF60 T3 FE42 T3CON b FF42

H

8-Bit Addr.

BB

E 59

BA

E 58

B9 0A 0B 89 20 A0 B0 21 A1

Description Reset

SSC Error Interrupt Control Register 0000

H

SSC Receive Buffer XXXX

H

SSC Receive Interrupt Control Register 0000

H

SSC Transmit Buffer 0000

H

SSC Transmit Interrupt Control Register 0000

H

CPU Stack Overflow Pointer Register FA00

H

CPU Stack Underflow Pointer Register FC00

H

CPU System Configuration Register

H

GPT1 Timer 2 Register 0000

H

GPT1 Timer 2 Control Register 0000

H

GPT1 Timer 2 Interrupt Control Register 0000

H

GPT1 Timer 3 Register 0000

H

GPT1 Timer 3 Control Register 0000

H

Value

1)

0XX0

H

T3IC b FF62 T4 FE44 T4CON b FF44 T4IC b FF64 T5 FE46 T5CON b FF46 T5IC b FF66 T6 FE48 T6CON b FF48 T6IC b FF68 TFR b FFAC WDT FEAE WDTCON b FFAE ZEROS b FF1C

1)

The system configuration is selected during reset.

2)

The reset value depends on the indicated reset source.

H

B1 22 A2 B2 23 A3 B3 24 A4 B4 D6 57 D7 8E

GPT1 Timer 3 Interrupt Control Register 0000

H

GPT1 Timer 4 Register 0000

H

GPT1 Timer 4 Control Register 0000

H

GPT1 Timer 4 Interrupt Control Register 0000

H

GPT2 Timer 5 Register 0000

H

GPT2 Timer 5 Control Register 0000

H

GPT2 Timer 5 Interrupt Control Register 0000

H

GPT2 Timer 6 Register 0000

H

GPT2 Timer 6 Control Register 0000

H

GPT2 Timer 6 Interrupt Control Register 0000

H

Trap Flag Register 0000

H

Watchdog Timer Register (read only) 0000

H

Watchdog Timer Control Register

H

Constant Value 0’s Register (read only) 0000

H

2)

00XX

H

Data Sheet 27 V2.0, 2001-01

Absolute Maximum Ratings

Table 7 Absolute Maximum Rating Parameters Parameter Symbol Limit Values Unit Notes

min. max.

C161K

C161O

Storage temperature Junction temperature

V

Voltage on respect to ground (

pins with

DD

V

SS

)

Voltage on any pin with respect to ground (

V

SS

)

Input current on any pin

T

ST

T

J

V

DD

V

IN

– -10 10 mA –

-65 150 °C –

-40 150 °C under bias

-0.5 6.5 V –

-0.5 VDD+0.5 V –

during overload condition Absolute sum of all input

–– |100| mA – currents during overload condition

Power dissipation

P

DISS

– 1.5 W –

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions ( voltage on

V

pins with respect to ground (VSS) must not exceed the values

DD

V

> VDD or VIN < VSS) the

IN

defined by the absolute maximum ratings.

Data Sheet 28 V2.0, 2001-01

C161K

C161O

Data Sheet 29 V2.0, 2001-01

C161K

C161O

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C161K/ O and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics): The logic of the C161K/O will provide signals with the respective timing characteristics.

SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C161K/O.

DC Characteristics (Standard Supply Voltage Range)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

1)

Input low voltage (TTL, all except XTAL1)

Input low voltage XTAL1 Input high voltage (TTL,

all except RSTIN

and XTAL1)

Input high voltage RSTIN (when operated as input)

Input high voltage XTAL1

Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, RSTOUT, RSTIN

2)

)

Output low voltage (all other outputs)

Output high voltage

3)

(PORT0, PORT1, Port 4, ALE,

, WR, BHE, RSTOUT)

RD Output high voltage

3)

(all other outputs)

min. max.

V

SR -0.5 0.2 V

IL

DD

V –

- 0.1

V V

V

SR -0.5 0.3 V

IL2

SR 0.2 V

IH

+ 0.9

SR 0.6 V

IH1

V

DD

0.5

DDVDD

+

DD

V – V –

V –

0.5

V

SR 0.7 V

IH2

DDVDD

+

V –

0.5

V

CC – 0.45 V IOL = 2.4 mA

OL

V

CC – 0.45 V IOL = 1.6 mA

OL1

V

CC 2.4 – V IOH = -2.4 mA

OH

V

0.9

V

CC 2.4 – V IOH = -1.6 mA

OH1

0.9

– V IOH = -0.5 mA

DD

V

– V IOH = -0.5 mA

DD

I

Input leakage current (Port 5) Input leakage current (all other) I RSTIN inactive current

Data Sheet 30 V2.0, 2001-01

4)

CC – ±200 nA 0 V < V

OZ1

CC – ±500 nA 0.45 V < V

OZ2

RSTH

5)

– -10 µA V

I

IN

= V

IN

IH1

< V

IN

DD

< V

DD

C161K

C161O

DC Characteristics (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

RSTIN active current RD/WR inact. current

/WR active current

RD ALE inactive current ALE active current Port 6 inactive current Port 6 active current

4)

7)

PORT0 configuration current

1)

7)

I

RSTL

I

RWH

I

RWL

I

ALEL

I

ALEH

I

P6H

I

P6L

I

P0H

I

P0L

6)

5)

6)

min. max.

6)

-100 – µA V

5)

– -40 µA V

-500 – µA V

5)

– 40 µA V

6)

500 – µA V – -40 µA V

-500 – µA V – -10 µA V

-100 – µA V

= V

IN

OUT

= V

IN

= V

IN

IL

= 2.4 V = V

OLmax

= V

OLmax

= 2.4 V = 2.4 V = V

OL1max

IHmin

ILmax

XTAL1 input current I Pin capacitance

8)

(digital inputs/outputs)

1)

Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. For signal levels outside these specifications also refer to the specification of the overload current

2)

Valid in bidirectional reset mode only.

3)

This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry.

4)

These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.

5)

The maximum current may be drawn while the respective signal line remains inactive.

6)

The minimum current must be drawn in order to drive the respective signal line active.

7)

This specification is valid during Reset and during Adapt-mode.

8)

Not 100% tested, guaranteed by design and characterization.

CC – ±20 µA0 V < V

IL

C

CC – 10 pF f = 1 MHz

IO

T

= 25 °C

A

IN

< V

I

OV

DD

.

Data Sheet 31 V2.0, 2001-01

C161K

C161O

DC Characteristics (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

1)

min. max.

Input low voltage (TTL, all except XTAL1)

Input low voltage XTAL1 Input high voltage (TTL,

all except RSTIN

and XTAL1)

Input high voltage RSTIN (when operated as input)

Input high voltage XTAL1

Output low voltage (PORT0, PORT1, Port 4, ALE, RD

, WR, BHE, RSTOUT,

RSTIN

2)

)

Output low voltage (all other outputs)

Output high voltage

3)

(PORT0, PORT1, Port 4, ALE,

, WR, BHE, RSTOUT)

RD Output high voltage

3)

(all other outputs)

V

V V

V

SR -0.5 0.8 V –

IL

SR -0.5 0.3 V

IL2

SR 1.8 VDD +

IH

DD

V – V –

0.5

SR 0.6 V

IH1

DDVDD

+

V –

0.5

SR 0.7 V

IH2

DDVDD

+

V –

0.5

CC – 0.45 V IOL = 1.6 mA

OL

CC – 0.45 V IOL = 1.0 mA

OL1

CC 0.9 V

OH

CC 0.9 V

OH1

– V IOH = -0.5 mA

DD

– V IOH = -0.25 mA

DD

Input leakage current (Port 5) Input leakage current (all other) I RSTIN inactive current RSTIN active current RD/WR inact. current

/WR active current

RD ALE inactive current ALE active current Port 6 inactive current Port 6 active current

Data Sheet 32 V2.0, 2001-01

4)

7)

I

OZ1

OZ2

I

RSTH

I

RSTL

I

RWH

I

RWL

I

ALEL

I

ALEH

I

P6H

I

P6L

CC – ±200 nA 0 V < V CC – ±500 nA 0.45 V < V

5)

6)

5)

6)

– -10 µA V

6)

-100 – µA V

5)

– -10 µA V

-500 – µA V

5)

– 20 µA V

6)

500 – µA V – -10 µA V

-500 – µA V

= V

IN

= V

IN

OUT

= 2.4 V = V = V = 2.4 V = 2.4 V = V

< V

IN

IH1

IL

OLmax

OL1max

DD

< V

DD

C161K

C161O

DC Characteristics (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

PORT0 configuration current

1)

7)

I

P0H

I

P0L

6)

5)

min. max.

– -5 µA V

-100 – µA V

IN

= V = V

IHmin

ILmax

XTAL1 input current I Pin capacitance

8)

C

(digital inputs/outputs)

1)

Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. For signal levels outside these specifications also refer to the specification of the overload current

2)

Valid in bidirectional reset mode only.

3)

This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry.

4)

These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.

5)

The maximum current may be drawn while the respective signal line remains inactive.

6)

The minimum current must be drawn in order to drive the respective signal line active.

7)

This specification is valid during Reset and during Adapt-mode.

8)

Not 100% tested, guaranteed by design and characterization.

CC – ±20 µA0 V < V

IL

CC – 10 pF f = 1 MHz

IO

T

= 25 °C

A

IN

< V

I

OV

DD

.

Data Sheet 33 V2.0, 2001-01

C161K

C161O

Power Consumption C161K/O (Standard Supply Voltage Range)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

min. max.

Power supply current (active) with all peripherals active

Idle mode supply current with all peripherals active

Power-down mode supply

I

DD5

I

IDX5

I

PDO5

– 15 +

1.8

– 2 +

0.4

× f

CPU

mA RSTIN = V

f

mA RSTIN = V

f

– 50 µA V

CPU

DD

= V

IL

in [MHz]

IH1

in [MHz]

DDmax

1)

2)

current

1)

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 7. These parameters are tested at

V

or VIH.

at

IL

2)

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at

V

- 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.

DD

V

and maximum CPU clock with all outputs disconnected and all inputs

DDmax

Power Consumption C161K/O (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

min. max.

Power supply current (active) with all peripherals active

I

DD3

– 3 +

1.3

× f

CPU

mA RSTIN = V

f

in [MHz]

CPU

IL

1)

Idle mode supply current with all peripherals active

Power-down mode supply

I

IDX3

I

PDO3

– 1 +

0.4

× f

CPU

mA RSTIN = V

f

– 30 µA V

CPU

DD

= V

IH1

in [MHz]

DDmax

1)

2)

current

1)

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 7. These parameters are tested at

V

or VIH.

at

IL

2)

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

V

0.1 V or at

- 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.

DD

V

Data Sheet 34 V2.0, 2001-01

and maximum CPU clock with all outputs disconnected and all inputs

DDmax

C161K

C161O

I

mA

I

100

80

60

DD5max

I

DD5typ

I

DD3max

I

DD3typ

40

I

20

IDX5max

I

IDX3max

I

IDX5typ

I

IDX3typ

0

10 20 30 400

MHz

f

CPU

MCD04860

Figure 7 Supply/Idle Current as a Function of Operating Frequency

Data Sheet 35 V2.0, 2001-01

AC Characteristics Definition of Internal Timing

C161K

C161O

The internal operation of the C161K/O is controlled by the internal CPU clock

f

CPU

. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Figure 8).

Direct Clock Drive

f

OSC

TCL

f

CPU

TCL

Prescaler Operation

f

OSC

TCL

f

CPU

TCL

MCT04826

Figure 8 Generation Mechanisms for the CPU Clock

The CPU clock signal

f

can be generated from the oscillator clock signal f

CPU

OSC

via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate

f

. This influence must

CPU

be regarded when calculating the timings for the C161K/O. The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG

in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins P0.15-13 (P0H.7-5).

Table 9 associates the combinations of these three bits with the respective clock

generation mode.

Data Sheet 36 V2.0, 2001-01

Table 9 C161K/O Clock Generation Modes

C161K

C161O

CLKCFG (P0H.7-5)

0XX 1XX f

1)

The maximum frequency depends on the duty cycle of the external clock signal.

CPU Frequency

f

= f

CPU

f

× 1 1 to 25 MHz Direct drive

OSC

/ 2 2 to 50 MHz CPU clock via prescaler

OSC

× F

External Clock Input Range

Notes

1)

Prescaler Operation

When prescaler operation is configured (CLKCFG = 1XX

) the CPU clock is derived

B

from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of the duration of an individual TCL) is defined by the period of the input clock

f

is half the frequency of f

CPU

and the high and low time of f

OSC

f

OSC

CPU

.

(i.e.

The timings listed in the AC Characteristics that refer to TCLs therefore can be

f

calculated using the period of

for any TCL.

OSC

Direct Drive

When direct drive is configured (CLKCFG = 0XX

) the CPU clock is directly driven from

B

the internal oscillator with the input clock signal. The frequency of

f

(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

CPU

f

.

OSC

f

directly follows the frequency of f

CPU

so the high and low time of

OSC

The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula:

TCL

For two consecutive TCLs the deviation caused by the duty cycle of so the duration of 2TCL is always 1/

min

= 1/f

OSC

× DC

min

(DC = duty cycle)

f

. The minimum value TCL

OSC

f

is compensated

OSC

therefore has to

min

be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/

Data Sheet 37 V2.0, 2001-01

f

OSC

.

AC Characteristics

Table 10 External Clock Drive XTAL1 (Standard Supply Voltage Range)

(Operating Conditions apply)

C161K

C161O

Parameter Symbol Direct Drive

1:1

Prescaler

2:1

min. max. min. max.

Oscillator period High time Low time Rise time Fall time

1)

The clock input signal must reach the defined levels V

2)

The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f direct drive mode depends on the duty cycle of the clock input signal.

1)

t

OSC

t

1

t

2

t

3

t

4

SR 40 – 20 – ns SR 20 SR 20

2)

– 6 – ns – 6 – ns

SR – 10 – 6ns SR – 10 – 6ns

IL2

and V

IH2

.

Table 11 External Clock Drive XTAL1 (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter Symbol Direct Drive

1:1

Prescaler

2:1

Unit

CPU

Unit

) in

min. max. min. max.

Oscillator period High time Low time Rise time Fall time

1)

The clock input signal must reach the defined levels V

2)

The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f direct drive mode depends on the duty cycle of the clock input signal.

1)

t

OSC

t

1

t

2

t

3

t

4

SR 50 – 25 – ns SR 25 SR 25

2)

– 8 – ns – 8 – ns

SR – 10 – 6ns SR – 10 – 6ns

IL2

and V

IH2

.

CPU

) in

Data Sheet 38 V2.0, 2001-01

C161K

C161O

Data Sheet 39 V2.0, 2001-01

Testing Waveforms

C161K

C161O

2.4 V

1.8 V

0.8 V

0.45 V

AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’.

V

Timing measurements are made at

min for a logic 1’ and

IH

Figure 10 Input Output Waveforms

+ 0.1 V

V

Load

V

- 0.1 V

Load

Test Points

’ ’’

Timing

Reference

Points

1.8 V

0.8 V

V

max for a logic 0’.

IL

V

OH

V

OL

’

MCA04414

- 0.1 V

+ 0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,

V

/

V

but begins to float when a 100 mV change from the loaded

OH

level occurs (

OL

I

/ = 20 mA).

OH OL

MCA00763

Figure 11 Float Waveforms

Data Sheet 40 V2.0, 2001-01

C161K

C161O

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed.

Table 12 Memory Cycle Variables Description Symbol Values

ALE Extension Memory Cycle Time Waitstates Memory Tristate Time

t

A

t

C

t

F

TCL × <ALECTL> 2TCL × (15 - <MCTC>) 2TCL × (1 - <MTTC>)

Note: Please respect the maximum operating frequency of the respective derivative.

AC Characteristics

Multiplexed Bus (Standard Supply Voltage Range)

(Operating Conditions apply) ALE cycle time = 6 TCL + 2

Parameter Symbol Max. CPU Clock

t

+ tC + tF (120 ns at 25 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 25 MHz

1 / 2TCL = 1 to 25 MHz

Unit

min. max. min. max.

ALE high time

Address setup to ALE

t

CC 10 + t

5

t

CC 4 + t

6

– TCL - 10

A

t

+

A

– TCL - 16

+

t

A

– ns

Address hold after ALE

ALE falling edge to RD WR

(with RW-delay)

ALE falling edge to RD

(no RW-delay)

WR Address float after RD

WR

(with RW-delay)

Address float after RD

(no RW-delay)

WR

, WR low time

RD (with RW-delay)

Data Sheet 41 V2.0, 2001-01

t

CC 10 + t

7

,

t

CC 10 + t

8

,

t

CC -10 + tA– -10 + t

9

,

t

CC – 6 – 6ns

10

,

t

CC – 26 – TCL + 6 ns

11

t

CC 30 + t

12

– TCL - 10

A

+

– TCL - 10

A

+

– 2TCL - 10

C

+

– ns

t

A

– ns

t

A

– ns

t

C

Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply)

t

ALE cycle time = 6 TCL + 2

+ tC + tF (120 ns at 25 MHz CPU clock without waitstates)

A

C161K

C161O

Parameter Symbol Max. CPU Clock

= 25 MHz

min. max. min. max.

RD, WR low time

t

CC 50 + t

13

– 3TCL - 10

C

(no RW-delay)

t

RD to valid data in

SR – 20 + t

14

C

(with RW-delay)

to valid data in

RD

t

SR – 40 + t

15

C

(no RW-delay) ALE low to valid data in

Address to valid data in

Data hold after RD

t

SR – 40 + t

16

+ t

t

SR – 50 + 2t

17

+ t

t

SR 0 – 0 – ns

18

A

C

rising edge

t

Data float after RD

SR – 26 + t

19

F

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

– ns

+

t

C

– 2TCL - 20

+

t

C

– 3TCL - 20

+

t

C

– 3TCL - 20

+

t

A

– 4TCL - 30

A

+

2t

– 2TCL - 14

+

t

F

+ t

A

Unit

ns

C

ns

C

ns

Data valid to WR

Data hold after WR

ALE rising edge after RD WR

Address hold after RD

,

WR ALE falling edge to CS

low to Valid Data In

CS

hold after RD, WR

1)

ALE fall. edge to RdCS WrCS

(with RW delay)

ALE fall. edge to RdCS WrCS

(no RW delay)

1)

,

t

CC 20 + t

22

t

CC 26 + t

23

,

t

CC 26 + t

25

t

CC 26 + t

27

t

CC -4 - t

38

t

SR – 40 + t

39

t

CC 46 + t

40

t

CC 16 + t

42

t

CC -4 + t

43

– 2TCL - 20

C

– 2TCL - 14

F

– 2TCL - 14

F

– 2TCL - 14

F

10 - t

A

F

A

C

+ 2t

A

– 3TCL - 14

– TCL - 4

– -4

– ns

t

+

C

– ns

+

t

F

– ns

t

+

F

– ns

+

t

F

-4 - t

A

10 - t

A

– 3TCL - 20

t

+ 2t

+

C

A

– ns

t

+

F

– ns

+

t

A

– ns

t

+

A

ns ns

Data Sheet 42 V2.0, 2001-01

Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2

t

+ tC + tF (120 ns at 25 MHz CPU clock without waitstates)

A

C161K

C161O

Parameter Symbol Max. CPU Clock

= 25 MHz

min. max. min. max.

Address float after RdCS, WrCS

(with RW delay)

Address float after RdCS, WrCS

RdCS

(no RW delay) to Valid Data In

t

CC – 0 – 0ns

44

t

CC – 20 – TCL ns

45

t

SR – 16 + t

46

C

(with RW delay) RdCS

to Valid Data In

t

SR – 36 + t

47

C

(no RW delay) RdCS

, WrCS Low Time

t

CC 30 + t

48

– 2TCL - 10

C

(with RW delay) RdCS

, WrCS Low Time

t

CC 50 + t

49

– 3TCL - 10

C

(no RW delay)

t

Data valid to WrCS

CC 26 + t

50

– 2TCL - 14

C

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

– 2TCL - 24

+

t

C

– 3TCL - 24

+

t

C

– ns

+

t

C

– ns

t

+

C

– ns

+

t

C

Unit

ns

Data hold after RdCS Data float after RdCS

Address hold after RdCS

, WrCS

Data hold after WrCS

1)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE

t

SR 0 – 0 – ns

51

t

SR – 20 + t

52

t

CC 20 + t

54

t

CC 20 + t

56

– 2TCL - 20

F

– 2TCL - 20

F

(see figures below).

– 2TCL - 20

F

+ – ns

t

+

F

– ns

t

+

F

t

F

ns

Data Sheet 43 V2.0, 2001-01

AC Characteristics

Multiplexed Bus (Reduced Supply Voltage Range)

(Operating Conditions apply) ALE cycle time = 6 TCL + 2

t

+ tC + tF (150 ns at 20 MHz CPU clock without waitstates)

A

C161K

C161O

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

ALE high time

Address setup to ALE

Address hold after ALE

ALE falling edge to RD WR

(with RW-delay)

ALE falling edge to RD WR

(no RW-delay)

Address float after RD WR

(with RW-delay)

Address float after RD,

(no RW-delay)

WR

t

CC 11 + t

5

t

CC 5 + t

6

t

CC 15 + t

7

,

t

CC 15 + t

8

,

t

CC -10 + tA– -10 + t

9

,

t

CC – 6 – 6ns

10

t

CC – 31 – TCL + 6 ns

11

A

– TCL - 14

A

– TCL - 20

– TCL - 10

A

– TCL - 10

A

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

– ns

t

+

A

– ns

+

t

A

– ns

t

+

A

– ns

+

t

A

– ns

Unit

, WR low time

RD (with RW-delay)

RD

, WR low time

(no RW-delay)

to valid data in

RD (with RW-delay)

RD

to valid data in

(no RW-delay) ALE low to valid data in

Address to valid data in

Data hold after RD

t

CC 34 + t

12

t

CC 59 + t

13

t

SR – 22 + t

14

t

SR – 47 + t

15

t

SR – 45 + t

16

t

SR – 57 + 2t

17

t

SR 0 – 0 – ns

18

– 2TCL - 16

C

+

– 3TCL - 16

C

+ – 2TCL - 28

C

– 3TCL - 28

C

– 3TCL - 30

A

+ t

C

– 4TCL - 43

A

+ t

C

– ns

t

C

– ns

t

C

+

t

C

t

+

C

+

t

+ t

A

2t

+

A

+ t

ns

C

ns

C

rising edge

Data Sheet 44 V2.0, 2001-01

Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply)

t

ALE cycle time = 6 TCL + 2

+ tC + tF (150 ns at 20 MHz CPU clock without waitstates)

A

C161K

C161O

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

Data float after RD t

Data valid to WR t

Data hold after WR

ALE rising edge after RD

,

SR – 36 + t

19

CC 24 + t

22

t

CC 36 + t

23

t

CC 36 + t

25

F

– 2TCL - 26

C

– 2TCL - 14

F

– 2TCL - 14

F

WR Address hold after RD

CC 36 + t

27

– 2TCL - 14

F

,

t

WR

1)

t

CC -8 - t

38

t

SR – 47+ t

39

t

CC 57 + t

40

10 - t

A

F

A

C

+ 2t

A

– 3TCL - 18

ALE falling edge to CS

low to Valid Data In

CS

CS hold after RD, WR

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

– 2TCL - 14

+

t

F

– ns

+

t

C

– ns

+

t

F

– ns

+

t

F

– ns

+

t

F

-8 - t

A

10 - t

A

– 3TCL - 28

t

+ 2t

+

C

A

– ns

+

t

F

Unit

ns

ns ns

ALE fall. edge to RdCS WrCS

(with RW delay)

ALE fall. edge to RdCS WrCS

(no RW delay)

Address float after RdCS WrCS

(with RW delay)

Address float after RdCS WrCS

RdCS

(no RW delay) to Valid Data In

(with RW delay) RdCS

to Valid Data In

(no RW delay) RdCS

, WrCS Low Time

(with RW delay) RdCS

, WrCS Low Time

(no RW delay)

,

t

CC 19 + t

42

,

t

CC -6 + t

43

,

t

CC – 0 – 0ns

44

,

t

CC – 25 – TCL ns

45

t

SR – 20 + t

46

t

SR – 45 + t

47

t

CC 38 + t

48

t

CC 63 + t

49

– TCL - 6

A

– -6

A

C

– 2TCL - 12

C

– 3TCL - 12

C

– ns

t

+

A

– ns

t

+

A

– 2TCL - 30

t

+

C

– 3TCL - 30

t

+

C

– ns

+

t

C

– ns

t

+

C

ns

Data Sheet 45 V2.0, 2001-01

Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2

t

+ tC + tF (150 ns at 20 MHz CPU clock without waitstates)

A

C161K

C161O

Parameter Symbol Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

min. max. min. max.

Data valid to WrCS t

Data hold after RdCS t Data float after RdCS

Address hold after RdCS

, WrCS

Data hold after WrCS

1)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE

CC 28 + t

50

SR 0 – 0 – ns

51

t

SR – 30 + t

52

t

CC 30 + t

54

t

CC 30 + t

56

– 2TCL - 22

C

F

– 2TCL - 20

F

– 2TCL - 20

F

(see figures below).

– ns

+

t

C

– 2TCL - 20

t

+

F

– ns

t

+

F

– ns

t

+

F

Unit

ns

Data Sheet 46 V2.0, 2001-01

C161K

C161O

Data Sheet 47 V2.0, 2001-01

C161K

C161O

ALE

CSxL

A21-A16 (A15-A8) BHE, CSxE

Read Cycle

BUS

RD

t

5

t

38

t

16

t

39

t

17

t

25

t

40

t

27

Address

t

6

Address

t

7

Data IN

t

8

t

10

t

14

t

12

t

54

t

19

t

18

RdCSx

Write Cycle

BUS

WR, WRL, WRH

WrCSx

t

42

t

4

t

46

t

48

t

51

t

52

t

23

Data OUTAddress

t

8

t

42

t

10

t

22

t

12

t

44

t

50

t

48

t

56

MCT04862

Figure 13 External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet 48 V2.0, 2001-01

C161K

C161O

ALE

CSxL

A21-A16 (A15-A8) BHE, CSxE

Read Cycle

BUS

RD

RdCSx

t

5

t

38

t

16

t

39

t

17

t

25

t

40

t

27

Address

t

6

t

7

t

54

t

19

t

18

Data INAddress

t

9

t

43

t

11

t

15

t

13

t

45

t

47

t

49

t

51

t

52

Write Cycle

BUS

Address

t

9

Data OUT

t

11

t

22

t

13

t

23

t

56

WR, WRL, WRH

t

43

t

45

t

50

t

49

WrCSx

MCT04863

Figure 14 External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet 49 V2.0, 2001-01

C161K

C161O

ALE

CSxL

A21-A16 (A15-A8) BHE, CSxE

Read Cycle

BUS

RD

t

5

t

38

t

16

t

39

t

17

t

25

t

40

t

27

Address

t

6

Address

t

7

Data IN

t

9

t

11

t

15

t

13

t

54

t

19

t

18

t

43

RdCSx

Write Cycle

BUS

t

9

WR, WRL, WRH

t

43

WrCSx

Figure 15 External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Extended ALE

t

45

t

47

t

49

t

51

t

52

t

23

Data OUTAddress

t

11

t

45

t

22

t

13

t

50

t

49

t

56

MCT04864

Data Sheet 50 V2.0, 2001-01

AC Characteristics

Demultiplexed Bus (Standard Supply Voltage Range)

(Operating Conditions apply) ALE cycle time = 4 TCL + 2

t

+ tC + tF (80 ns at 25 MHz CPU clock without waitstates)

A

C161K

C161O

Parameter Symbol Max. CPU Clock

= 25 MHz

min. max. min. max.

ALE high time

Address setup to ALE

ALE falling edge to RD

(with RW-delay)

WR ALE falling edge to RD

WR

(no RW-delay)

RD

, WR low time

t

CC 10 + t

5

t

CC 4 + t

6

,

t

CC 10 + t

8

,

t

CC -10 + tA– -10

9

t

CC 30 + t

12

– TCL - 10

A

– TCL - 16

A

– TCL - 10

A

– 2TCL - 10

C

(with RW-delay)

, WR low time

RD

t

CC 50 + t

13

– 3TCL - 10

C

(no RW-delay)

t

RD to valid data in

SR – 20 + t

14

C

(with RW-delay)

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

– ns

t

+

A

– ns

+

t

A

– ns

t

+

A

– ns

+

t

A

– ns

+

t

C

– ns

+

t

C

– 2TCL - 20

t

+

C

Unit

ns

to valid data in

RD (no RW-delay)

ALE low to valid data in

Address to valid data in

Data hold after RD

t

SR – 40 + t

15

t

SR – 40 +

16

t

+ t

A

C

t

SR – 50 +

17

2

t

+ t

A

t

SR 0 – 0 – ns

18

– 3TCL - 20

C

– 3TCL - 20

– 4TCL - 30

C

+

t

C

t

+ t

+

A

+

2t

A

+ t

ns

C

ns

C

rising edge Data float after RD

rising

edge (with RW-delay

Data float after RD edge (no RW-delay

Data Sheet 51 V2.0, 2001-01

rising

1)

)

t

SR – 26 +

20

)

t

SR – 10 +

21

2

t

+ t

A

t

+ t

2

A

– 2TCL - 14

1)

F

– TCL - 10

1)

F

+ +

22t t

F

22t t

F

1)

ns

A

ns

A

Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply)

t

ALE cycle time = 4 TCL + 2

+ tC + tF (80 ns at 25 MHz CPU clock without waitstates)

A

C161K

C161O

Parameter Symbol Max. CPU Clock

= 25 MHz

min. max. min. max.

Data valid to WR t

Data hold after WR t

ALE rising edge after RD

, WR Address hold after WR ALE falling edge to CS

low to Valid Data In

CS

CS hold after RD, WR

2)

3)

ALE falling edge to RdCS

, WrCS (with RW-

CC 20 + t

22

CC 10 + t

24

t

CC -10 + tF– -10 + t

26

t

CC 0 + t

28

t

CC -4 - t

38

t

SR – 40 +

39

t

CC 6 + t

41

t

CC 16 + t

42

– 2TCL - 20

C

– TCL - 10

F

– 0 + t

F

10 - t

A

F

A

tC + 2t

A

– TCL - 14

– TCL - 4

delay)

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

– ns

+

t

C

– ns

+

t

F

– ns

10 - t

A

-4 - t

F

A

– 3TCL - 20

+

t

+ 2t

C

A

– ns

+

t

F

– ns

+

t

A

Unit

ns ns

ALE falling edge to RdCS

, WrCS (no RW-

delay) RdCS

to Valid Data In

(with RW-delay) RdCS

to Valid Data In

(no RW-delay) RdCS

, WrCS Low Time

(with RW-delay) RdCS

, WrCS Low Time

(no RW-delay) Data valid to WrCS

Data hold after RdCS

t

CC -4 + t

43

t

SR – 16 + t

46

t

SR – 36 + t

47

t

CC 30 + t

48

t

CC 50 + t

49

t

CC 26 + t

50

t

SR 0 – 0 – ns

51

– -4

A

C

– 2TCL - 10

C

– 3TCL - 10

C

– 2TCL - 14

C

– ns

t

+

A

– 2TCL - 24

t

+

C

– 3TCL - 24

+

t

C

– ns

t

+

C

– ns

+

t

C

– ns

t

+

C

ns

Data Sheet 52 V2.0, 2001-01

Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2

t

+ tC + tF (80 ns at 25 MHz CPU clock without waitstates)

A

C161K

C161O

Parameter Symbol Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

min. max. min. max.

Data float after RdCS (with RW-delay)

1)

Data float after RdCS (no RW-delay)

1)

Address hold after RdCS

, WrCS

Data hold after WrCS

1)

RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2)

Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD

3)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE

t

SR – 20 + t

53

t

SR – 0 + t

68

t

CC -6 + t

55

t

CC 6 + t

57

F

have no impact on read cycles.

F

– -6 + t

F

– TCL - 14

(see figures below).

– 2TCL - 20

+

2t

+ tF

A

1)

– TCL - 20

+

2t

+ tF

A

1)

F

– ns

t

+

F

Unit

ns

Data Sheet 53 V2.0, 2001-01

C161K

C161O

AC Characteristics

Demultiplexed Bus (Reduced Supply Voltage Range)

(Operating Conditions apply) ALE cycle time = 4 TCL + 2

Parameter SymuC(m)3.5(e)- 786.425 c125.009 781.48B5.C4 l86.199 781.654 l86.199 791.268 l881Tj002 Tc-0.002 Tw[(Pa)3.8(ra)3.8(m)3.5(e)-5.7(t)9.4(e)-5.7(r)-6658.7(S)0. 1 Tfd9o.7(r)4.8(a)8.7(t)6.9(i)8(ng)8.784.341 113.164 7( Tm-0.003 T.34W3 T.34W3 T.34O312.00)199 781.654 l86./F691.C48 ref1362.5(3.1) 655.11.7(t)9.4(e)-55(4 TC)-4.7(L + )-9.5(2)]TJw 2 Tm-0.00105 210.93 651.9901 Tm(A)Tj12.5995 0 0 114.75ter SL + 2

t

+ tC + tF (100 ns at 20 MHz CPU clock without waitstates)

A

Data Sheet 54 V2.0, 2001-01

Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply)

t

ALE cycle time = 4 TCL + 2

+ tC + tF (100 ns at 20 MHz CPU clock without waitstates)

A

C161K

C161O

Parameter Symbol Max. CPU Clock

= 20 MHz

min. max. min. max.

Data valid to WR t

Data hold after WR t

ALE rising edge after RD

, WR Address hold after WR ALE falling edge to CS

low to Valid Data In

CS

CS hold after RD, WR

2)

3)

ALE falling edge to RdCS

, WrCS (with RW-

CC 24 + t

22

CC 15 + t

24

t

CC -12 + tF– -12 + t

26

t

CC 0 + t

28

t

CC -8 - t

38

t

SR – 47 +

39

t

CC 9 + t

41

t

CC 19 + t

42

– 2TCL - 26

C

– TCL - 10

F

– 0 + t

F

10 - t

A

F

A

tC + 2t

A

– TCL - 16

– TCL - 6

delay)

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

– ns

+

t

C

– ns

+

t

F

– ns

10 - t

A

-8 - t

F

A

– 3TCL - 28

+

t

+ 2t

C

A

– ns

+

t

F

– ns

+

t

A

Unit

ns ns

ALE falling edge to RdCS

, WrCS (no RW-

delay) RdCS

to Valid Data In

(with RW-delay) RdCS

to Valid Data In

(no RW-delay) RdCS

, WrCS Low Time

(with RW-delay) RdCS

, WrCS Low Time

(no RW-delay) Data valid to WrCS

Data hold after RdCS

t

CC -6 + t

43

t

SR – 20 + t

46

t

SR – 45 + t

47

t

CC 38 + t

48

t

CC 63 + t

49

t

CC 28 + t

50

t

SR 0 – 0 – ns

51

– -6

A

C

– 2TCL - 12

C

– 3TCL - 12

C

– 2TCL - 22

C

– ns

t

+

A

– 2TCL - 30

t

+

C

– 3TCL - 30

+

t

C

– ns

t

+

C

– ns

+

t

C

– ns

t

+

C

ns

Data Sheet 55 V2.0, 2001-01

Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2

t

+ tC + tF (100 ns at 20 MHz CPU clock without waitstates)

A

C161K

C161O

Parameter Symbol Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

min. max. min. max.

Data float after RdCS (with RW-delay)

1)

Data float after RdCS (no RW-delay)

1)

Address hold after RdCS

, WrCS

Data hold after WrCS

1)

RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2)

Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD

3)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE

t

SR – 30 + t

53

t

SR – 5 + t

68

t

CC -16 + tF– -16 + t

55

t

CC 9 + t

57

– TCL - 16

F

have no impact on read cycles.

(see figures below).

F

– 2TCL - 20

+

2t

+ tF

A

1)

– TCL - 20

+

2t

+ tF

A

1)

F

– ns

t

+

F

Unit

ns

Data Sheet 56 V2.0, 2001-01

A21-A16 A15-A0 BHE, CSxE

C161K

C161O

Address

Data IN

Data OUT

MCT04865

Figure 16 External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet 57 V2.0, 2001-01

C161K

C161O

ALE

CSxL

A21-A16 A15-A0 BHE, CSxE

Read Cycle

BUS (D15-D8) D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

20

t

18

Data IN

t

8

t

14

t

12

RdCSx

Write Cycle

BUS (D15-D8) D7-D0

WR, WRL, WRH

WrCSx

t

42

t

46

t

48

t

51

t

53

t

24

Data OUT

t

8

t

42

t

22

t

12

t

50

t

48

t

57

MCT04866

Figure 17 External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet 58 V2.0, 2001-01

C161K

C161O

ALE

CSxL

A21-A16 A15-A0 BHE, CSxE

Read Cycle

BUS (D15-D8) D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

21

t

18

Data IN

t

9

t

43

t

15

t

13

t

47

t

49

t

51

t

68

RdCSx

Write Cycle

BUS (D15-D8) D7-D0

t

9

WR, WRL, WRH

t

43

WrCSx

Figure 18 External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Normal ALE

t

24

Data OUT

t

22

t

13

t

50

t

49

t

57

MCT04867

Data Sheet 59 V2.0, 2001-01

C161K

C161O

ALE

CSxL

A21-A16 A15-A0 BHE, CSxE

Read Cycle

BUS (D15-D8) D7-D0

RD

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

21

t

18

Data IN

t

9

t

15

t

13

RdCSx

Write Cycle

BUS (D15-D8) D7-D0

WR, WRL, WRH

WrCSx

t

43

t

47

t

49

t

51

t

68

t

24

Data OUT

t

9

t

43

t

22

t

13

t

50

t

49

t

57

MCT04868

Figure 19 External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet 60 V2.0, 2001-01

Package Outlines

P-MQFP-80-1 (SMD)

(Plastic Metric Quad Flat Package)

C161K

C161O

0.65

±0.08

0.3

12.35

17.2

1)

14

D

A

80

Index Marking

1) Does not include plastic or metal protrusions of 0.25 max per side

1

0.6x45˚

C

B

+0.1

-0.05

2.45 max

2

0.25 min

0.1

M

0.12

0.2

A-B

0.2

A-B

1)

17.2

14

A-B

D

H

D

80x HD

4x

C

0.88

80x

-0.02

+0.08

0.15

7˚max

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

SMD = Surface Mounted Device

Dimensions in mm

Data Sheet 61 V2.0, 2001-01

GPR05249

Infineon goes for Business Excellence

“Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.”

Dr. Ulrich Schumacher

http://www.infineon.com

Published by Infineon Technologies AG

Datasheet C161K, C161O Datasheet (Amphenol)

Specifications and Main Features

Frequently Asked Questions

User Manual

Ordering Information

Functional Description

Memory Organization

External Bus Controller

Central Processing Unit (CPU)

Interrupt System

General Purpose Timer (GPT) Unit

Serial Channels

Watchdog Timer

Parallel Ports

Instruction Set Summary

Special Function Registers Overview

Absolute Maximum Ratings

Parameter Interpretation

DC Characteristics (Standard Supply Voltage Range)

DC Characteristics (Reduced Supply Voltage Range)

Power Consumption C161K/O (Standard Supply Voltage Range)

Power Consumption C161K/O (Reduced Supply Voltage Range)

AC Characteristics Definition of Internal Timing

Prescaler Operation

Direct Drive

AC Characteristics

Testing Waveforms

Memory Cycle Variables

AC Characteristics

Multiplexed Bus (Standard Supply Voltage Range)

AC Characteristics

Multiplexed Bus (Reduced Supply Voltage Range)

AC Characteristics

Demultiplexed Bus (Standard Supply Voltage Range)

AC Characteristics

Demultiplexed Bus (Reduced Supply Voltage Range)

Package Outlines