HORIZONTAL DEFLECTION FOR HIGH-END
COLOUR TV AND 19" MONITORS
DESCRIPTION
The BUW1015 is manufactured using
Multiepitaxial Mesa technology for cost-effective
high performance and uses a Hollow Emitter
structure to enhance switching speeds.
BUW1015
NPN POWER TRANSISTOR
3
2
1
TO-247
INTERNAL SCHEMATIC DIAGRA M
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
P
T
Collector-Base Voltage (IE = 0)1500V
CBO
Collector-Emitter Voltage (IB = 0)700V
CEO
Emitter-Base Voltage (IC = 0)10V
EBO
Collector Current14A
I
C
Collector Peak Current (tp < 5 ms)18A
CM
Base Current8A
I
B
Base Peak Current (tp < 5 ms)11A
BM
Total Dissipation at Tc = 25 oC160W
tot
Storage Temperature-65 to 150
stg
Max. Operating Junction Temperature150
T
j
o
C
o
C
February 2002
1/7
Page 2
BUW1015
THERMAL DATA
R
thj-case
Thermal Resistance Junction-case Max0.78
o
C/W
ELECTRICAL CHARACT ER ISTI CS
= 25 oC unless otherwise specified)
(T
case
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
CES
I
EBO
V
CEO(sus)
Collector Cut-off
Current (V
BE
= 0)
Emitter Cut-off Current
(I
= 0)
C
∗ Collector-Emitter
= 1500 V
V
CE
V
= 1500 V Tj = 125 oC
CE
= 5 V100µA
V
EB
I
= 100 mA 700V
C
0.2
2
Sustaining Voltage
(I
= 0)
B
V
EBO
Emitter-Base Voltage
(I
V
∗ Collector-Emitter
CE(sat)
= 0)
C
= 10 mA 10V
I
E
= 10 A IB = 2 A1.5V
I
C
Saturation Voltage
V
∗ Base-Emitter
BE(sat)
= 10 A IB = 2 A1.5V
I
C
Saturation Voltage
h
∗DC Current GainI
FE
RESISTIVE LOAD
s
t
f
Storage Time
Fall Time
t
INDUCTIVE LOAD
t
s
t
f
Storage Time
Fall Time
INDUCTIVE LOAD
s
t
f
Storage Time
Fall Time
t
∗
Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
= 10 A VCE = 5 V
C
I
= 10 A VCE = 5 V Tj = 100 oC
C
V
= 400 V IC = 10 A
CC
I
= 2 A IB2= -6 A1.5
B1
I
= 10 A f = 31250 Hz
C
I
= 2 A I
B1
V
I
C
I
B1
V
V
= 1200 sin
ceflyback
= 6 A f = 64 KHz
= 1 A
= - 2 V
beoff
= 1100 sin
ceflyback
B2
= -6 A
π
10
5
π
10
5
6
6
t V
t V
7
5
1014
110
4
220
3.7
200
mA
mA
µs
ns
µs
ns
µs
ns
2/7
Page 3
BUW1015
Safe Operating Area
Derating Curve
Thermal Impedance
DC Current Gain
Collector Emitter Saturation Voltage
Base Emitter Saturation Voltage
3/7
Page 4
BUW1015
Power Losses at 64 KHz Switching Time Inductive Load at 64KHz
(see figure 2)
Reverse Biased SOA
BASE DRIVE INFORMATION
In order to saturate the power switch and reduce
conduction losses, adequate direct base current
I
has to be provided for the lowest gain hFE at T
B1
= 100 oC (line scan phase). On the other hand,
negative base current I
must be provided the
B2
transistor to turn off (retrace phase). Most of the
dissipation, especially in the deflection
application, occurs at switch-off so it is essential
to determine the value of I
power losses, fall time t
and, consequently, Tj. A
f
which minimizes
B2
new set of curves have been defined to give total
power losses, t
and tf as a function of IB1 at 64
s
KHz scanning frequencies for choosing the
4/7
optimum drive. The test circuit is illustrated in
figure 1.
j
The values of L and C are calculated from the
following equations:
1
L
2
ω =
(
2
1
2
)
I
=
C
π
f
=
C
2
1
L
√
(
C
V
CEfly
2
)
Where IC= operating collector current, V
flyback voltage, f= frequency of oscillation during
retrace.
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