Datasheet BUK9614-55A Datasheet (Philips)

Philips Semiconductors Product specification

TrenchMOS transistor BUK9614-55
Logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effectpowertransistorina
plastic envelope suitable for surface V
mounting. Using ’trench’ technology I
thedevice features very low on-state P
resistance and has integral zener T
diodes giving ESD protection up to R

DS

D

tot
j

DS(ON)

2kV. It is intended for use in resistance VGS = 5 V
automotive and general purpose
switching applications.

PINNING - SOT404 PIN CONFIGURATION SYMBOL

Drain-source voltage 55 V
Drain current (DC) 68 A
Total power dissipation 142 W
Junction temperature 175 ˚C
Drain-source on-state 14 mΩ

PIN DESCRIPTION

mb

d

1 gate
2 drain
3 source

mb drain

2

13

g

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
±V
I

D

I

D

I

DM

P
T

DS
DGR

tot

stg

GS

, T

j

Drain-source voltage - - 55 V
Drain-gate voltage RGS = 20 kΩ -55V
Gate-source voltage - - 10 V
Drain current (DC) Tmb = 25 ˚C - 68 A
Drain current (DC) Tmb = 100 ˚C - 48 A
Drain current (pulse peak value) Tmb = 25 ˚C - 240 A
Total power dissipation Tmb = 25 ˚C - 142 W
Storage & operating temperature - - 55 175 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

Electrostatic discharge capacitor Human body model - 2 kV
voltage (100 pF, 1.5 kΩ)

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

R

th j-a

April 1998 1 Rev 1.000

Thermal resistance junction to - - 1.05 K/W
mounting base
Thermal resistance junction to Minimum footprint, FR4 50 - K/W
ambient board

Philips Semiconductors Product specification

TrenchMOS transistor BUK9614-55

Logic level FET

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

I

DSS

I

GSS

±V
R

DS(ON)

(BR)GSS

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V

Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA

Tj = 175˚C - - 500 uA

Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA

Tj = 175˚C - - 10 µA
Gate-source breakdown IG = ±1 mA; 10 - - V
voltage
Drain-source on-state VGS = 5 V; ID = 25 A - 12 14 mΩ
resistance Tj = 175˚C - - 30 mΩ

DYNAMIC CHARACTERISTICS

Tmb = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g
C

C
C

t
t
t
t

L

fs

iss
oss
rss

d on
r
d off
f

d

Forward transconductance VDS = 25 V; ID = 25 A 30 65 - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 2900 3800 pF

Output capacitance - 500 600 pF
Feedback capacitance - 240 330 pF

Turn-on delay time VDD = 30 V; ID = 25 A; - 35 50 ns
Turn-on rise time VGS = 5 V; RG = 10 Ω - 95 145 ns
Turn-off delay time - 130 180 ns
Turn-off fall time - 60 80 ns

Internal drain inductance Measured from upper edge of drain - 2.5 - nH

tab to centre of die

L

s

Internal source inductance Measured from source lead - 7.5 - nH

soldering point to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V

t

rr

Q

SD

rr

Continuous reverse drain - - 68 A
current
Pulsed reverse drain current - - 240 A
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V

IF = 65 A; VGS = 0 V - 1.0 - V

Reverse recovery time IF = 65 A; -dIF/dt = 100 A/µs; - 57 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.14 - µC

April 1998 2 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9614-55

Logic level FET

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

Drain-source non-repetitive ID = 65 A; VDD ≤ 25 V; - - 200 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Tmb / C

= f(Tmb)

D 25 ˚C

Normalised Current Derating

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

100

SOAX514

tp =
1 us

10 us
100 us

1 ms

10 ms
100 ms

1000

ID / A

RDS(ON) = VDS/ID

100

10

1

11055

DC

VDS / V

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

t

p

T

BUKX514-55

p

t

D =

T

t

Zth / (K/W)

1E+01

1E+00

1E-01

1E-02

1E-03

0.5

0.2

0.1

0.05

0.02

0

1E-07 1E-05 1E-03 1E-01 1E+01

t / s

P

D

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

p

April 1998 3 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9614-55
Logic level FET

100

10

ID/A

5

80

60

40

20

0

0246810

4

VDS/V

VGS/V =

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

Fig.5. Typical output characteristics, Tj = 25 ˚C

RDS(ON)/mOhm

20

18

16

14

ID = f(VDS); parameter V

VGS/V =

3.6

GS

4

4.2

4.4

4.6
5

70

gfs/S

60

50

40

30

20

10

0

0 20406080100

.

Fig.8. Typical transconductance, Tj = 25 ˚C

ID/A

.

gfs = f(ID); conditions: VDS = 25 V

2.5

1.5

a

2

BUK959-60

Rds(on) normlised to 25degC

12

10

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100

ID/A

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

= f(ID); parameter V

DS(ON)

100

ID/A

80

60

40

20

0

012345

Tj/C = 175 25

VGS/V

GS

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

1

0.5

-100 -50 0 50 100 150 200

.

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

VGS(TO) / V

2.5
max.

2

typ.

1.5

min.

1

0.5

0

-100 -50 0 50 100 150 200

Tmb / degC

= f(Tj); ID = 25 A; VGS = 5 V

BUK959-60

Tj / C

Fig.10. Gate threshold voltage.

V

j

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

GS

April 1998 4 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9614-55
Logic level FET

1E-01

1E-02

1E-03

1E-04

1E-05

1E-05

0 0.5 1 1.5 2 2.5 3

2% typ

Sub-Threshold Conduction

98%

Fig.11. Sub-threshold drain current.

ID = f(V

6

5

4

3

Thousands pF

2

1

0

0.01 0.1 1 10 100

Fig.12. Typical capacitances, C

; conditions: Tj = 25 ˚C; VDS = V

GS)

VDS/V

, C

iss

oss

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

, C

GS

rss

Ciss

Coss
Crss

.

100

IF/A

80

60

40

Tj/C = 175 25

20

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4

VSDS/V

Fig.14. Typical reverse diode current.

IF = f(V

120
110
100

90
80
70
60
50
40
30
20
10

0

); conditions: V

SDS

WDSS%

20 40 60 80 100 120 140 160 180

= 0 V; parameter T

GS

Tmb / C

Fig.15. Normalised avalanche energy rating.

W

% = f(Tmb); conditions: ID = 75 A

DSS

j

6

VGS/V

5

VDS = 14V

4

3

2

1

0

0 1020304050

QG/nC

VDS = 44V

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); conditions: ID = 50 A; parameter V

GS

DS

L

VDS

VGS

0

RGS

T.U.T.

Fig.16. Avalanche energy test circuit.

W

= 0.5 ⋅LI

DSS

2

D

⋅BV

DSS

/(BV

R 01

shunt

DSS−VDD

VDD

+

-

-ID/100

)

April 1998 5 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9614-55
Logic level FET

VDD

+

RD

VDS

VGS

0

RG

T.U.T.

Fig.17. Switching test circuit.

-

April 1998 6 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9614-55

Logic level FET

MECHANICAL DATA

Dimensions in mm
Net Mass: 1.4 g

2.54 (x2)

MOUNTING INSTRUCTIONS

Dimensions in mm

10.3 max

11 max

15.4

0.85 max
(x2)

4.5 max

1.4 max

0.5

Fig.18. SOT404 : centre pin connected to mounting base.

11.5

2.5

9.0

17.5

2.0

3.8

5.08

Fig.19. SOT404 : soldering pattern for surface mounting

.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

April 1998 7 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9614-55

Logic level FET

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

April 1998 8 Rev 1.000