Page 1
Philips Semiconductors Product specification
TrenchMOS transistor BUK9605-30A
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effectpowertransistorina
plastic envelope suitable for surface V
mounting. Using ’trench’ technology I
thedevice features very low on-state P
resistance. It is intended for use in T
automotive and general purpose R
DS
D
tot
j
DS(ON)
switching applications. resistance VGS = 5 V 5 mΩ
PINNING - SOT404 PIN CONFIGURATION SYMBOL
Drain-source voltage 30 V
Drain current (DC) 75 A
Total power dissipation 230 W
Junction temperature 175 ˚C
Drain-source on-state
V
= 10 V 4.6 mΩ
GS
PIN DESCRIPTION
mb
d
1 gate
2 drain
(no connection possible)
3 source
mb drain
2
13
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
±V
±V
I
D
I
D
I
DM
P
T
DS
DGR
tot
stg
GS
GSM
, T
j
Drain-source voltage - - 30 V
Drain-gate voltage RGS = 20 kΩ -30V
Gate-source voltage - - 10 V
Non-repetitive gate-source voltage tp≤50µS - 15 V
Drain current (DC) Tmb = 25 ˚C - 75 A
Drain current (DC) Tmb = 100 ˚C - 75 A
Drain current (pulse peak value) Tmb = 25 ˚C - 400 A
Total power dissipation Tmb = 25 ˚C - 230 W
Storage & operating temperature - - 55 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
R
th j-a
August 1999 1 Rev 1.100
Thermal resistance junction to - - 0.65 K/W
mounting base
Thermal resistance junction to Minimum footprint, FR4 50 - K/W
ambient board
Page 2
Philips Semiconductors Product specification
TrenchMOS transistor BUK9605-30A
Logic level FET
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
R
DS(ON)
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 30 - - V
voltage Tj = -55˚C 27 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2.0 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
Zero gate voltage drain current VDS = 30 V; VGS = 0 V; - 0.05 10 µA
Tj = 175˚C - - 500 µA
Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
Drain-source on-state VGS = 5 V; ID = 25 A - 4.3 5 mΩ
resistance Tj = 175˚C - - 9.3 mΩ
VGS = 10 V; ID = 25 A - 3.9 4.6 mΩ
VGS = 4.5 V; ID = 25 A - - 5.4 mΩ
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
C
C
C
t
t
t
t
L
iss
oss
rss
d on
r
d off
f
d
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 6500 8600 pF
Output capacitance - 1500 1800 pF
Feedback capacitance - 1000 1350 pF
Turn-on delay time VDD = 30 V; R
=1.2Ω; - 45 65 ns
load
Turn-on rise time VGS = 5 V; RG = 10 Ω - 220 330 ns
Turn-off delay time - 435 600 ns
Turn-off fall time - 320 450 ns
Internal drain inductance Measured from upper edge of drain - 2.5 - nH
tab to centre of die
L
s
Internal source inductance Measured from source lead - 7.5 - nH
soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DR
I
DRM
V
t
rr
Q
SD
rr
Continuous reverse drain - - 75 A
current
Pulsed reverse drain current - - 240 A
Diode forward voltage IF = 25 A; VGS = 0 V - 0.85 1.2 V
IF = 75 A; VGS = 0 V - 1.1 - V
Reverse recovery time IF = 75 A; -dIF/dt = 100 A/µs; - 400 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 1.0 - µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
W
DSS
August 1999 2 Rev 1.100
Drain-source non-repetitive ID = 75 A; VDD ≤ 25 V; - - 500 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
Page 3
Philips Semiconductors Product specification
TrenchMOS transistor BUK9605-30A
Logic level FET
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Normalised Power Derating
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/P
ID%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
= f(Tmb)
D 25 ˚C
Normalised Current Derating
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
= f(Tmb); conditions: VGS ≥ 5 V
D 25 ˚C
Zth / (K/W)
P
t/S
D
D =
T
t
T
p
t
p
t
0.1
0.01
0.001
1
D =
0.5
0.2
0.1
0.05
0.02
0
0.00001 0.001 0.1 10
Fig.4. Transient thermal impedance.
Z
= f(t); parameter D = tp/T
th j-mb
400
10.0
7.0
ID/V
6.0
5.0
300
200
100
0
0246810
4.8
4.6
4.4
VGS/V =
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
VDS/V
Fig.5. Typical output characteristics, Tj = 25 ˚C
ID = f(VDS); parameter V
GS
.
1000
ID/A
RDS(ON) = VDS/ID
100
10
1
1 10 100
DC
VDS/V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter t
tp =
100uS
1mS
10mS
100mS
p
RDS(ON)/mOhm
11
10
9
VGS/V =
8
7
6
5
4
3
3.0
3.2
3.4
3.6
4.0
5.0
0 20406080100
ID/A
Fig.6. Typical on-state resistance, Tj = 25 ˚C
R
= f(ID); parameter V
DS(ON)
GS
.
August 1999 3 Rev 1.100
Page 4
Philips Semiconductors Product specification
TrenchMOS transistor BUK9605-30A
Logic level FET
RDS(ON)/mOhm
6.5
6
5.5
5
4.5
4
3.5
3
345678910
VGS/V
Fig.7. Typical on-state resistance, Tj = 25 ˚C
R
= f(VGS); conditions: ID = 25 A;
DS(ON)
100
ID/A
80
60
175
40
Tj/C =
25
a
2
1.5
1
0.5
0
-100 0 100 200
.
Fig.10. Normalised drain-source on-state resistance.
a = R
DS(ON)/RDS(ON)25 ˚C
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
Tj / C
= f(Tj); ID = 25 A; VGS = 5 V
30V TrenchMOS
15050-50
BUK959-60
20
0
0 0.5 1 1.5 2 2.5 3 3.5
VGS/V
Fig.8. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter T
150
gfs/S
100
50
0
0 20406080100
ID/A
Fig.9. Typical transconductance, Tj = 25 ˚C
gfs = f(ID); conditions: VDS = 25 V
0.5
0
-100 -50 0 50 100 150 200
Tj / C
Fig.11. Gate threshold voltage.
V
j
1E-01
1E-02
1E-03
1E-04
1E-05
1E-05
.
= f(Tj); conditions: ID = 1 mA; VDS = V
GS(TO)
Sub-Threshold Conduction
2% typ
0 0.5 1 1.5 2 2.5 3
98%
GS
Fig.12. Sub-threshold drain current.
ID = f(V
; conditions: Tj = 25 ˚C; VDS = V
GS)
GS
August 1999 4 Rev 1.100
Page 5
Philips Semiconductors Product specification
TrenchMOS transistor BUK9605-30A
Logic level FET
20
15
10
Thousands pF
5
0
0.01 0.1 1 10 100
Fig.13. Typical capacitances, C
VDS/V
, C
iss
oss
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
6
VGS/V
5
4
VDS =
3
2
14V
24V
, C
rss
Ciss
Coss
Crss
.
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.16. Normalised avalanche energy rating.
W
% = f(Tmb); conditions: ID = 75 A
DSS
+
L
VDS
VGS
0
T.U.T.
-
VDD
-ID/100
1
0
0 20 40 60 80 100 120
QG/nC
Fig.14. Typical turn-on gate-charge characteristics.
V
= f(QG); conditions: ID = 50 A; parameter V
GS
100
ID/A
80
60
Tj/C =
40
20
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
175
VSDS/V
DS
25
Fig.15. Typical reverse diode current.
IF = f(V
); conditions: V
SDS
= 0 V; parameter T
GS
j
RGS
Fig.17. Avalanche energy test circuit.
RG
2
D
⋅BV
DSS
/(BV
RD
DSS−VDD
VDS
T.U.T.
VGS
0
W
= 0.5 ⋅LI
DSS
Fig.18. Switching test circuit.
R 01
shunt
)
VDD
+
-
August 1999 5 Rev 1.100
Page 6
Philips Semiconductors Product specification
TrenchMOS transistor BUK9605-30A
Logic level FET
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
base
A
1
L
p
c
Q
E
D
1
D
H
D
2
13
b
e e
0 2.5 5 mm
scale
mounting
SOT404
A
DIMENSIONS (mm are the original dimensions)
A
UNIT
mm
A
4.50
4.10
OUTLINE
VERSION
SOT404
b
1
1.40
0.85
1.27
0.60
IEC JEDEC EIAJ
0.64
0.46
max.
D
11
D
1
1.60
1.20
REFERENCES
E
10.30
9.70
2.54
eLpHDQc
2.60
15.40
2.90
2.10
14.80
2.20
EUROPEAN
PROJECTION
ISSUE DATE
98-12-14
99-06-25
Fig.19. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
August 1999 6 Rev 1.100
Page 7
Philips Semiconductors Product specification
TrenchMOS transistor BUK9605-30A
Logic level FET
MOUNTING INSTRUCTIONS
Dimensions in mm
9.0
3.8
Fig.20. SOT404 : soldering pattern for surface mounting
11.5
17.5
2.0
5.08
.
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999 7 Rev 1.100
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