Datasheet BUK9640-100A, BUK9540-100A Datasheet (Philips)

Philips Semiconductors Product specification

TrenchMOS transistor BUK9540-100A
Logic level FET BUK9640-100A

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effectpowertransistorina
plastic envelope available in V

DS

Drain-source voltage 100 V

TO220AB and SOT404 . Using I

D

Drain current (DC) 37 A

’trench’ technology which features P

tot

Total power dissipation 138 W

very low on-state resistance. It is T

j

Junction temperature 175 ˚C

intended for use in automotive and R

DS(ON)

Drain-source on-state
general purpose switching resistance VGS = 5 V 40 mΩ
applications. VGS = 10 V 39 mΩ

PINNING
TO220AB & SOT404 PIN CONFIGURATION SYMBOL

PIN DESCRIPTION

1 gate
2 drain
3 source

tab/mb drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

Drain-source voltage - - 100 V

V

DGR

Drain-gate voltage RGS = 20 kΩ - 100 V

±V

GS

Gate-source voltage - - 10 V

±V

GSM

Non-repetitive gate-source voltage tp≤50µS - 15 V

I

D

Drain current (DC) Tmb = 25 ˚C - 37 A

I

D

Drain current (DC) Tmb = 100 ˚C - 26 A

I

DM

Drain current (pulse peak value) Tmb = 25 ˚C - 149 A

P

tot

Total power dissipation Tmb = 25 ˚C - 138 W

T

stg

, T

j

Storage & operating temperature - - 55 175 ˚C

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

Thermal resistance junction to - - 1.1 K/W
mounting base

R

th j-a

Thermal resistance junction to in free air 60 - K/W
ambient(TO220AB)

R

th j-a

Thermal resistance junction to Minimum footprint, FR4 50 - K/W
ambient(SOT404) board

123

tab

13

mb

2

SOT404

TO220AB

d

g

s

December 1999 1 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9540-100A
Logic level FET BUK9640-100A

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - V
voltage Tj = -55˚C 89 - - V

V

GS(TO)

Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2.0 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V

I

DSS

Zero gate voltage drain current VDS = 100 V; VGS = 0 V; - 0.05 10 µA

Tj = 175˚C - - 500 µA

I

GSS

Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA

R

DS(ON)

Drain-source on-state VGS = 5 V; ID = 25 A - 30 40 mΩ
resistance Tj = 175˚C - - 100 mΩ

VGS = 10 V; ID = 25 A - 29 39 mΩ
VGS = 4.5 V; ID = 25 A - 31 43 mΩ

DYNAMIC CHARACTERISTICS

Tmb = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

C

iss

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 2304 3072 pF

C

oss

Output capacitance - 222 266 pF

C

rss

Feedback capacitance - 151 207 pF

t

d on

Turn-on delay time VDD = 30 V; R

load

=1.2Ω; - 20 30 ns

t

r

Turn-on rise time VGS = 5 V; RG = 10 Ω - 135 189 ns

t

d off

Turn-off delay time - 125 189 ns

t

f

Turn-off fall time - 90 135 ns

L

d

Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH

from package to centre of die

L

d

Internal drain inductance Measured from contact screw on - 3.5 - nH

tab to centre of die(TO220AB)

L

d

Internal drain inductance Measured from upper edge of drain - 2.5 - nH

tab to centre of die(SOT404)

L

s

Internal source inductance Measured from source lead to - 7.5 - nH

source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

Continuous reverse drain - - 37 A
current

I

DRM

Pulsed reverse drain current - - 149 A

V

SD

Diode forward voltage IF = 25 A; VGS = 0 V - 0.85 1.2 V

IF = 37 A; VGS = 0 V - 1.1 - V

t

rr

Reverse recovery time IF = 37 A; -dIF/dt = 100 A/µs; - 60 - ns

Q

rr

Reverse recovery charge VGS = -10 V; VR = 30 V - 0.24 - µC

December 1999 2 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9540-100A
Logic level FET BUK9640-100A

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

1

Drain-source non-repetitive ID = 25 A; VDD ≤ 25 V; - - 31 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

D 25 ˚C

= f(Tmb)

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

D 25 ˚C

= f(Tmb); conditions: VGS ≥ 5 V

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

p

Fig.4. Transient thermal impedance.

Z

th j-mb

= f(t); parameter D = tp/T

0 20 40 60 80 100 120 140 160 180

Tmb / C

PD%

Normalised Power Derating

120
110
100

90
80
70
60
50
40
30
20
10

0

1

1

10

100

1000

ID/A

10

100

1000

RDS(ON)=VDS/ID

DC

10us

100us

100ms

10ms

1ms

tp =

VDS/V

1us

0 20 40 60 80 100 120 140 160 180

Tmb / C

ID%

Normalised Current Derating

120
110
100

90
80
70
60
50
40
30
20
10

0

0.001

0.01

0.1

1

10

1E-07 1E-05 1E-03 1E-01 1E+01

t/s

Zth/(K/W)

0

0.02

0.05

0.1

0.2

0.5

1 For maximum permissible repetive avanche current see fig.18.

December 1999 3 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9540-100A
Logic level FET BUK9640-100A

Fig.5. Typical output characteristics, Tj = 25 ˚C

.

ID = f(VDS); parameter V

GS

Fig.6. Typical on-state resistance, Tj = 25 ˚C

.

R

DS(ON)

= f(ID); parameter V

GS

Fig.7. Typical on-state resistance, Tj = 25 ˚C

.

R

DS(ON)

= f(VGS); conditions: ID = 25 A;

Fig.8. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

j

Fig.9. Typical transconductance, Tj = 25 ˚C

.

gfs = f(ID); conditions: VDS = 25 V

Fig.10. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj); ID = 25 A; VGS = 5 V

0

20

40

60

80

100

120

0246810

VDS/V

ID/A

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

5.0

10.0

VGS/V =

0

5

10

15

20

25

30

35

40

012345678910

Gate-source voltage, VGS (V)

Drain current, ID (A)

VDS > ID X RDS(ON)

Tj = 25 C

175 C

20

25

30

35

40

45

50

10 20 30 40 50 60 70

VDS/V

ID/A

3.0

3.2

3.4

3.6

4.0

5.0

0

10

20

30

40

50

60

70

0 10203040

ID/A

gfs/S

26

28

30

32

34

36

38

345678910

VGS/V

RDS(ON) Ohm

0.5

1

1.5

2

2.5

3

-100 -50 0 50 100 150 200
Tmb / degC

a

Rds(on) normalised to 25degC

December 1999 4 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9540-100A
Logic level FET BUK9640-100A

Fig.11. Gate threshold voltage.

V

GS(TO)

= f(Tj); conditions: ID = 1 mA; VDS = V

GS

Fig.12. Sub-threshold drain current.

ID = f(V

GS)

; conditions: Tj = 25 ˚C; VDS = V

GS

Fig.13. Typical capacitances, C

iss

, C

oss

, C

rss

.

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

Fig.14. Typical turn-on gate-charge characteristics.

V

GS

= f(QG); conditions: ID = 25 A; parameter V

DS

Fig.15. Typical reverse diode current.

IF = f(V

SDS

); conditions: V

GS

= 0 V; parameter T

j

Fig.16. Normalised avalanche energy rating.

W

DSS

% = f(Tmb); conditions: ID = 75 A

-100 -50 0 50 100 150 200

0

0.5

1

1.5

2

2.5

Tj / C

VGS(TO) / V

max.

typ.

min.

0

1

2

3

4

5

0 1020304050

QG / nC

VGS / V

VDS = 14V

VDS = 44V

0 0.5 1 1.5 2 2.5 3

1E-05

1E-05

1E-04

1E-03

1E-02

1E-01

Sub-Threshold Conduction

2% typ

98%

0

5

10

15

20

25

30

35

40

45

50

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5

Source-Drain Voltage, VSDS (V)

Source-Drain Diode Current, IF (A)

Tj = 25 C

175 C

VGS = 0 V

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0.01 0.1 1 10 100
VDS/V

Capacitance/nF

Ciss

Coss
Crss

20 40 60 80 100 120 140 160 180

Tmb / C

120
110
100

90
80
70
60
50
40
30
20
10

0

WDSS%

December 1999 5 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9540-100A
Logic level FET BUK9640-100A

Fig.17. Avalanche energy test circuit.

Fig.18. Maximum permissible repetitive avalanche

current(IAV) versus avalanche time(tAV) for unclamped

inductive loads.

Fig.19. Switching test circuit.

L

T.U.T.

VDD

RGS

R 01

VDS

-ID/100

+

-

shunt

VGS

0

RD

T.U.T.

VDD

RG

VDS

+

-

VGS

0

W

DSS

= 0.5 ⋅LI

D

2

⋅BV

DSS

/(BV

DSS−VDD

)

1

10

100

0.001 0.01 0.1 1 10

Avalanche Time, tAV (ms)

I

AV

Tj prior to avanche 150ºC

25ºC

December 1999 6 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9540-100A
Logic level FET BUK9640-100A

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

Fig.20. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

10,3
max

3,7

2,8

3,0

3,0 max

not tinned

1,3

max

(2x)

123

2,4

0,6

4,5
max

5,9

min

15,8

max

1,3

2,54 2,54

0,9 max (3x)

13,5

min

December 1999 7 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9540-100A
Logic level FET BUK9640-100A

MECHANICAL DATA

Fig.21. SOT404 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

UNIT

A

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

A

1

D

1

D

max.

E

eLpHDQc

2.54

2.60

2.20

15.40

14.80

2.90

2.10

11

1.60

1.20

10.30

9.70

4.50

4.10

1.40

1.27

0.85

0.60

0.64

0.46

b

DIMENSIONS (mm are the original dimensions)

SOT404

0 2.5 5 mm

scale

Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)

SOT404

e e

E

b

D

1

H

D

D

Q

L

p

c

A

1

A

13

2

mounting

base

98-12-14
99-06-25

December 1999 8 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9540-100A
Logic level FET BUK9640-100A

MOUNTING INSTRUCTIONS

Dimensions in mm

Fig.22. SOT404 : soldering pattern for surface mounting

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

17.5

11.5

9.0

5.08

3.8

2.0

December 1999 9 Rev 1.000