Datasheet BUK581-60A Datasheet (Philips)

Philips Semiconductors Product Specification

PowerMOS transistor BUK581-60A
Logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
logic level field-effect power
transistor in a plastic envelope V
suitable for surface mount I
applications. P
The device is intended for use in T
automotive and general purpose R

DS

D

tot
j

DS(ON)

switching applications. resistance; VGS = 5 V

PINNING - SOT223 PIN CONFIGURATION SYMBOL

Drain-source voltage 60 V
Drain current (DC) 1.5 A
Total power dissipation 1.5 W
Junction temperature 150 ˚C
Drain-source on-state 0.40 Ω

PIN DESCRIPTION

4

d

1 gate
2 drain
3 source
4 drain (tab)

1

23

g

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

V

DGR

±VGSGate-source voltage - - 15 V
I

D

I

D

I

DM

P

tot

T

stg

T

j

Drain-source voltage - - 60 V
Drain-gate voltage RGS = 20 kΩ -60V

Drain current (DC) T
Drain current (DC) T
Drain current (pulse peak value) T
Total power dissipation T

= 25 ˚C - 1.5 A

amb

= 100 ˚C - 1 A

amb

= 25 ˚C - 6 A

amb

= 25 ˚C - 1.5 W

amb

Storage temperature - - 55 150 ˚C
Junction Temperature - - 150 ˚C

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R
R

th j-sp
th j-amb

From junction to solder point
From junction to ambient Mounted on PCB of Fig.18 - - 85 K/W

1

Mounted on any PCB . - 14 17 K/W

1 Temperature measured at solder joint on drain tab.

October 1995 1 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK581-60A
Logic level FET

STATIC CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

I

DSS

I

DSS

I

GSS

R

DS(ON)

DYNAMIC CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g

fs

C

iss

C

oss

C

rss

t

d on

t

r

t

d off

t

f

Drain-source breakdown VGS = 0 V; ID = 0.25 mA 60 - - V
voltage
Gate threshold voltage VDS = VGS; ID = 0.1 mA 1.0 1.5 2.0 V
Zero gate voltage drain current VDS = 60 V; VGS = 0 V; - 1 10 µA
Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj = 125 ˚C - 0.1 1.0 mA
Gate source leakage current VGS = ±15 V; VDS = 0 V - 10 100 nA
Drain-source on-state VGS = 5 V; ID = 1.5 A - 0.28 0.40 Ω
resistance

Forward transconductance VDS = 25 V; ID = 1.5 A 1.0 2.2 - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 170 300 pF

Output capacitance - 60 100 pF
Feedback capacitance - 25 50 pF

Turn-on delay time VDD = 30 V; ID = 3 A; - 7 10 ns
Turn-on rise time VGS = 5 V; RGS = 50 Ω; - 45 55 ns
Turn-off delay time R
Turn-off fall time - 25 35 ns

= 50 Ω - 1525ns

gen

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V
t

rr

Q

SD

rr

Continuous reverse drain - - - 1.5 A
current
Pulsed reverse drain current - - - 6 A
Diode forward voltage IF = 1.5 A; VGS = 0 V - 0.85 1.1 V

Reverse recovery time IF = 1.5 A; -dIF/dt = 100 A/µs; - 30 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 50 - nC

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

Drain-source non repetitive ID = 1.5 A ; VDD < 25 V - - 10 mJ
unclamped inductive turn-off VGS = 5 V ; RGS = 50 Ω
energy T

= 25 ˚C

amb

October 1995 2 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK581-60A
Logic level FET

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Normalised Power Derating

Tamb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Tamb / C

= f(T

D 25 ˚C

Normalised Current Derating

amb

)

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

D 25 ˚C

= f(T

); conditions: VGS ≥ 5 V

amb

ID / A

10

1

0.1

0.01

RDS(ON) = VDS/ID

DC

0.1 1 10 100
VDS / V

Fig.4. Safe operating area T

ID & I

f(VDS); IDM single pulse; parameter t

DM =

ID / A

5

10

4.5

4

3

2

1

0

0 2 4 6 8 10

5

VDS / V

BUK581-60A

tp = 100 us

1 ms

10 ms

100 ms
1 s

10 s

= 25 ˚C

amb

BUK581-60A

VGS / V = 2.5

p

4

3.5

3

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS); parameter V

GS

.

Zth j-amb / (K/W)

1E+02

D =

0.5

1E+01

1E+00

0.2

0.1

0.05

0.02

t

P

p

D

1E-01

T

1E-02

1E-07 1E-05 1E-03 1E-01 1E+01 1E+03

t / s

Fig.3. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-amb

BUKX81

t

p

D =

T

t

RDS(ON) / Ohm

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1
0

0 2 4

34

135

3.5

ID / A

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

= f(ID); parameter V

DS(ON)

BUK581-60A

4.5
5

VGS / V = 10

.

GS

October 1995 3 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK581-60A
Logic level FET

3

BUK581-60A

150

5

ID / A

5

4

Tj / C = 25

3

2

1

0

0 2 4

1

VGS / V

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

gfs / S

3

2.8

2.6

2.4

2.2
2

1.8

1.6

1.4

1.2
1

0.8

0.6

0.4

0.2
0

0 2 4

1

ID / A

Fig.8. Typical transconductance, Tj = 25 ˚C

BUK581-60A

35

.

gfs = f(ID); conditions: VDS = 25 V

VGS(TO) / V

2

1

0

-60 -40 -20 0 20 40 60 80 100 120 140

max.

typ.

min.

Tj / C

Fig.10. Gate threshold voltage.

V

j

= f(Tj); conditions: ID = 0.1 mA; VDS = V

GS(TO)

ID / A

1E-02

1E-03

1E-04

1E-05

1E-06

1E-07

00.4 0.8 1.2 1.6 2 2.4

SUB-THRESHOLD CONDUCTION SIZE 1

2 %

VGS / V

typ

98 %

GS

Fig.11. Sub-threshold drain current.

ID = f(VGS); conditions: Tj = 25 ˚C; VDS = V

GS

a

1.5

1.0

0.5

0

-60 -40 -20 0 20 40 60 80 100 120 140

Normalised RDS(ON) = f(Tj)

Tj / C

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj); ID = 1.5 A; VGS = 5 V

C / pF

1000

100

10

0 20 40

10 30

VDS / V

Fig.12. Typical capacitances, C

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

BUK581-60A

, C

iss

oss

Ciss

Coss

Crss

, C

rss

.

October 1995 4 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK581-60A
Logic level FET

VGS / V

10

9
8
7
6
5
4
3
2
1
0

0 2 4 6 8 10

QG / nC

BUK581-60A

48 VDS / V =12

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); conditions: ID = 1.5 A; parameter V

GS

IF / A

5

4

3

2

BUK581-60A

25Tj / C = 150

DS

WDSS% Normalised Avalanche Energy

120
110
100

90
80
70
60
50
40
30
20
10

0

20 40 60 80 100 120 140

Tamb/ C

Fig.15. Normalised avalanche energy rating.

W

% = f(T

DSS

); conditions: ID = 1.5 A

amb

+

L

VDS

VGS

0

T.U.T.

-

VDD

-ID/100

1

0

0 1

0.5
VSDS / V

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

1.5

RGS

Fig.16. Avalanche energy test circuit.

W

= 0.5 ⋅LI

j

DSS

D

2

⋅ BV

DSS

/(BV

R 01

shunt

DSS−VDD

)

October 1995 5 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK581-60A
Logic level FET

MOUNTING INSTRUCTIONS

Dimensions in mm.

3.8

min

1.5

min

1.5

min
(3x)

1.5

min

Fig.17. soldering pattern for surface mounting

SOT223.

2.3

4.6

6.3

PRINTED CIRCUIT BOARD

Dimensions in mm.

36

18

60

4.6

9

10

7

50

15

Fig.18. PCB for thermal resistance and power rating

for SOT223.

PCB: FR4 epoxy glass (1.6 mm thick), copper

laminate (35 µm thick).

4.5

October 1995 6 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK581-60A
Logic level FET

MECHANICAL DATA

Dimensions in mm
Net Mass: 0.11 g

16

max

1.8

max

0.32

0.24

0.10

0.02

10
max

13

1.05

0.85

6.7

6.3

3.1

2.9

4

1

2.3

23

0.80

0.60

4.6

B

A

7.3

6.7

M

B

0.1

3.7

3.3

(4x)

Fig.19. SOT223 surface mounting package.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to surface mounting instructions for SOT223 envelope.

3. Epoxy meets UL94 V0 at 1/8".

AM0.2

October 1995 7 Rev 1.100

Philips Semiconductors Product Specification

PowerMOS transistor BUK581-60A
Logic level FET

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

October 1995 8 Rev 1.100