Datasheet BUK554-60H Datasheet (Philips)

Page 1
Philips Semiconductors Product specification
PowerMOS transistor BUK554-60H Logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT level field-effectpower transistor in a plastic envelope V The device is intended for use in I automotive and general purpose P switching applications. T
D
R
DS
tot j
DS(ON)

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION
tab
d
1 gate 2 drain
g
3 source
tab drain
123
s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
DS
V
DGR
±VGSGate-source voltage - - 15 V ±V
GSM
I
D
I
D
I
DM
P
tot
T
stg
T
j
Drain-source voltage - - 60 V Drain-gate voltage RGS = 20 k -60V
Non-repetitive gate-source tp 50 µs - 20 V voltage Drain current (DC) Tmb = 25 ˚C - 39 A Drain current (DC) Tmb = 100 ˚C - 28 A Drain current (pulse peak value) Tmb = 25 ˚C - 156 A Total power dissipation Tmb = 25 ˚C - 125 W Storage temperature - - 55 175 ˚C Junction temperature - - 175 ˚C

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
R
th j-a
August 1996 1 Rev 1.000
Thermal resistance junction to - 1.2 K/W mounting base Thermal resistance junction to 60 - K/W ambient
Page 2
Philips Semiconductors Product specification
PowerMOS transistor BUK554-60H Logic level FET

STATIC CHARACTERISTICS

Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GS(TO)
I
DSS
I
DSS
I
GSS
R
DS(ON)

DYNAMIC CHARACTERISTICS

Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
g
fs
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
Drain-source breakdown VGS = 0 V; ID = 0.25 mA 60 - - V voltage Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj = 25 ˚C - 1 10 µA Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj =125 ˚C - 0.1 1.0 mA Gate source leakage current VGS = ±15 V; VDS = 0 V - 10 100 nA Drain-source on-state VGS = 5 V; ID = 20 A - 35 42 m resistance
Forward transconductance VDS = 25 V; ID = 20 A 10 18 - S Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1100 1750 pF
Output capacitance - 420 600 pF Feedback capacitance - 160 275 pF
Turn-on delay time VDD = 30 V; ID = 3 A; - 25 40 ns Turn-on rise time VGS = 5 V; RGS = 50 ; - 110 150 ns Turn-off delay time R
= 50 - 150 220 ns
gen
Turn-off fall time - 100 145 ns Internal drain inductance Measured from contact screw on - 3.5 - nH
tab to centre of die
Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
Internal source inductance Measured from source lead 6 mm - 7.5 - nH
from package to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DR
Continuous reverse drain - - - 39 A current
I
DRM
V t
rr
Q
SD
rr
Pulsed reverse drain current - - - 156 A Diode forward voltage IF = 39 A ; VGS = 0 V - 0.95 2.0 V
Reverse recovery time IF = 39 A; -dIF/dt = 100 A/µs; - 60 - ns Reverse recovery charge VGS = 0 V; VR = 30 V - 0.30 - µC

AVALANCHE LIMITING VALUE

Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
W
DSS
August 1996 2 Rev 1.000
Drain-source non-repetitive ID = 39 A ; VDD 25 V ; - - 90 mJ unclamped inductive turn-off VGS = 5 V ; RGS = 50 energy
Page 3
Philips Semiconductors Product specification
PowerMOS transistor BUK554-60H Logic level FET
PD%
120 110 100
90 80 70 60 50 40 30 20 10
0
0 20 40 60 80 100 120 140 160 180
Normalised Power Derating
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/P
ID%
120 110 100
90 80 70 60 50 40 30 20 10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
= f(Tmb)
D 25 ˚C
Normalised Current Derating
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
= f(Tmb); conditions: VGS ≥ 5 V
D 25 ˚C
Zth(j-mb) K/W
10
D =
1
0.5
0.2
0.1
0.1
0.05
0.02
tp / sec
P
D
0.01 0
0.001 1E-07 1E-05 1E-03 1E-01 1E+01
p
t
T
BUK464-60H
p
t
D =
T
t
Fig.4. Transient thermal impedance.
Z
= f(t); parameter D = tp/T
th j-mb
ID / A
100
80
60
40
20
0
012345
VGS / V =
Fig.5. Typical output characteristics, Tj = 25 ˚C
ID = f(VDS); parameter V
BUK564-60H
810
6
5
4.5 4
3.5 3
2.5
VDS / V
.
GS
1000
100
ID / A
RDS(ON) = VDS/ID
BUK564-60H
tp =
10 us
100 us
RDS(ON) / Ohm
0.1
2.5 3 3.5 4 4.5
0.08
0.06
BUK564-60H
5
VGS / V =
6
8
0.04
10
DC
1
1 10 100
VDS / V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter t
1 ms 10 ms
100 ms
10
0.02
0
0 20 40 60 80 100
ID / A
Fig.6. Typical on-state resistance, Tj = 25 ˚C
R
p
= f(ID); parameter V
DS(ON)
GS
.
August 1996 3 Rev 1.000
Page 4
Philips Semiconductors Product specification
PowerMOS transistor BUK554-60H Logic level FET
ID / A
80
60
40
20
0
0246810
BUK564-60H
Tj / C = -40 150
25
VGS / V
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter T
gfs / S
20
10
BUK564-60H
-40
25
Tj / C = 150
j
VGS(TO) / V
2
1
0
-60 -20 20 60 100 140 180
max.
typ.
min.
Tj / C
Fig.10. Gate threshold voltage.
V
= f(Tj); conditions: ID = 1 mA; VDS = V
GS(TO)
1E-01
1E-02
1E-03
1E-04
ID / A
SUB-THRESHOLD CONDUCTION
2 %
typ
98 %
GS
0
0 20406080
Fig.8. Typical transconductance, Tj = 25 ˚C
ID / A
.
gfs = f(ID); conditions: VDS = 25 V
a
2.0
1.5
1.0
0.5
0
-60 -20 20 60 100 140 180
Normalised RDS(ON) = f(Tj)
Tj / C
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)/RDS(ON)25 ˚C
= f(Tj); ID = 20 A; VGS = 5 V
1E-05
1E-06
0 1 2 3 4
VGS / V
Fig.11. Sub-threshold drain current.
ID = f(V
10000
1000
100
02040
Fig.12. Typical capacitances, C
; conditions: Tj = 25 ˚C; VDS = V
GS)
C / pF
BUK564-60H
VDS / V
GS
Ciss
Coss
Crss
, C
, C
iss
oss
rss
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
.
August 1996 4 Rev 1.000
Page 5
Philips Semiconductors Product specification
PowerMOS transistor BUK554-60H Logic level FET
VGS / V
12
10
8
6
4
2
0
0 10203040
BUK564-60H
VDS / = 12
48
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
V
= f(QG); conditions: ID = 39 A; parameter V
GS
IF / A
100
80
60
40
20
0
012
Tj / C = 150 -40
BUK564-60H
25
VSDS / V
DS
Fig.14. Typical reverse diode current.
IF = f(V
); conditions: V
SDS
= 0 V; parameter T
GS
j
WDSS%
120 110 100
90 80 70 60 50 40 30 20 10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.15. Normalised avalanche energy rating.
W
% = f(Tmb); conditions: ID = 39 A
DSS
+
L
VDS
R 01
shunt
DSS−VDD
-
)
VGS
0
RGS
T.U.T.
Fig.16. Avalanche energy test circuit.
W
= 0.5 LI
DSS
2
D
BV
DSS
/(BV
VDD
-ID/100
August 1996 5 Rev 1.000
Page 6
Philips Semiconductors Product specification
PowerMOS transistor BUK554-60H Logic level FET

MECHANICAL DATA

Dimensions in mm Net Mass: 2 g
10,3 max
1,3
3,7
4,5 max
3,0 max
not tinned
1,3
max
(2x)
123
2,54 2,54
2,8
3,0
13,5
min
0,9 max (3x)
5,9
min
15,8
max
0,6
2,4
Fig.17. TO220AB; pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide.
2. Refer to mounting instructions for TO220 envelopes.
3. Epoxy meets UL94 V0 at 1/8".
August 1996 6 Rev 1.000
Page 7
Philips Semiconductors Product specification
PowerMOS transistor BUK554-60H Logic level FET

DEFINITIONS

Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1996 7 Rev 1.000
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