Datasheet BUK553-48C Datasheet (Philips)

Philips Semiconductors Product specification

PowerMOS transistor BUK553-48C
Voltage clamped logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

Protected N-channel enhancement SYMBOL PARAMETER MIN. TYP. MAX. UNIT
mode logic level field-effect power
transistor in a plastic envelope. V
The device is intended for use in I
automotive applications. It has P
built-in zenerdiodes providing active T
drain voltage clamping. W

(CL)DSR

D

tot
j

DSRR

R

DS(ON)

PINNING - TO220AB PIN CONFIGURATION SYMBOL

Drain-source clamp voltage 40 48 58 V
Drain current (DC) 21 A
Total power dissipation 75 W
Junction temperature 175 ˚C
Repetitive clamped turn off 50 mJ
energy; Tj = 150˚C
Drain-source on-state 85 mΩ
resistance; VGS = 5 V

PIN DESCRIPTION

tab

d

1 gate
2 drain
3 source

tab drain

123

g

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
±V
I

D

I

D

I

DM

P
T
T

DS
DG

GS

tot
stg
j

Drain-source voltage continuous - 30 V
Drain-gate voltage continuous - 30 V
Gate-source voltage - - 15 V
Drain current (DC) Tmb = 25 ˚C - 21 A
Drain current (DC) Tmb = 100 ˚C - 15 A
Drain current (pulse peak Tmb = 25 ˚C - 84 A
value)
Total power dissipation Tmb = 25 ˚C - 75 W
Storage temperature - - 55 175 ˚C
Junction Temperature - - 55 175 ˚C

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

th j-mb

R

th j-a

August 1994 1 Rev 1.000

Thermal resistance junction to with heatsink compound - - 2 K/W
heatsink
Thermal resistance junction to - 60 - K/W
ambient

Philips Semiconductors Product specification

PowerMOS transistor BUK553-48C

Voltage clamped logic level FET

STATIC CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DG

V

GS(TO)

V

GS(ON)

I

DSS

I

GSS

R

DS(ON)

DYNAMIC CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(CL)DSR

g

fs

C

iss

C

oss

C

rss

t

d on

t

r

t

d off

t

f

L

d

L

s

Drain-gate zener voltage 0.2 < -IG < 0.4 mA; 38 45 54 V

-55˚C < Tj < 150˚C
Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V
Gate voltage VDS = 10 V; ID = 10 A; 2.0 3.1 4.0 V

-55˚C < Tj < 150˚C
Zero gate voltage drain current VDS = 30 V; VGS = 0 V; Tj =150 ˚C - 0.01 1.0 mA
Gate source leakage current VGS = ±15 V; VDS = 0 V; Tj =150 ˚C - 0.1 10 µA
Drain-source on-state VGS = 5 V; ID = 10 A - 65 85 mΩ
resistance

Drain source clamp voltage RG = 10 kΩ; ID = 10 A; 40 48 58 V
(peak value) -55 < Tj < 150˚C; Inductive load.

Forward transconductance VDS = 25 V; ID = 10 A 7 12 - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 550 825 pF

Output capacitance - 240 350 pF
Feedback capacitance - 100 160 pF

Turn-on delay time VDD = 12 V; ID = 5 A; - 3.5 - µs
Turn-on rise time VGS = 5 V; RG = 10 kΩ; - 22 - µs
Turn-off delay time - 16 - µs
Turn-off fall time - 18 - µs

Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH

from package to centre of die

Internal source inductance Measured from source lead 6 mm - 7.5 - nH

from package to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V

SD

August 1994 2 Rev 1.000

Continuous reverse drain - - - 21 A
current
Pulsed reverse drain current - - - 84 A
Diode forward voltage IF = 21 A ; VGS = 0 V - 1.3 1.7 V

Philips Semiconductors Product specification

PowerMOS transistor BUK553-48C

Voltage clamped logic level FET

CLAMPED ENERGY LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

W

W

DSRS

DSRR

Non-repetitive drain-source Tj = 25˚C prior to clamping; - 200 mJ
clamped inductive turn off ID = 10 A; VDD < 16 V; VGS = 5 V;
energy RG = 10 kΩ; inductive load

Drain-source repetitive clamped Tj = 150˚C prior to clamping; - 50 mJ
inductive turn off energy ID = 10 A; VDD < 16 V; VGS = 5 V;

RG = 10 kΩ; inductive load

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID / A

100

RDS(ON) = VDS/ID

10

DC

Self-clamped

1

1 100

10

VDS / V

D 25 ˚C

= f(Tmb)

BUK553-48C

tp =

10 us

100 us

1 ms

10 ms
100 ms

Fig.2. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Current Derating

Tmb / C

Fig.3. Normalised continuous drain current.

ID% = 100⋅ID/I

Zth j-mb / (K/W)

1E+01

1E+00

1E-01

1E-02

0.5

0.2

0.1

0.05

0.02

0

1E-07 1E-05 1E-03 1E-01 1E+01

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

t

P

p

D

T

t / s

ZTHX53

t

D =

T

p

t

Fig.4. Transient thermal impedance.

Z

p

= f(t); parameter D = tp/T

th j-mb

August 1994 3 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistor BUK553-48C
Voltage clamped logic level FET

ID / A

40

10

30

20

10

0

0246810

VDS / V

BUK5Y3-48C

VGS / V = 5

4.5

4

3.5

3

2.5

Fig.5. Typical output characteristics, Tj = 25 ˚C

RDS(ON) / Ohm

0.5

0.4

0.3

0.2

ID = f(VDS); parameter V

3.532.5

VGS / V = 4

GS

BUK5Y3-48C

4.5

5

ID / A

40

30

20

10

0

01234567

.

Fig.8. Typical transfer characteristics.

VGS / V

ID = f(VGS) ; conditions: VDS = 25 V

gfs / S

20

15

10

BUK5Y3-48C

Tmb / degC =

150

25

-55

.

BUK5Y3-48C

0.1

0

0 10203040

VDS / V

10

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

= f(ID); parameter V

DS(ON)

V(CL)DSR / V

51
50
49
48
47
46
45
44
43

024681012

ID / A

GS

BUK5Y3-48C

Tmb / degC =

150

25

-55

Fig.7. Typical clamping voltage

V

= f(ID) ; conditions: RG = 10 k

(CL)DSR

Ω

5

0

0 10203040

.

Fig.9. Typical transconductance

Id / A

Tmb / degC =

150

25

-55

.

gfs = f(ID); conditions: VDS = 25 V

V(CL)DSR / V

58

56

54

52

50

48

46

44

11020

RG / kOhm

52

BUK5Y3-48C

Tmb / degC =

150

25

-55

Fig.10. Typical clamping voltgage

V

= f(RG) ; conditions: ID = 10 A

(CL)DSR

.

August 1994 4 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistor BUK553-48C
Voltage clamped logic level FET

a

2.0

1.5

1.0

0.5

0

-60 -20 20 60 100 140 180

Normalised RDS(ON) = f(Tj)

Tj / C

Fig.11. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

ID / A

1E-01

1E-02

1E-03

1E-04

= f(Tj); ID = 10 A; VGS = 5 V

SUB-THRESHOLD CONDUCTION

2 %

typ

98 %

VGS(TO) / V

2

1

0

-60 -20 20 60 100 140 180

max.

typ.

min.

Tj / C

Fig.14. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

IS / A

40

30

20

Tmb / degC =

150

25

-55

BUK5Y3-48C

GS

1E-05

1E-06

0 0.4 0.8 1.2 1.6 2 2.4

VGS / V

Fig.12. Sub-threshold drain current.

ID = f(V

2000

1000

500

200

100

50

0.01 0.1 1 10 100

Fig.13. Typical capacitances, C

; conditions: Tj = 25 ˚C; VDS = V

GS)

C / pF

VDS / V

BUK5Y3-48C

, C

iss

oss

Ciss

Coss

Crss

, C

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

GS

rss

10

0

0 0.5 1 1.5

VSDS / V

Fig.15. Typical reverse diode current.

IF = f(V

VGS / V

7

6

5

4

3

2

1

0

0 5 10 15 20

.

Fig.16. Typical turn-on gate-charge characteristics.

V

GS

); conditions: V

SDS

QG / nC

= 0 V; parameter T

GS

BUK5Y3-48C

VDD / V = 12

30

= f(QG); conditions: ID = 10 A; parameter V

j

DS

August 1994 5 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistor BUK553-48C
Voltage clamped logic level FET

t

: adjust for correct Ic

p

V

GE

Fig.17. Inductive clamping test circuit.

V

DD

Load

D.U.T.

R

G

Id measure

I,V

5 V

P,E

I

D

PDS = ID x VDS

E =

PDS dt

V

(CL)DSR

V

DS

V

GS

t

W

DSR

0V

0R1

Fig.18.

Typical Inductive Clamping waveforms

t

August 1994 6 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistor BUK553-48C

Voltage clamped logic level FET

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

10,3
max

1,3

3,7

4,5
max

3,0 max

not tinned

1,3

max

(2x)

123

2,54 2,54

2,8

3,0

13,5

min

0,9 max (3x)

5,9

min

15,8

max

0,6

2,4

Fig.19. TO220AB; pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for TO220 envelopes.

3. Epoxy meets UL94 V0 at 1/8".

August 1994 7 Rev 1.000

Philips Semiconductors Product specification

PowerMOS transistor BUK553-48C

Voltage clamped logic level FET

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

August 1994 8 Rev 1.000

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