Datasheet BUK102-50GS Datasheet (Philips)

Page 1
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
DESCRIPTION QUICK REFERENCE DATA
Monolithic temperature and SYMBOL PARAMETER MAX. UNIT overload protected power MOSFET in a 3 pin plastic envelope, intended V
DS
as a general purpose switch for I
D
automotive systems and other P
D
Total power dissipation 125 W
applications. T
j
Continuous junction temperature 150 ˚C
R
DS(ON)
Drain-source on-state resistance 28 m
APPLICATIONS V
IS
= 10 V
General controller for driving
lamps motors solenoids heaters
FEATURES FUNCTIONAL BLOCK DIAGRAM
Vertical power DMOS output stage Low on-state resistance Overload protection against over temperature Overload protection against short circuit load Latched overload protection reset by input 10 V input level Low threshold voltage also allows 5 V control Control of power MOSFET and supply of overload protection circuits derived from input ESD protection on input pin Overvoltage clamping for turn off of inductive loads
Fig.1. Elements of the TOPFET.
PINNING - TO220AB PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 input 2 drain 3 source
tab drain
POWER MOSFET
DRAIN
SOURCE
INPUT
O/V
CLAMP
LOGIC AND
PROTECTION
RIG
123
tab
P
D
S
I
TOPFET
January 1993 1 Rev 1.200
Page 2
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DSS
Continuous off-state drain source VIS = 0 V - 50 V voltage
1
V
IS
Continuous input voltage - 0 11 V
I
D
Continuous drain current T
mb ≤
25 ˚C; VIS = 10 V - 50 A
I
D
Continuous drain current T
mb ≤
100 ˚C; VIS = 10 V - 31 A
I
DRM
Repetitive peak on-state drain current Tmb 25 ˚C; VIS = 10 V - 200 A
P
D
Total power dissipation Tmb 25 ˚C - 125 W
T
stg
Storage temperature - -55 150 ˚C
T
j
Continuous junction temperature
2
normal operation - 150 ˚C
T
sold
Lead temperature during soldering - 250 ˚C
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
ISP
Protection supply voltage
3
for valid protection 5 - V
Over temperature protection
V
DDP(T)
Protected drain source supply voltage VIS = 10 V - 50 V
Short circuit load protection
V
DDP(P)
Protected drain source supply voltage4VIS = 10 V - 16 V
VIS = 5 V - 24 V
P
DSM
Instantaneous overload dissipation Tmb = 25 ˚C - 2.1 kW
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
I
DROM
Repetitive peak clamping current VIS = 0 V - 50 A
E
DSM
Non-repetitive clamping energy Tmb 25 ˚C; IDM = 25 A; - 1 J
VDD 25 V; inductive load
E
DRM
Repetitive clamping energy Tmb 85 ˚C; IDM = 16 A; - 80 mJ
VDD 20 V; f = 250 Hz
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
C
Electrostatic discharge capacitor Human body model; - 2 kV voltage C = 250 pF; R = 1.5 k
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 A higher Tj is allowed as an overload condition but at the threshold T
j(TO)
the over temperature trip operates to protect the switch.
3 The input voltage for which the overload protection circuits are functional. 4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed V
DDP(P)
maximum.
For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.
January 1993 2 Rev 1.200
Page 3
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Thermal resistance
R
th j-mb
Junction to mounting base - - 0.8 1.0 K/W
R
th j-a
Junction to ambient in free air - 60 - K/W
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(CL)DSS
Drain-source clamping voltage VIS = 0 V; ID = 10 mA 50 - - V
V
(CL)DSS
Drain-source clamping voltage VIS = 0 V; IDM = 2 A; tp 300 µs; - - 70 V
δ 0.01
I
DSS
Zero input voltage drain current VDS = 12 V; VIS = 0 V - 0.5 10 µA
I
DSS
Zero input voltage drain current VDS = 50 V; VIS = 0 V - 1 20 µA
I
DSS
Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 ˚C - 10 100 µA
R
DS(ON)
Drain-source on-state IDM = 25 A; VIS = 10 V - 22 28 m resistance tp 300 µs; δ 0.01 VIS = 5 V - 30 35 m
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Short circuit load protection1Tmb = 25 ˚C; L 10 µH
E
DS(TO)
Overload threshold energy VDD = 13 V; VIS = 10 V - 1.1 - J
t
d sc
Response time VDD = 13 V; VIS = 10 V - 0.8 - ms
Over temperature protection
T
j(TO)
Threshold junction temperature VIS = 10 V; from ID 2 A
2
150 - - ˚C
INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
IS(TO)
Input threshold voltage VDS = 5 V; ID = 1 mA 1.0 1.5 2.0 V
I
IS
Input supply current VIS = 10 V; normal operation - 0.4 1.0 mA
V
ISR
Protection reset voltage
3
2.0 2.6 3.5 V
V
ISR
Protection reset voltage Tj = 150 ˚C 1.0 - -
I
ISL
Input supply current VIS = 10 V; protection latched 2 6 20 mA
V
(BR)IS
Input clamp voltage II = 10 mA 11 13 - V
R
IG
Input series resistance to gate of power MOSFET - 1.5 - k
1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
P
DSM
, which is always the case when VDS is less than V
DSP
maximum. Refer to OVERLOAD PROTECTION LIMITING VALUES.
2 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum I
D
ensures this condition.
3 The input voltage below which the overload protection circuits will be reset.
January 1993 3 Rev 1.200
Page 4
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
TRANSFER CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
g
fs
Forward transconductance VDS = 10 V; IDM = 25 A tp 300 µs; 17 28 - S
δ 0.01
I
D(SC)
Drain current
1
VDS = 13 V; VIS = 10 V - 150 - A
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C. RI = 50 . Refer to waveform figures and test circuits.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
t
d on
Turn-on delay time VDD = 13 V; VIS = 10 V - 1.5 - µs
t
r
Rise time resistive load RL = 1.1 - 5.5 - µs
t
d off
Turn-off delay time VDD = 13 V; VIS = 0 V - 13 - µs
t
f
Fall time resistive load RL = 1.1 -9-µs
t
d on
Turn-on delay time VDD = 13 V; VIS = 10 V - 1.5 - µs
t
r
Rise time inductive load IDM = 11 A - 1.3 - µs
t
d off
Turn-off delay time VDD = 13 V; VIS = 0 V - 18 - µs
t
f
Fall time inductive load IDM = 11 A - 1.4 - µs
REVERSE DIODE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
I
S
Continuous forward current Tmb 25 ˚C; VIS = 0 V - 50 A
REVERSE DIODE CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
SDS
Forward voltage IS = 50 A; VIS = 0 V; tp = 300 µs - 1.0 1.5 V
t
rr
Reverse recovery time not applicable
2
----
ENVELOPE CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
L
d
Internal drain inductance Measured from contact screw on - 3.5 - nH
tab to centre of die
L
d
Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
L
s
Internal source inductance Measured from source lead 6 mm - 7.5 - nH
from package to source bond pad
1 During overload before short circuit load protection operates. 2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
January 1993 4 Rev 1.200
Page 5
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
Fig.2. Normalised limiting power dissipation.
PD% = 100⋅PD/PD(25 ˚C) = f(Tmb)
Fig.3. Normalised continuous drain current.
ID% = 100⋅ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V
Fig.4. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter t
p
Fig.5. Transient thermal impedance.
Zth
j-mb
= f(t); parameter D = tp/T
Fig.6. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs & tp < t
d sc
Fig.7. Typical on-state characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs
0 20 40 60 80 100 120 140
Tmb / C
PD%
Normalised Power Derating
120 110 100
90 80 70 60 50 40 30 20 10
0
BUK102-50GS
1E-07 1E-05 1E-03 1E-01 1E+01
t / s
Zth / (K/W)
10
1
0.1
0.01
0.001
0
0.5
0.2
0.1
0.05
0.02
D =
D =
t
p
t
p
T
T
P
t
D
0 20 40 60 80 100 120 140
Tmb / C
ID%
Normalised Current Derating
120 110 100
90 80 70 60 50 40 30 20 10
0
0 4 8 12 16 20 24 28 32
BUK102-50GS
VDS / V
ID / A
180 160 140 120 100
80 60 40 20
0
8
9
11
10
7
6
5
4
3
VIS / V =
1 100
VDS / V
1000
100
10
1
BUK102-50GS
10
ID & IDM / A
Overload protection characteristics not shown
DC
100 us
1 ms
10 ms
100 ms
10 us
tp =
RDS(ON) = VDS/ID
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
BUK102-50GS
VDS / V
ID / A
80 70 60 50 40 30 20 10
0
3
4
5
6
10
9
8
7
VIS / V =
January 1993 5 Rev 1.200
Page 6
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
Fig.8. Typical on-state resistance, Tj = 25 ˚C.
R
DS(ON)
= f(ID); parameter VIS; tp = 250 µs
Fig.9. Typical transfer characteristics, Tj = 25 ˚C.
ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 µs
Fig.10. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 10 V; tp = 250 µs
Fig.11. Normalised drain-source on-state resistance.
a = R
DS(ON)/RDS(ON)
25 ˚C = f(Tj); ID = 25 A; VIS = 10 V
Fig.12. Typical overload protection characteristics.
t
d sc
= f(PDS); conditions: VIS ≥ 5 V; Tj = 25 ˚C.
Fig.13. Normalised limiting overload dissipation.
P
DSM
% =100⋅P
DSM/PDSM
(25 ˚C) = f(Tmb)
0 20 40 60 80 100 120 140 160
BUK102-50GS
ID / A
RDSON / Ohm
0.06
0.05
0.04
0.03
0.02
0.01
0
VIS / V = 5 6 7 8 109
-60 -40 -20 0 20 40 60 80 100 120 140 Tj / C
a
Normalised RDS(ON) = f(Tj)
1.5
1.0
0.5
0
0 2 4 6 8 10 12
BUK102-50GS
VIS / V
ID / A
160 140 120 100
80 60 40 20
0
0.1 1 10 PDS / kW
BUK102-50GS
10
1
0.1
td sc / ms
PDSM
0 100 150
BUK102-50GS
ID / A
gfs / S
30
20
10
0
50
-60 -40 -20 0 20 40 60 80 100 120 140 Tmb / C
PDSM%
120
100
80
60
40
20
0
January 1993 6 Rev 1.200
Page 7
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
Fig.14. Typical overload protection characteristics.
Conditions: VDD = 13 V; VIS = 10 V; SC load = 30 m
Fig.15. Typical clamping characteristics, 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs
Fig.16. Input threshold voltage.
V
IS(TO)
= f(Tj); conditions: ID = 1 mA; VDS = 5 V
Fig.17. Typical DC input characteristics, Tj = 25 ˚C.
IIS = f(VIS); normal operation
Fig.18. Typical DC input characteristics, Tj = 25 ˚C.
I
ISL
= f(VIS); overload protection operated ⇒ ID = 0 A
Fig.19. Typical reverse diode current, Tj = 25 ˚C.
IS = f(V
SDS
); conditions: VIS = 0 V; tp = 250 µs
-60 -20 20 60 100 140 180 220 Tmb / C
BUK102-50GS
1.5
1.0
0.5
0
Energy & Time
Time / ms
Energy / J
Tj(TO)
0 2 4 6 8 10 12 14
BUK102-50GS
VIS / V
IIS / mA
2.0
1.5
1.0
0.5
0
50 60 70
VDS / V
ID / A
BUK102-50GS
50
40
30
20
10
0
typ.
BUK102-50GS
0 2 4 6 8 10 12 14
0
2
4
6
8
10
VIS / V
IIS / mA
RESET
PROTECTION LATCHED
NORMAL
-60 -40 -20 0 20 40 60 80 100 120 140 Tj / C
VIS(TO) / V
2
1
0
max.
typ.
min.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
BUK102-50GS
VSD / V
IS / A
200
150
100
50
0
January 1993 7 Rev 1.200
Page 8
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
Fig.20. Test circuit for resistive load switching times.
Fig.21. Typical switching waveforms, resistive load.
VDD = 13 V; RL = 1.1 Ω; RI = 50 Ω, Tj = 25 ˚C.
Fig.22. Typical switching waveforms, resistive load.
VDD = 13 V; RL = 1.1 Ω; RI = 50 Ω, Tj = 25 ˚C.
Fig.23. Test circuit for inductive load switching times.
Fig.24. Typical switching waveforms, inductive load.
VDD = 13 V; ID = 11 A; RI = 50 Ω, Tj = 25 ˚C.
Fig.25. Typical switching waveforms, inductive load.
VDD = 13 V; ID = 11 A; RI = 50 Ω, Tj = 25 ˚C.
VDD
D.U.T.
R
0V
0R1
I
VIS
ID measure
D
S
I
TOPFET
P
RL
: adjust for correct ID
VDD = VCL
LD
D.U.T.
R
0V
t
p
0R1
I
VIS
ID measure
D
S
I
TOPFET
P
0 10 20
RESISTIVE TURN-ON
time / us
BUK102-50GS
15
10
5
0
VDS / V
VIS / V
ID / A
10%
10%
90%
td on
tr
0 10 20
INDUCTIVE TURN-ON
time / us
BUK102-50GS
10
5
0
VDS / V
VIS / V
ID / A
90%
10%
10%
tr
td on
0 20 40
RESISTIVE TURN-OFF
time / us
BUK102-50GS
15
10
5
0
10 30 50
VDS / V
ID / A
VIS / V
90%
90%
10%
td off
tf
0 20 40
INDUCTIVE TURN-OFF
time / us
BUK102-50GS
10
5
0
10 30 50
VIS / V
ID / A
VDS / V
90%
90%
10%
tf
td off
January 1993 8 Rev 1.200
Page 9
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
Fig.26. Normalised limiting clamping energy.
E
DSM
% = f(Tmb); conditions: ID = 25 A; VIS = 10 V
Fig.27. Clamping energy test circuit, RIS = 50 Ω.
Fig.28. Typical off-state leakage current.
I
DSS
= f(Tj); Conditions: VDS = 40 V; IIS = 0 V.
Fig.29. Normalised input current (normal operation).
IIS/IIS25 ˚C = f(Tj); VIS = 10 V
Fig.30. Normalised input current (protection latched).
I
ISL/IISL
25 ˚C = f(Tj); VIS = 10 V
Fig.31. Maximum drain source supply voltage for
SC load protection. V
DDP(P)
= f(VIS); Tmb ≤ 150 ˚C
0 20 40 60 80 100 120 140
Tmb / C
EDSM%
120 110 100
90 80 70 60 50 40 30 20 10
0
-60 -20 20 60 100 140 180 Tj / C
Iiso normalised to 25 C
1.5
1
0.5
-60 -20 20 60 100 140 180 Tj / C
Iisl normalised to 25 C
1.5
1
0.5
L
D.U.T.
VDD
RIS
R 01
VDS
-ID/100
+
-
shunt
VIS
0
P
D
S
I
TOPFET
ID
0
VDS
0
VDD
V(CL)DSS
Schottky
E
DSM
= 0.5 LI
D
2
V
(CL)DSS
/(V
(CL)DSSVDD
)
0 20 40 60 80 100 120 140
Tj / C
Idss
1 mA
100 uA
10 uA
1 uA
100 nA
typ.
0 2 4 6 8 10
VIS / V
VDDP(P) / V
BUK102-50GS
50
40
30
20
10
0
max
January 1993 9 Rev 1.200
Page 10
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
MECHANICAL DATA
Dimensions in mm Net Mass: 2 g
Fig.32. TO220AB; pin 2 connected to mounting base.
Notes
1. Refer to mounting instructions for TO220 envelopes.
2. Epoxy meets UL94 V0 at 1/8".
10,3 max
3,7
2,8
3,0
3,0 max
not tinned
1,3
max
(2x)
123
2,4
0,6
4,5 max
5,9
min
15,8
max
1,3
2,54 2,54
0,9 max (3x)
13,5
min
January 1993 10 Rev 1.200
Page 11
Philips Semiconductors Product specification
PowerMOS transistor BUK102-50GS TOPFET
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
January 1993 11 Rev 1.200
Loading...