The BU8241F, BU8241FS, BU8242F, and BU8244F are ICs developed for use with cordless telephones, and are
equipped with switching and mixing functions. In addition, these ICs are provided with an internal power save function
which enables the circuit to be run on line current if the power supply fails, by connecting a switch between the circuit
and a new handset, reducing line current consumption. A series of these ICs is also under development, based on the
number of circuits.
Communication ICsBU8241F / BU8241FS / BU8242F / BU8244F
Pin descriptions
Input/output circuits
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Communication ICsBU8241F / BU8241FS / BU8242F / BU8244F
Circuit operation
Sections (1) to (3) below describe operation using the
BU8241F and BU8241FS as examples.
(1) Analog signals pass through an input amplifier and
are supplied to eight switches.
The analog input signals are turned on and off by the
switches and can thus be directed to any desired output
amplifier. Using mixing resistors connected to the outputs of the switches, and feedback resistors, each output
amplifier can output a signal that is a mix of up to eight
input signals.
(2) The switch states are set using a 64-bit shift register
and data latch.
The shift register reads the data at the rising edge of the
shift clock, and stores it until the next data is read at the
rising edge of the next shift clock.
After the 64 data bits have been read, supply of the rising
edge of the clock is stopped, the LATCH pin is set to
HIGH, and the switches are set. (See Figure 2 for the timing waveform.)
To change a switch setting, new setting data and shift
clocks must be supplied for 64 bits of data, and the
LATCH pin set to HIGH. If the LATCH pin is set to HIGH
before 64 shift clocks have been supplied, or after more
than 64 have been supplied, the switches cannot be set
properly. (See Table 1 for the logic of switch settings.)
Table.1 Switch Sn stage (Note 6)
(3) The power save mode is set as long as the PS pin is
kept HIGH. (See T able 2 for the power save setting logic.)
In the power save mode, the following are fixed : IN1
OUT1 (S1 = ON) and IN2 OUT2 (S10 = ON). (The other 62 switches are off.) In addition, the line current is reduced. When the PS pin goes from HIGH to LOW, the IC
state switches from the power save mode back to normal
operation. At that point, the state of the switch remains
in the power save mode (only S1 and S10 are on). (See
Figure 3 for the timing waveform in the power save
mode.)
(4) With the BU8242F, of the 64 data bits, the following
should be input at LOW level : D
35, D36, D43, D44, D51, D52, D59, and D60.
D
3, D4, D11, D12, D17 to D32,
(5) With the BU8244F, DIN is 16 bits.
The ON path in the power save mode is the same for the
BU8241F and BU8241FS, but the pertinent switches are
S1 and S6.
Table.2 Power save setting theory
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Communication ICsBU8241F / BU8241FS / BU8242F / BU8244F
Application example
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Communication ICsBU8241F / BU8241FS / BU8242F / BU8244F
Selecting attached components
1) Components related to power supply and bias
3) Components related to output pins
C602: V
C603: VB decoupling capacitor; normally 10µF
2) Components related to input pins
C605 to C612: DC cutoff capacitor. A value should be
R605 to R612: Resistor which sets the input level. This
DD bias capacitor; normally 10µF
selected which does not attenuate voice
signals in the high band (300 Hz ).
should normally be left open.
The constants shown in Figure 8 are set
to match the oscillator output impedance.
C613 to C620: DC cutoff capacitor. A value should be
selected which does not attenuate voice
signals in the high band (300 Hz ).
R613 to R620: Output load resistors. This should nor-
mally be left open.
If using R615 to R620, select values that
result in a total input impedance of 10kΩ
or greater on the output side. If the total
impedance is less than 10kΩ, the load
on the output amplifier of the cross-point
mixer will be excessive, and signals
may be lost.
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Communication ICsBU8241F / BU8241FS / BU8242F / BU8244F
Operation notes
(1) Turning on the power supply
When the power supply is turned on, the shift register is
in an indeterminate state. After turning on the power supply, switch settings should be entered by supplying shift
clock pulses to shift 64 bits of data into the shift register,
and then setting the LATCH pin to HIGH. (For the
BU8244, send 16 clock pulses.)
(2) Setting serial data
If the number of bits shifted or clock pulses applied is less
than or more than the number stated above, the switches
will not be set properly. Never apply shift clock pulses
when the LATCH pin is HIGH. Doing so will change the
data latch contents.
(3) Drive impedance
The input impedance Zin is 80 ± 32kΩ.
To suppress input gain and loss, we recommend using
the drive impedance shown in the table below.
If the level is to be attenuated at the input pin, make sure
the level is not affected by the internal resistance of the
IC, as shown in Figure 10. This can cause gain and/or
loss.
(4) Gain and noise when mixing signals
Increasing the number of signals mixed in a single output
(increasing the number of switches connected to the
same output amplifier that are on) causes a slight drop
in gain. With the BU8241 and BU8241FS/
BU8242F, increasing the number of signals mixed in a
single output (increasing the number of switches connected to the same output amplifier that are on) causes
a slight increase in the noise level in terms of logic. If
noise is a problem, we recommend limiting the number
of signals mixed in a single output.
(5) Output load capacitance
The capacitance connected to GND in relation to an output pin (the output load capacitance) should be kept to
50pF or lower. (BU8241F/BU8241FS/ BU8242F)
Electrical characteristic curves
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Communication ICsBU8241F / BU8241FS / BU8242F / BU8244F
Electrical characteristic curves
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Communication ICsBU8241F / BU8241FS / BU8242F / BU8244F
External dimensions (Units: mm)
276
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