Datasheet BTS 781 GP Datasheet (lnfineon)

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TrilithIC

Data Sheet

1Overview

1.1 Features

• Quad D-MOS switch

• Free configurable as bridge or quad-switch

• Optimized for DC motor management applications

•Low

R

switch (typical values @ 25 °C)

• Maximum peak current: typ. 42 A @ 25 °C=

• Very low quiescent current: typ. 4 µA @ 25 °C=

• Small outline, thermal optimized PowerPak

• Load and GND-short-circuit-protection

• Operates up to 40 V

• Status flag for over temperature

• Open load detection in Off-mode

• Overtemperature shut down with hysteresis

• Internal clamp diodes

• Isolated sources for external current sensing

• Under-voltage detection with hysteresis

: 26 mΩ high-side switch, 14 mΩ low-side

DS ON

BTS 781 GP

P-TO263-15-1

Type Ordering Code Package

BTS 781 GP Q67006-A9526 P-TO263-15-1

1.2 Description

The BTS 781 GP is part of the TrilithIC family containing three dies in one package: One double high-side switch and two low-side switches. The drains of these three vertical DMOS chips are mounted on separated leadframes. The sources are connected to individual pins, so the BTS 781 GP can be used in H-bridge- as well as in any other configuration. The double high-side is manufactured in SMART SIPMOS which combines low

R

vertical DMOS power stages with CMOS control circuit. The

DS ON

®

technology

high-side switch is fully protected and contains the control and diagnosis circuit. To achieve low

R

and fast switching performance, the low-side switches are

DS ON

manufactured in S-FET 2 logic level technology. The equivalent standard product is the SPD30N06S2L-13.

Data Sheet 1 2002-06-28

1.3 Pin Configuration

(top view)

BTS 781 GP

Molding Compound

NC

SL1

IL1

NC

IH1

ST1

SH1

DHVS

GND

IH2

1

2

3

4

5

6

7

8

9

10

Heat-Slug 1

18

DL1

Heat-Slug 2

1716DHVS

ST2

SH2

11

12

Heat-Slug 3

SL2

13

DL2

NC

IL2

Figure 1

Data Sheet 2 2002-06-28

14

15

BTS 781 GP

1.4 Pin Definitions and Functions

Pin No. Symbol Function

1 NC Not connected

2 SL1 Source of low-side switch 1

3 IL1 Analog input of low-side switch 1

4 NC Not connected

5 IH1 Digital input of high-side switch 1

6 ST1 Status of high-side switch 1; open Drain output

7 SH1 Source of high-side switch 1

8 DHVS Drain of high-side switches and power supply voltage

9 GND Ground of high-side switches

10 IH2 Digital input of high-side switch 2

11 ST2 Status of high-side switch 2; open Drain output

12 SH2 Source of high-side switch 2

13 SL2 Source of low-side switch 2

14 NC Not connected

15 IL2 Analog input of low-side switch 2

16 DL2 Drain of low-side switch 2

Heat-Slug 3

17 DHVS Drain of high-side switches and power supply voltage

Heat-Slug 2

18 DL1 Drain of low-side switch 1

Heat-Slug 1

Pins written in bold type need power wiring.

Data Sheet 3 2002-06-28

1.5 Functional Block Diagram

BTS 781 GP

DHVS

ST1

ST2

IH1

IH2

GND

IL1

10

6

11

5

9

8, 17

Diagnosis

Biasing and Protection

Driver

OUT 0IN0 L L 0 1 L H 1 0 H L 1 1 H H

3

R

O1

R

O2

16

18

12

SH2

DL2

7

SH1

DL1

15

IL2

2

SL1

13

SL2

Figure 2 Block Diagram

Data Sheet 4 2002-06-28

BTS 781 GP

1.6 Circuit Description

Input Circuit

The control inputs IH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs are protected by ESD clamp-diodes.

The inputs IL1 and IL2 are connected to the gates of the standard N-channel vertical power-MOS-FETs.

Output Stages

The output stages consist of a low

R

Power-MOS H-bridge. In H-bridge

DS ON

configuration, the D-MOS body diodes can be used for freewheeling when commutating inductive loads. If the high-side switches are used as single switches, positive and negative voltage spikes which occur when driving inductive loads are limited by integrated power clamp diodes.

Short Circuit Protection

The outputs are protected against

– output short circuit to ground – overload (load short circuit).

An internal OP-amp controls the Drain-Source-voltage by comparing the DS-voltagedrop with an internal reference voltage. Above this trippoint the OP-Amp reduces the output current depending on the junction temperature and the drop voltage.

In the case of overloaded high-side switches the status output is set to low.

Overtemperature Protection

The high-side switches incorporate an overtemperature protection circuit with hysteresis which switches off the output transistors and sets the status output to low.

Undervoltage-Lockout (UVLO)

When VS reaches the switch-on voltage V The high-side output transistors are switched off if the supply voltage switch off value

V

UVOFF.

the IC becomes active with a hysteresis.

UVON

V

drops below the

S

Open Load Detection

Open load is detected by voltage measurement in off state. If the output voltage exceeds a specified level the error flag is set with a delay.

Data Sheet 5 2002-06-28

BTS 781 GP

Status Flag

The two status flag outputs are an open drain output with Zener-diode which require a pull-up resistor, c.f. the application circuit on page 15. ST1 and ST2 provide separate diagnosis for each high-side switch. Various errors as listed in the table “Diagnosis” are detected by switching the open drain output ST1/2 to low. Forward current in the integrated body diode of the highside switch may cause undefined voltage levels at the corresponding status output. The open load detection can be used to detect a short to Vs as long as both lowside switches are off and R BCR192W.

2 Truthtable and Diagnosis (valid only for the High-Side-Switches)

Flag IH1 IH2 SH1 SH2 ST1 ST2 Remarks

Inputs Outputs

is disconnected from 5V by

OL

0 Normal operation; identical with functional truth table

Open load at high-side switch 1

Open load at high-side switch 2

Overtemperature high-side switch1 0

Overtemperature high-side switch2 X

Overtemperature both high-side switches

Undervoltage X X L L 1 1 not detected

0

1

0

1

X

1

X

0

X

1

0 1 0 1

X X 0 1

X X

0 1

0 1 X

L L H H

Z H X X

L L

X X

L L L

L H L H

X X Z H

X X

L L

L L L

1 1 1 1

0 1 1 1

1 0

1 1

1 1 0

1 1 1 1

1 1 0 1

1 1 detected

1 0 detected

1 0 1

stand-by mode switch2 active switch1 active both switches active

detected

detected detected

Note: * multiple simultaneous errors are not shown in this table

Inputs: Outputs: Status:

0 = Logic LOW Z = Output in tristate condition 1 = No error

1 = Logic HIGH L = Output in sink condition 0 = Error

X = don’t care H = Output in source condition

X = Voltage level undefined

Data Sheet 6 2002-06-28

3 Electrical Characteristics

3.1 Absolute Maximum Ratings

T

– 40 °C <

< 150 °C

j

Parameter Symbol Limit Values Unit Remarks

min. max.

High-Side-Switches (Pins DHVS, IH1,2 and SH1,2)

BTS 781 GP

Supply voltage

Supply voltage for full short

V

S

V

S(SCP)

– 0.3 42 V –

28 V –

circuit protection

HS-drain current

HS-input current

HS-input voltage

I

V

S

IH

– 10 * A TC = 125°C; DC

– 5 5 mA Pin IH1 and IH2

– 10 16 V Pin IH1 and IH2

Note: * internally limited

Status Output ST (Pins ST1 and ST2)

Status pull up voltage

Status Output current

V

I

ST

– 0.3 5.4 V –

– 5 5 mA Pin ST1 or ST2

Low-Side-Switches (Pins DL1,2, IL1,2 and SL1,2)

Drain- source break down

V

DSL

55 – V VIL=0V; ID≤ 1mA

voltage

LS-drain current

T

= 85°C

C

LS-input voltage

I

V

DL

IL

–20 20 A TC = 125°C; DC

–25Atp < 100 ms; ν<0.1

–100A

t

< 1 ms; ν<0.1

p

– 20 20 V Pin IL1 and IL2

Temperatures

Junction temperature

Storage temperature

Data Sheet 7 2002-06-28

T

j

T

stg

– 40 150 °C–

– 55 150 °C–

3.1 Absolute Maximum Ratings (cont’d)

– 40 °C <

T

< 150 °C

j

Parameter Symbol Limit Values Unit Remarks

min. max.

Thermal Resistances (one HS-LS-Path active)

BTS 781 GP

LS-junction case

HS-junction case

Junction ambient

R

thja

= T

j(HS)

/(P

(HS)+P(LS)

R

thjC L

R

thjC H

R

thja

)

–0.6K/W

– 0.75 K/W

– 35 K/W device soldered to

reference PCB with

2

6cm

cooling area

ESD Protection (Human Body Model acc. MIL STD 883D, method 3015.7 and EOS/ ESD assn. standard S5.1 - 1993)

Input LS-Switch

Input HS-Switch

Status HS-Switch

Output LS and HS-Switch

V

ESD

0.5 kV

1kV

2kV

4 kV all other pins connected

to Ground

Note: Maximum ratings are absolute ratings; exceeding any one of these values may

cause irreversible damage to the integrated circuit.

3.2 Operating Range

T

– 40 °C <

< 150 °C

j

Parameter Symbol Limit Values Unit Remarks

min. max.

Supply voltage

Input voltages HS V

Input voltages LS

Status output current

Junction temperature

V

I

T

ST

S

IH

IL

jHS

V

UVOFF

42 V After VS rising

above

V

– 0.3 15 V –

– 0.3 20 V –

02mA–

– 40 150 °C–

UVON

Note: In the operating range the functions given in the circuit description are fulfilled.

Data Sheet 8 2002-06-28

3.3 Electrical Characteristics

I

SH1

= I

SH2

= I

SL1

= I

= 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V

SL2

unless otherwise specified

BTS 781 GP

Parameter Symb

ol

Current Consumption HS-switch

Quiescent current

Supply current

Leakage current of

I

S Q

I

S

I

SH LK

highside switch

Leakage current through logic GND in free

I

LKCL

I

FH

+ I

=

SH

wheeling condition

Current Consumption LS-switch

Limit Values Unit Test Condition

min. typ. max.

–49µAIH1 = IH2 = 0V

T

= 85 °C

j

––20µAIH1 = IH2 = 0V

– 2.5 4.5 mA IH1 or IH2 = 5 V

– 5 9 mA IH1 and IH2 = 5 V

––7µA VIH = VSH = 0 V

T

= 85 °C

j

–2.210mAIFH =5 A

Input current

Leakage current of

I

IL

I

DL LK

–10100nAVIL = 20 V

––12µA VIL = 0 V

lowside switch

Under Voltage Lockout (UVLO) HS-switch

Switch-ON voltage V

Switch-OFF voltage

Switch ON/OFF

V

UVON

UVOFF

UVHY

––5VVS increasing

1.8 – 4.5 V VS decreasing

–1–VV

hysteresis

V

= 0 V

DSL

V

= 40 V

DSL

T

= 85 °C

j

UVON

– V

UVOFF

Data Sheet 9 2002-06-28

3.3 Electrical Characteristics (cont’d)

I

SH1

= I

SH2

= I

SL1

= I

= 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V

SL2

unless otherwise specified

BTS 781 GP

Parameter Symb

ol

Output stages

Inverse diode of high-

V

FH

side switch; Forwardvoltage

Inverse diode of lowside

V

FL

switch; Forward-voltage

Static drain-source

R

DS ON H

on-resistance of highside switch

Static drain-source

R

DS ON L

on-resistance of lowside switch

Static path on-resistance

R

DS ON

Limit Values Unit Test Condition

min. typ. max.

–0.81.2VIFH = 5 A

–0.81.2VIFL = 5 A

– 2635mΩ ISH =5A

T

= 25 °C

j

– 1417mΩ ISL =5A;

V

= 5 V

IL

T

= 25 °C

j

––100mΩ

R

DS ON H

I

=5A;

SH

+R

DS ON L

Short Circuit of highside switch to GND

Initial peak SC current I

Initial peak SC current

SCP H

I

SCP H

I

SCP H

35 48 65 A Tj = – 40 °C

30 42 54 A Tj = + 25 °C

25 32 42 A Tj = + 150 °C

Note: Peak SC current is significantly lower at V

V

Short Circuit of highside switch to

Output pull-down-resistor

R

O

S

7 1442kΩ V

> 18V

S

DSL

= 3 V

Data Sheet 10 2002-06-28

3.3 Electrical Characteristics (cont’d)

I

SH1

= I

SH2

= I

SL1

= I

= 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V

SL2

unless otherwise specified

BTS 781 GP

Parameter Symb

ol

Limit Values Unit Test Condition

min. typ. max.

Thermal Shutdown

Thermal shutdown

T

j SD

155 180 190 °C–

junction temperature

Thermal switch-on

T

j SO

150 170 180 °C–

junction temperature

Temperature hysteresis ∆

T –10–°C ∆T = T

Status Flag Output ST of highside switch

Low output voltage

Leakage current

Zener-limit-voltage

Status change after

V

ST L

I

ST LK

V

ST Z

t

d(SToffo+)

–0.20.6VIST = 1.6 mA

––5µA VST = 5 V

5.4 – V IST = 1.6 mA

––20µs positive input slope with open load

jSD

– T

jSO

Status change after

t

d(SToffo-)

––700µs negative input slope with open load

Status change after

t

d(STofft+)

–1.610µs RST = 47 kΩ positive input slope with overtemperature

Status change after

t

d(STofft-)

–14100µs RST = 47 kΩ negative input slope with overtemperature

Note: times are guaranteed by design

Open load detection in Off condition

Open load detection

V

OUT(OL)

234V voltage

Data Sheet 11 2002-06-28

3.3 Electrical Characteristics (cont’d)

I

SH1

= I

SH2

= I

SL1

= I

= 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V

SL2

unless otherwise specified

BTS 781 GP

Parameter Symb

ol

Limit Values Unit Test Condition

min. typ. max.

Switching times of highside switch

Turn-ON-time; to 90%

V

SH

Turn-OFF-time; to 10%

V

SH

Slew rate on 10 to 30%

V

SH

Slew rate off 70 to 40%

V

SH

t

ON

t

OFF

dV/ dt

ON

-dV/ dt

OFF

–100220µsR

–120250µsR

–0.51.1V/µsR

–0.71.3V/µsR

Note: switching times are guaranteed by design

Switching times of low-side switch

Turn-ON delay time;

V

= 5V; R

IL

Gate

= 16Ω

t

d_ON_L

– 40 ns resistive load

= 12 Ω

Load

V

= 12 V

S

= 12 Ω

Load

V

= 12 V

S

= 12 Ω

Load

V

= 12 V

S

= 12 Ω

Load

V

= 12 V

S

I

= 10 A; VS = 12 V

SL

Switch-ON time;

V

= 5V; R

IL

Gate

= 16Ω

Switch-OFF delay time;

V

= 5V; R

IL

Gate

= 16Ω

Switch-OFF time;

V

= 5V; R

IL

Gate

= 16Ω

Input to source charge;

Input to drain charge;

Input charge total;

t

ON_L

t

d_OFF_L

t

OFF_L

Q

IS

Q

ID

Q

I

– 170 ns resistive load

I

– 100 ns resistive load

I

– 200 ns resistive load

I

–4.56nCISL = 10 A; VS = 40 V

– 1624nCISL = 10 A; VS = 40 V

– 5569nCISL = 10 A; VS = 40 V

V

Input plateau voltage;

Note: switching times and input charges are guaranteed by design

V

(plateau)

–2.6–VISL = 10 A; VS = 40 V

= 10 A; VS = 12 V

SL

= 10 A; VS = 12 V

SL

= 10 A; VS = 12 V

SL

= 0 to 10 V

IL

Data Sheet 12 2002-06-28

3.3 Electrical Characteristics (cont’d)

I

SH1

= I

SH2

= I

SL1

= I

= 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V

SL2

unless otherwise specified

BTS 781 GP

Parameter Symb

ol

Limit Values Unit Test Condition

min. typ. max.

Control Inputs of highside switches IH 1, 2

H-input voltage

L-input voltage

Input voltage hysterese

H-input current

L-input current

Input series resistance

Zener limit voltage

V

IH High

V

IH Low

V

IH HY

I

IH High

I

IH Low

R

I

V

IH Z

––2.5V–

1––V–

–0.5–V–

53060µA VIH = 5 V

51425µA VIH = 0.4 V

2.7 4 6 kΩ –

5.4 – – V IIH = 1.6 mA

Control Inputs IL1, 2

Gate-threshold-voltage

I

= 1 mA

DL

V

IL th

–1.92.6VTj = – 40 °C

–1.7–

T

= + 25 °C

j

0.8 1.1 –

T

= + 150 °C

j

Note: The listed characteristics are ensured over the operating range of the integrated

circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at

V

= 12 V.

S

T

= 25 °C and

A

Data Sheet 13 2002-06-28

BTS 781 GP

V

S

I

FH1,2

I

S

C

S

470nF

C

L

100µF

I

ST LK1

I

ST1

I

ST LK2

I

ST2

V

ST1

V

STL1

V

ST2

V

STZ1

V

STL2

V

STZ2

V

IL th 1

I

IH1

I

IH1

V

IH2

I

IL1

I

IL1

IL2

V

IL2

V

IL th 2

ST1

ST2

IH1

IH2

GND

I

GND

I

LKCL

IL1

IL2

6

11

5

10

6

3

15

Diagnosis

Gate

Driver

Gate

Driver

Biasing and Protection

2

SL1

I

SCP L 1

I

SL1

DHVS

8, 17

R

O1

O2

SH2

12

DL2

16

SH1

7

DL1

18

13

SL2

I

SCP L 2

I

SL2

I

SH2

I

DL2

I

DL LK 2

I

SH1

I

DL1

I

DL LK 1

V

DSH2

DSH1

-V

FH2

FH1

V

UVON

V

UVOFF

V

DSL1

DSL2

-V

FL1

FL2

Figure 3 Test Circuit

HS-Source-Current Named during Short

Circuit

I

SH1,2

Data Sheet 14 2002-06-28

I

SCP H

Named during LeakageCond.

I

DL LK

100 k

BTS 781 GP

Watchdog

I

D01 Z39

VS=12V

C

S

10µF

Q

TLE

4278G

D

C

D

47nF

Reset

R

Q

100 k

R

Q

ΩΩΩΩ

22µF

C

Q

WD R

µP

V

CC

R

10 k

R

10 k

ST1

S

6

ΩΩΩΩ

ST2

S

11

Diagnosis

Biasing and Protection

ΩΩΩΩ

5

IH1

Gate

Driver

IH2

10

Gate

Driver

9

GND

DHVS

8, 17

BCR192W

Can be replaced by diode when

to µC

Short to Vs detection is not needed

R

OL

560Ohm

optional for open load in off

R

O1

R

O2

16

SH2

12

DL2

M

SH1

7

DL1

18

3

IL1

15

IL2

GND

2

SL1

13

SL2

Figure 4 Application Circuit

Data Sheet 15 2002-06-28

4 Package Outlines

P-TO263-15-1

(Plastic Transistor Single

±0.15

5.56

±0.2

1

X1, 1)

4.8

±0.2

9.25

(15)

21.6

8.3

8.18

±0.2

X2, 1)

±0.15

BTS 781 GP

4.4

±0.1

1.27

B

±0.5

4.7

0.1

2.4

±0.3

2.7

0.05

A

±0.3

1

1)

7.65

FootprintFootprint

1)

Typical

14 x 1.4

M

0.8

BA0.25

0...0.15

±0.1

Metal surface min. X1 = 3.57, X2 = 7.03, Y = 6.9 All metal surfaces tin plated, except area of cut.

21.6

0.8

8.4

9.5

16

8˚

MAX.

4

0.5

±0.1

0.1

B

0.4

1

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”.

SMD = Surface Mounted Device

Dimensions in mm

Data Sheet 16 2002-06-28

BTS 781 GP

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the

failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life

support devices or systems are intended to be implanted in the human body, or to support and/or maintain and

sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other

persons may be endangered.

Data Sheet 17 2002-06-28