• ’SAMSUNG’ KS0065B-PCC (Die form) LCD Segment Driver or equivalent.
2. Mechanical Specifications
The mechanical detail is shown in Fig. 2 and summarized in Table 1 below.
Table 1
Parameter Specifications Unit
Outline dimensions 116.0(W) x 37.0(H) x 11.0 MAX.(D) mm
Effective viewing area 83.0(W) x 18.6(H) mm
Display format 20 characters x 2 lines Character size 3.20(W) x 5.55(H) (5 x 8 dots) mm
Character spacing 0.50(W) x 0.40(H) mm
Character pitch 3.70(W) x 5.95(H) mm
Dot size 0.628(W) x 0.681(H) mm
Dot spacing 0.015(W) x 0.015(H) mm
Dot pitch 0.643(W) x 0.696(H) mm
Weight: TBD grams
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3. Interface signals
Table 2
Pin No. Symbol Description
1 VSS Ground(0V).
2 VDD Power supply for logic (+5V)
3 V0 Power supply for LCD driver
4 RS Register Select Input:
“High” for Data register (for read and write)
”Low” for Instruction register (for write),
Busy flag, address counter (for read)
5 R/W Read/Write signal:
” High” for Read mode.
“Low” for Write mode.
6 E Enable.
Start signal for data read /write.
7 DB0 Data input/output (LSB)
8 DB1 Data input/output
9 DB2 Data input/output
10 DB3 Data input/output
11 DB4 Data input/output
12 DB5 Data input/output
13 DB6 Data input/output
14 DB7 Data input/output (MSB)
15(A) LED(+) Anode of LED backlight
16(K) LED(-) Cathode of LED backlight
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A
H
V
H
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BTHQ 22005VSS-SRE
4. Absolute Maximum Ratings
4.1 Electrical Maximum Ratings(Ta = 25 ºC)
Table 3
ParameterSymbolMin.Max.Unit
Power Supply voltage (Logic)VDD - VSS-0.3+7.0V
Power Supply voltage (LCD drive)VLCD=VDD – V0-0.3+15.0V
Input voltageVin-0.3VDD +0.3V
Note:
The modules may be destroyed if they are used beyond the absolute maximum ratings.
8/13
All voltage values are referenced to VSS = 0V.
4.2 Environmental Condition
Operating
Item
Temperature
(Topr)
Min. Max. Min. Max.
mbient Temperature
umidity
0°C +50°C -10°C +60°C
95% max. RH for Ta ≤ 40°C
< 95% RH for Ta > 40°C
ibration (IEC 68-2-6)
cells must be mounted
on a suitable connector
Shock (IEC 68-2-27)
alf-sine pulse shape
Frequency: 10 ∼ 55 Hz
Amplitude: 0.75 mm
Duration: 20 cycles in each direction.
Pulse duration : 11 ms
Peak acceleration: 981 m/s
Number of shocks : 3 shocks in 3
mutually perpendicular axes.
Table 4
Storage
Temperature
(Tstg)
2
= 100g
Remark
Dry
no condensation
3 directions
3 directions
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5. Electrical Specifications
5.1 Typical Electrical Characteristics
At Ta = 25 °°°°C, VDD = 5V±±±±5%, VSS=0V.
Parameter Symbol Conditions Min. Typ. Max. Unit
Supply voltage (Logic) VDD-VSS 4.75 5.0 5.25 V
Supply voltage (LCD) VLCD
=VDD-V0
VIH ”H” level 2.2 - VDD V Input signal voltage
for E,DB0-DB7,R/W,RS.
(Logic & LCD)
” L” level -0.3 - 0.6 V
V
IL
IDD
Table 5
VDD =5.0V,
Note1.
Character mode,
Note 1
Checker board
mode, Note 1
Character mode,
Note 1
Checker board
mode, Note 1
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4.2 4.5 4.8 V
- 1.0 1.5 mA Supply Current
- 1.2 1.8 mA
- 0.3 0.5 mA Supply Current (LCD) I0
- 0.3 0.5 mA
Note (1) : There is tolerance in optimum LCD driving voltage during production and it will be within
the specified range.
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5.2 Timing Specifications
At Ta = 0 °C To +50 °C , VDD = +5V±5%, VSS = 0V.
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Refer to Fig. 3
, the bus timing diagram for write mode.
Table 6
Parameter Symbol Min. Max. Unit Test pin
E cycle time tC 500 - ns E
E rise time tR - 25 ns E
E fall time tF - 25 ns E
E pulse width (High, Low) tW 220 - ns E
R/W and RS set-up time t
40 - ns R/W,RS
SU1
R/W and RS hold time tH1 10 - ns R/W, RS
Data set-up time t
60 - ns DB0-DB7
SU2
Data hold time tH2 10 - ns DB0-DB7
Refer to Fig. 4, the bus timing diagram for read mode .
Table 7
Parameter Symbol Min. Max. Unit Test pin
E cycle time tC 500 - ns E
E rise time tR - 25 ns E
E fall time tF - 25 ns E
E pulse width tW 220 - ns E
R/W and RS set-up time tSU 40 - ns R/W,RS
R/W and RS hold time tH 10 - ns R/W, RS
Data output delay time tD - 120 ns DB0-DB7
Data hold time tDH 20 - ns DB0-DB7
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Figure 3: The bus timing diagram for write mode
Figure 4: The bus timing diagram for read mode .
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5.3 Timing Diagram of VDD against V0.
Power on sequence shall meet the requirement of Figure 5, the timing diagram of VDD against V0.
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VDD
95%
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LOGIC SUPPLY
VOLTAGE
0V
0V
LCD SUPPLY
VOLTAGE
V0
50ms(typical)
Figure 5: Timing diagram of VDD against V0.
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6. CGROM Character Code Table
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