The mechanical detail is shown in Fig. 1 and summarized in Table 1 below.
Table 1
Parameter Specifications Unit
Outline dimensions 122.0(W) x 43.0(H) x 11.0 MAX.(D) mm
Effective viewing area 99.0(W) x 23.0(H) mm
Display format 16 characters x 2 lines Character size 4.84(W) x 9.22(H) (5 x 8 dots ) mm
Character spacing 1.16(W) x 0.53(H) mm
Character pitch 6.00(W) x 9.75(H) mm
Dot size 0.956(W) x 1.139(H) mm
Dot spacing 0.015(W) x 0.015(H) mm
Dot pitch 0.971(W) x 1.154(H) mm
Weight: TBD Grams
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3. Absolute Maximum Ratings
3.1 Electrical Maximum Ratings(Ta = 25 °°°°C)
Table 2
ParameterSymbolMin.Max.Unit
Power Supply voltage (Logic)VDD - VSS-0.3 +7.0V
Power Supply voltage (LCD drive)VLCD=VDD – V0-0.3+15.0V
Input voltageVin-0.3VDD+0.3V
Note:
The modules may be destroyed if they are used beyond the absolute maximum ratings.
All voltage values are referenced to VSS = 0V.
BTHQ 21608VSS-SRE
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3.2 Environmental Condition
Item
Ambient Temperature
Humidity
Vibration (IEC 68-2-6)
cells must be mounted
on a suitable connector
Shock (IEC 68-2-27)
Half-sine pulse shape
95% max. RH for Ta ≤ 40°C
< 95% RH for Ta > 40°C
Frequency: 10 ∼ 55 Hz
Amplitude: 0.75 mm
Duration: 20 cycles in each direction.
Pulse duration : 11 ms
Peak acceleration: 981 m/s2= 100g
Number of shocks:3 shocks in 3 mutually perpendicular axes.
Table 3
Operating
Temperature
(Topr)
Min. Max. Min. Max.
0°C +50°C -10°C +60°C
Storage
Temperature
(Tstg)
Remark
Dry
no condensation
3 directions
3 directions
DATA MODUL AG Landsberger Str. 322 80687 München Tel.: 089/ 56017-0 Fax 089/ 56017-119
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4. Electrical Specifications
4.1 Interface signals
Table 4
Pin No. Symbol Description
1 VSS Ground (0V).
2 VDD Power supply for logic (+5.0V)
3 V0 Power supply for LCD driver
4 RS Register Select Input:
”High’ for Data register (for read and write)
”Low” for Instruction register (for write),
Busy flag, address counter (for read)
5 R/W Read/Write signal:
‘High’ for Read mode.
‘Low’ for Write mode.
6 E Enable.
Start signal for data read /write.
7 DB0 Data input/output (LSB)
8 DB1 Data input/output
9 DB2 Data input/output
10 DB3 Data input/output
11 DB4 Data input/output
12 DB5 Data input/output
13 DB6 Data input/output
14 DB7 Data input/output (MSB)
A LED(+) Anode of LED Backlight.
K LED(-) Cathode of LED Backlight.
BTHQ 21608VSS-SRE
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DATA MODUL AG Landsberger Str. 322 80687 München Tel.: 089/ 56017-0 Fax 089/ 56017-119
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BTHQ 21608VSS-SRE
4.2 Typical Electrical Characteristics
At Ta = +25 °°°°C, VDD = +5V±±±±5%, VSS = 0V.
Table 5
Parameter Symbol Conditions Min. Typ. Max. Unit
Supply voltage (Logic) VDD-VSS 4.75 5.0 5.25 V
Supply voltage (LCD) VLCD
=VDD-V0
Input signal voltage 1
for E,DB0-DB7,R/W,RS
Input signal voltage 2
for OSC1
Supply Current
V
IH1
V
IL1
V
IH2
V
IL2
IDD Character mode,
(Logic & LCD)
Supply Current (LCD) I0 Character mode,
VDD = 5V,
4.0 4.5 5.0 V
Note 1
“High” level 2.2 - VDD V
“Low” level -0.3 - 0.6 V
“High” level VDD -1.0 - VDD V
“Low” level - - 1.0 V
- 1.7 2.6 mA
Note 1
- 0.9 1.4 mA
Note 1
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Note (1):
There is tolerance in optimum LCD driving voltage during production and it will be within
the specified range.
DATA MODUL AG Landsberger Str. 322 80687 München Tel.: 089/ 56017-0 Fax 089/ 56017-119
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BTHQ 21608VSS-SRE
4.3 Timing Specifications
At Ta = 0 °C to +50 °C , VDD = 5V±5%, VSS=0V.
Refer to Fig. 2, the bus timing diagram for write mode.
Table 6
Parameter Symbol Min. Max. Unit Test pin
E cycle time tC 500 - ns E
E rise time tR - 25 ns E
E fall time tF - 25 ns E
E pulse width (High, Low) tW 220 - ns E
R/W and RS set-up time t
40 - ns R/W,RS
SU1
R/W and RS hold time tH1 10 - ns R/W, RS
Data set-up time t
60 - ns DB0-DB7
SU2
Data hold time tH2 10 - ns DB0-DB7
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Refer to Fig. 3, the bus timing diagram for read mode.
Table 7
Parameter Symbol Min. Max. Unit Test pin
E cycle time tC 500 - ns E
E rise time tR - 25 ns E
E fall time tF - 25 ns E
E pulse width tW 220 - ns E
R/W and RS set-up time tSU 40 - ns R/W,RS
R/W and RS hold time tH 10 - ns R/W, RS
Data output delay time tD - 120 ns DB0-DB7
Data hold time tDH 20 - ns DB0-DB7
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BTHQ 21608VSS-SRE
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Figure 2: The bus timing diagram for write mode .
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Figure 3: The bus timing diagram for read mode .
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4.4 Timing Diagram of VDD against V0.
Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against V0.
BTHQ 21608VSS-SRE
VDD
95%
LOGIC SUPPLY
12/12
VOLTAGE
0V
OV
LCD SUPPLY
VOLTAGE
50ms(typical)
Figure 4: Timing diagram of VDD against V0.
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V0
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