Datasheet BT865AKPF, BT864AKPF Datasheet (CONEX)

Data Sheet 100138B

September 2000

Bt864A/865A

YCrCb to NTSC/PAL Digital Video Encoder

The Bt864A/865A is specifically designed for video systems requiring the generation of
composite, Y/C (S-video) or RGB (SCART) video signals from an 8- or 16-bit YCrCb
digital video stream. Worldwide video standards are supported including NTSC-M (N.
America, Taiwan, Japan), PAL-B,D,G,H,I (Europe, Asia), PAL–M (Brazil), PAL-N
(Uruguay, Paraguay) and PAL–Nc (Argentina). The Bt864A and Bt865A are functionally
identical, with the exception that Bt865A can output the Macrovision level 7 anticopy
algorithm.

Horizontal sync (HSYNC*) and vertical sync (VSYNC*) may be configured as inputs
(slave mode) or outputs (master mode). BLANK* is an input and may be externally
controlled. Horizontal and vertical blanking are automatically generated. The rise and fall
times of sync, the burst envelope, and closed caption data are internally controlled.

Analog luminance (Y) and chrominance (C) information is available on the Y and C
outputs for interfacing to S-video equipment. The composite analog video signal is
output simultaneously onto two outputs. This allows one output to provide baseband
composite video while the other drives an RF modulator. Analog RGB is also available to
allow for support of the European SCART/PeriTV interface.

Functional Block Diagram

Internal

RESET*

C/R

Y/CVBS

CVBS/G

COMP

1.3 MHz
LPF

VREF FSADJUST

DAC

DAC

DAC

CVBS/B

DAC

10

Color

Space

Latch

Y[7:0]

HSYNC*

VSYNC*

BLANK*

CLK

RGBOUT

SCLSDA

Convert

Mod.

and

Mixer

2 x

Upsampling

10

10

10

FIELD

SLAVE

SLEEP

VREF

VBIASTTXDAT

ALTADDR

TTXREQ

P[7:0]

VDD3V

Distinguishing Features

• 8- or 16-bit 4:2:2 YCrCb inputs

• NTSC-M/PAL/PAL–M/PAL–N/PAL–Nc

composite video outputs

• S-Video/RGB (SCART) outputs

• CCIR 601 or square pixel operation

• 2x oversampling

• 10-bit DACs

• Master or slave video timing

• Auto mode detection function

(slave mode)

• Interlaced/noninterlaced operation

• Macrovision 7 support (Bt865A only)

• Closed caption encoding

• Teletext encoding (WST system B)

• I

2

C Interface

• On-board voltage reference

• Power-down modes

• 52-pin PQFP package

• Programmable luma delay

(single-channel)

• 5 V or 3.3 V supply voltage

• CGMS/WSS (16:9)

Related Products

• Bt852

• Bt856/7

• Bt864/5

• Bt866/7

Applications

• Digital cable systems

• Satellite television setup boxes

(DBS/DSS)

• DVD players

• Digital VCR (DVC, DVHS)

• VideoCD players

• Portable VideoCD players

• Digital cameras

• PC add-on cards

100138B Conexant

© 2000, Conexant Systems, Inc.

All Rights Reserved.

Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are
provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no
responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at
any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to its specifications and product descriptions.

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engineer.

Ordering Information

Model Number Package Ambient Temperature Range

Bt864AKPF 52-Pin Plastic Quad Flatpack 0° to +70 °C

Bt865AKPF 52-Pin Plastic Quad Flatpack 0° to +70 °C

100138B Conexant iii

Table of Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

1.0 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3 Pixel Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.1 8-bit YCrCb Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.2 16-bit YCrCb Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.3 Pixel Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.4 HSYNC* Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.5 Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.5.1 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.5.2 Sync and Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.5.3 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.5.4 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.5.5 FIELD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.5.6 Pixel Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.5.7 Burst Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

1.5.8 Digital Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

1.5.9 Chrominance Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

1.5.10 Subcarrier Phasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

1.5.11 Vertical Blanking Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

1.5.12 BLANK* Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

1.5.13 Noninterlaced Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

1.6 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

1.7 Pixel Input Ranges and Colorspace Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23

1.7.1 YC Inputs (4:2:2 YCrCb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23

1.7.2 DAC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23

1.8 Closed Captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

Table of Contents Bt864A/865A

YCrCb to NTSC/PAL Digital Video Encoder

iv Conexant 100138B

1.9 Teletext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

1.9.1 CCIR601 Operation (13.5 MHz pixel rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

1.9.2 Square Pixel Operation (14.75 MHz pixel rate). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

1.9.3 Teletext Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

1.9.4 Teletext Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

1.10 Wide Screen Signaling (WSS)/Copy Generation Management System (CGMS) Encoding . . . . 1-29

1.11 Anticopy Process (Bt865A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

1.12 Internal Color Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

1.13 SCART/PeriTV Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

1.14 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

1.15 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

1.15.1 Luminance or CVBS (Y/CVBS) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

1.15.2 Chrominance or Red (C/R) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

1.15.3 Composite Video or Blue (CVBS/B) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

1.15.4 Composite Video or Green (CVBS/G) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

2.0 Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Essential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Important Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.3 Writing Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.4 Reading Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.5 Programming Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

3.0 PC Board Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Power and Ground Planes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.3 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.3.1 Device Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.3.2 Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.3.3 COMP Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.3.4 VREF Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.3.5 VBIAS Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.4 Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.4.1 Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.4.2 Analog Signal Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.5 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.5.1 ESD and Latchup Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.5.2 Clock and Subcarrier Stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.5.3 Mutual Inductance Concerns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.5.4 Reset Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.5.5 Filtering RF Modulator Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.5.6 Luminance Delay on CVBS/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Bt864A/865A Table of Contents

YCrCb to NTSC/PAL Digital Video Encoder

100138B Conexant v

3.6 I2C Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.6.1 Data Transfer on the I2C Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

4.0 Parametric Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Table of Contents Bt864A/865A

YCrCb to NTSC/PAL Digital Video Encoder

vi Conexant 100138B

Bt864A/865A List of Figures

YCrCb to NTSC/PAL Digital Video Encoder

100138B Conexant vii

List of Figures

Figure 1-1. Bt864A/865A Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 1-2. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Figure 1-3. HSYNC* Timing In Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Figure 1-4. Interlaced 525-Line (NTSC) Video Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Figure 1-5. Interlaced 525-Line (PAL-M) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Figure 1-6. Interlaced 625-Line (PAL–B, D, G, H, I, Nc) Video Timing. . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Figure 1-7. Interlaced 625-Line (PAL–B, D, G, H, I, Nc) Video Timing. . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Figure 1-8. Interlaced 625-Line (PAL–N) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Figure 1-9. Interlaced 625-Line (PAL–N) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Figure 1-10. Noninterlaced 262-Line (NTSC) Video Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Figure 1-11. Noninterlaced 262-Line (PAL-M) Video Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Figure 1-12. Noninterlaced 312-Line (PAL-B, D, G, H, I, N, Nc) Video Timing. . . . . . . . . . . . . . . . . . . . 1-14

Figure 1-13. Three-Stage Chrominance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Figure 1-14. Three-Stage Chrominance Filter (Passband). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Figure 1-15. Luminance 2X Upsampling Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Figure 1-16. Luminance 2X Upsampling Filter Response (Passband). . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Figure 1-17. DAC Sinx/x Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

Figure 1-18. DAC Sinx/x Response (Passband). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

Figure 1-19. Teletext Timing for Bt864A/865A Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

Figure 1-20. PQ Ratio Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Figure 1-21. Typical WSS/CGMS Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

Figure 1-22. Y (Luminance) Video Output Waveform SETUPDIS = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33

Figure 1-23. Y (Luminance) Video Output Waveform SETUPDIS = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34

Figure 1-24. C (Chrominance) Video Output Waveform SETUPDIS = 0. . . . . . . . . . . . . . . . . . . . . . . . . 1-35

Figure 1-25. C (Chrominance) Video Output Waveform SETUPDIS = 1. . . . . . . . . . . . . . . . . . . . . . . . . 1-36

Figure 1-26. CVBS (Composite) Video Output Waveform SETUPDIS = 0 . . . . . . . . . . . . . . . . . . . . . . . 1-37

Figure 1-27. CVBS (Composite) Video Output Waveform SETUPDIS = 1 . . . . . . . . . . . . . . . . . . . . . . . 1-38

Figure 3-1. Example Power Plane Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Figure 3-2. Typical Connection Diagram and Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Figure 3-3. Example of Mutual Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Figure 3-4. Wiring for the Reset Input Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Figure 3-5. I2C Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Figure 4-1. YCrCb Video Input and Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Figure 4-2. 52-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

List of Figures Bt864A/865A

YCrCb to NTSC/PAL Digital Video Encoder

viii Conexant 100138B

Bt864A/865A List of Tables

YCrCb to NTSC/PAL Digital Video Encoder

100138B Conexant ix

List of Tables

Table 1-1. Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Table 1-2. Field Resolutions and Clock Rates for Various Modes of Operation . . . . . . . . . . . . . . . . . . 1-15

Table 1-3. Horizontal Counter Values for Various Video Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Table 1-4. DAC Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23

Table 1-5. Legal Values to TXHS and TXHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-27

Table 1-6. Teletext Clock P and Q Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Table 1-7. DAC Output Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

Table 1-8. Y (Luminance) Video Output Truth Table SETUPDIS = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33

Table 1-9. Y (Luminance) Video Output Truth Table SETUPDIS = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34

Table 1-10. C (Chrominance) Video Output Truth Table SETUPDIS = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 1-35

Table 1-11. C (Chrominance) Video Output Truth Table SETUPDIS = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 1-36

Table 1-12. CVBS (Composite) Video Output Truth Table SETUPDIS = 0. . . . . . . . . . . . . . . . . . . . . . . . 1-37

Table 1-13. CVBS (Composite) Video Output Truth Table SETUPDIS = 1. . . . . . . . . . . . . . . . . . . . . . . . 1-38

Table 1-14. RGB Output Table (RGBOUT = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-39

Table 2-1. Read-back Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Table 2-2. Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Table 4-1. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Table 4-2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Table 4-3. DC Characteristics (VDD = 5 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Table 4-4. AC Characteristics (VDD = 5 V, VAA = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

List of Tables Bt864A/865A

YCrCb to NTSC/PAL Digital Video Encoder

x Conexant 100138B

100138B Conexant 1-1

1

1.0 Circuit Description

1.1 Pin Descriptions

Pin names, input/output assignments, numbers, and descriptions are listed in

Table 1 -1 . Figure 1-1 illustrates the Bt864A/865A pinout diagram, and Figure 1-2

details the block diagram.

Table 1-1. Pin Assignments (1 of 3)

Pin Name I/O Pin # Description

CLK I 43 2x pixel clock input (TTL compatible).

RESET* I 47 Reset control input (TTL compatible). A logical zero disables and resets video

timing (horizontal, vertical, subcarrier counters to the start of VSYNC of first
field) and resets the I2C interface (but does not reset I2C registers). RESET*

must be a logical one for normal operation.

BLANK* I 48 Composite blanking control input (TTL compatible). BLANK* is registered on

the rising edge of CLK. The P[7:0] and Y[7:0] inputs are ignored while BLANK*
is a logical zero.

VSYNC* I/O 49 Vertical sync input/output (TTL compatible). As an output (master mode

operation), VSYNC* is output following the rising edge of CLK. As an input
(slave mode operation), VSYNC* is registered on the rising edge of CLK.

HSYNC* I/O 50 Horizontal sync input/output (TTL compatible). As an output (master mode

operation), HSYNC* is output following the rising edge of CLK. As an input
(slave mode operation), HSYNC* is registered on the rising edge of CLK.

P[7:0] I 35–28 YCrCb pixel inputs (TTL compatible) in 8-bit YCrCb mode. CrCb pixel inputs

(TTL compatible) in 16-bit YCrCb mode. A higher index corresponds to a greater
bit significance.

Y[7:0] I 25, 24, 21–16 Y pixel inputs (TTL compatible) in 16-bit YCrCb mode. Y[7] enables internal

color bars when operating in 8-bit YCrCb mode. A higher index corresponds to a
greater bit significance.

(1)

TTXDAT I 27

Teletext bit stream input (TTL compatible).

(1)

TTXREQ O 38 Teletext request output (TTL compatible).

ALTADDR I 26 Alternate slave address input (TTL compatible). A logical one configures the

device to respond to an I2C address of 0x88; a logical zero configures the device
to respond to an I

2

C address of 0x8A.

(1)

1.0 Circuit Description Bt864A/865A

1.1 Pin Descriptions YCrCb to NTSC/PAL Digital Video Encoder

1-2 Conexant 100138B

SLAVE I 42 Slave/master mode select input (TTL compatible). A logical one configures the

device for slave video timing operation. A logical zero configures the device for
master video timing operation. This pin may be connected directly to VDD or
GND.

RGBOUT I 14 Analog RGB control input (TTL compatible). A logical one configures the device

to output analog RGB (RGBOUT mode) and one composite video output. A
logical zero configures the device to generate S-video along with two composite
video outputs. This pin may be connected directly to VDD or GND.

FIELD O 15 Field control output (TTL compatible). FIELD transitions after the rising edge of

CLK, two clock cycles following falling HSYNC*. It is a logical zero during FIELD
1 and is a logical one during FIELD 2.

SLEEP I 39 Power-down control input (TTL compatible). A logical one configures the device

for power-down mode. A logical zero configures the device for normal
operation. This pin may be connected directly to VDD or GND.

SDA I/O 40 Serial interface data input/output (TTL compatible). Data is written to and read

from the device via this serial bus.

SCL I 41 Serial interface clock input (TTL compatible). The maximum clock rate is

100 kHz.

VDD3V I 44 Input threshold adjustment. When low, indicates nominal supply voltage of

5 volts. When high, indicates nominal supply voltage of 3.3 volts.

CVBS/B O 8 Composite video or Blue (with blanking and sync, and optionally, Macrovision

encoding). Optional luma delay channel for composite video output.

AGND (CVBS/B) 6 Analog ground for pin CVBS/B.

CVBS/G O 10 Composite video or Green (with blanking and sync, and optionally, Macrovision

encoding).

AGND (CVBS/G) 7 Analog ground for pin CVBS/G.

C/R O 12 Modulated chrominance, or Red.

AGND (C/R) 9 Analog ground for pin C/R.

Y/CVBS O 13 Luminance or composite video (with blanking, sync, and optionally,

Macrovision encoding, and/or closed-captioning encoding).

AGND (Y/CVBS) 11 Analog ground for pin Y/CVBS.

FSADJUST I 1 Full-scale adjust control pin. A resistor (RSET) connected between this pin and

GND controls the full-scale output current on the analog outputs. For standard
operation, use the nominal RSET values shown under Recommended Operating
Conditions.

VBIAS O 2 DAC bias voltage. A 0.1 µF ceramic capacitor must be used to decouple this pin

to GND. The capacitor must be as close to the device as possible to keep lead
lengths to an absolute minimum.

VREF O 3 Voltage reference pin. A 0.1 µF ceramic capacitor must be used to decouple this

pin to GND. The capacitor must be as close to the device as possible to keep
lead lengths to an absolute minimum.

Table 1-1. Pin Assignments (2 of 3)

Pin Name I/O Pin # Description

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.1 Pin Descriptions

100138B Conexant 1-3

COMP O 5 Compensation pin. A 0.1 µF ceramic capacitor must be used to decouple this

pin to VAA. The capacitor must be as close to the device as possible to keep lead
lengths to an absolute minimum.

VAA – 4 Analog power. Refer to PC Board Considerations section of this document.

VDD – 37, 23, 46 Digital power. Refer to the PC Board Considerations section of this document.

AGND – 51, 52 Analog ground. Refer to the PC Board Considerations section of this document.

GND – 22, 36, 45 Digital ground. Refer to the PC Board Considerations section of this document.

NOTE(S):

(1)

Any unused inputs should not be left floating.

Table 1-1. Pin Assignments (3 of 3)

Pin Name I/O Pin # Description

Figure 1-1. Bt864A/865A Pinout Diagram

FS ADJUST

VBIAS

VREF

VAA

COMP

AGND
AGND

CVBS/B

AGND

CVBS/G

AGND

C/R

AGND

HSYNC*

VSYNC*

BLANK*

RESET*

VDD

GND

VDD3V

CLK

SLAVE

SCL

SDA

SLEEP
TTXREQ
VDD
GND
P[7]
P[6]
P[5]
P[4]
P[3]
P[2]
P[1]
P[0]
TTXDAT

RGBOUT

FIELD

Y[0]

Y[1]

GND

VDD

AGND

Y/CVBS

Y[2]

Y[6]

Y[7]

Y[5]

ALTADDR

Y[3]

Y[4]

14151617181920212223242526

1
2
3
4
5
6
7
8
9

52515049484746454443424140

39
38
37
36
35
34
33
32
31
30
29
28
27

10
11
12
13

1.0 Circuit Description Bt864A/865A

1.1 Pin Descriptions YCrCb to NTSC/PAL Digital Video Encoder

1-4 Conexant 100138B

Figure 1-2. Detailed Block Diagram

Internal Voltage

Reference

2X

RGBOUT

DEMUX,

VREF

FSADJUST

CVBS/G

Y/CVBS

C/R

DAC

DAC

DAC

Upsample

+

P[7:0]

8

NTSC

Blanking

Pedestal

SLAVE

Y

BLANK*

Video

Timing

Control

RESET*

Sync

Rise/Fall

Expander

+

+

1.3 MHz LPF

and 2X

Upsample

U/V

Modulator

10

CLK

SCL

SLEEP

SDA

and

Mixer

10

10

G

B

R

10

CVBS/BDAC

10

9

10

9

10

10

9

10

FIELD

HSYNC*

VSYNC*

COMP

BLANK*

VBIAS

ALTADDR

Color

Space

Convert

Y[7:0]

8

I

2

C Interface

Captioning,

Macrovision

Closed

TTXREQ

TTXDAT

+

Luma

Delay

10

4:2:2 -> 4:4:4

Upsample,

Magnitude

Luminance

Te le t ex t /

Scaling

CGMS

VDD3V

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.2 Clock Timing

100138B Conexant 1-5

1.2 Clock Timing

A clock signal with a frequency twice the pixel sampling rate must be present at
the CLK pin. The device generates an internal pixel CLOCK that in slave mode is
synchronized to the HSYNC* pin. This signal is used to increment the horizontal
pixel and vertical line counters and to register the pixel (P[7:0], Y[7:0], TTXDAT,
RESET*, BLANK*, SLAVE, HSYNC*, and VSYNC*) inputs. All setup and
hold timing specifications are measured with respect to the rising edge of CLK.

1.3 Pixel Input Timing

1.3.1 8-bit YCrCb Input Mode

The 8-bit YCrCb multiplexed input mode is selected by default. Multiplexed Y,
Cb, and Cr data is input through the P[7:0] inputs. By default, the input sequence
for active video pixels must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc. in
accordance with CCIR656.

1.3.2 16-bit YCrCb Input Mode

The 16-bit mode is selected by setting the YC16 register bit. Y data is input
through the Y[7:0] inputs. Multiplexed Cb and Cr data is input through the P[7:0]
inputs.

1.3.3 Pixel Synchronization

The default input pixel sequence is such that the next clock after HSYNC* goes
low will be the start of the 4-byte Cb/Y/Cr/Y sequence in 8-bit mode, or Y/Cb
sample pair in 16-bit mode. This is true for slave mode, and for master mode with
the default HSYNC* timing. This sequence can be changed by the SYNCDLY
and CBSWAP bits in both master and slave modes, or by using the variable
HSYNC* timing in master mode.

The SYNCDLY bit will decrease the delay between the HSYNC* pin and the
analog output by one clock cycle. The pixel-to-analog out timing is unaffected.
This makes the next pixel after the falling edge of HSYNC* the last Y of the
Cb/Y/Cr/Y sequence in 8-bit mode.

The CBSWAP bit will shift the sequence at the input such that the next sample
after the falling edge of HSYNC* will be the Cr sample of the Cb/Y/Cr/Y
sequence in 8-bit mode, or the Y/Cr sample pair in 16-bit mode. The relationship
between the HSYNC* pin and the analog output is unaffected, as is the
pixel-to-analog out timing.

1.0 Circuit Description Bt864A/865A

1.4 HSYNC* Timing YCrCb to NTSC/PAL Digital Video Encoder

1-6 Conexant 100138B

1.4 HSYNC* Timing

1.4.1 Master Mode

There are two HSYNC* timing modes in master mode; default mode and variable
HSYNC* timing mode. The variable HSYNC* timing mode is enabled by setting
ADJHSYNC high. This mode allows the user to specify the placement of the
falling and rising edges of HSYNC* by using the HSYNCF and HSYNCR
registers, respectively. The values of registers HSYNCF and HSYNCR
correspond to the pixel count of the internal pixel counter (see Figure 1-3).
HSYNCF and HSYNCR cannot be zero and cannot be equal. Values must also be
less than or equal to the total horizontal resolution given in Ta bl e 1- 2. If the
internal pixel counter resets before the rising edge occurs, the part will not
automatically reset, but will wait until the pixel counter reaches the specified
HSYNCR value. The placement of the analog horizontal sync pulse is fixed
relative to the internal pixel counter, therefore when the rising and falling edges of
HSYNC* are moved, the pipeline delay between the HSYNC* pulse and the
analog horizontal sync pulse is altered. In this mode, the pipeline delay from
HSYNC* to analog sync out is 40–(2*HSYNCF) if SYNCDLY = 0, and
41–(2*HSYNCF) if SYNCDLY = 1. In the default HSYNC* timing mode, the
placement of the edges of the HSYNC* pulse are fixed, with the exception of the
one clock delay available through the register SYNCDLY. In this mode, the
pipeline delay from HSYNC* to analog sync out is 40 clocks if SYNCDLY = 0,
and 41 clocks if SYNCDLY = 1. In the default mode, the delay from internal
horizontal pixel counter reset to the falling edge of HSYNC* is 2 clocks.

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.4 HSYNC* Timing

100138B Conexant 1-7

1.4.2 Slave Mode

Slave mode does not support a variable HSYNC* timing mode. The default
pipeline delay from the HSYNC* falling edge to analog sync out falling edge is
47 clocks if SYNCDLY = 0, and 46 clocks if SYNCDLY = 1. The default delay
from the falling edge of HSYNC* input to internal horizontal pixel counter reset
is 5 clocks. In both master and slave modes, the pixel data pipeline delay is 52
clocks.

Figure 1-3. HSYNC* Timing In Master Mode

NOTE(S):

(1)

One clock delay (1/2 pixel) of HSYNC* falling edge, using register SYNCDLY.

(2)

Falling edge of HSYNC* is definable in variable HSYNC* timing mode, using the register HSYNCF.

(3)

Rising edge of HSYNC* is definable in variable HSYNC* timing mode, using the register HSYNCR.

(4)

Maximum horizontal resolution (see Table 1-2 ).

5. Waveforms not to scale.

Internal Pixel

Clock/Counter

Internal

Horizontal Reset

HSYNC*

(1) (1)

Active
Video

Color
Burst

Analog Output

Video Waveform

Default

(2)

Default

(3)

Horizontal Sync

Pipeline Delay

Reset

Pixel Count

1 2 3 . . .

(4)

Pixel Count

1 2 3 . . .

(4)

(2)

1.0 Circuit Description Bt864A/865A

1.5 Video Timing YCrCb to NTSC/PAL Digital Video Encoder

1-8 Conexant 100138B

1.5 Video Timing

The width of the analog horizontal sync pulses and the start and end of color burst
are automatically calculated and inserted for each mode according to

ITU-RBT.470-3. Color burst is disabled on appropriate scan lines. Serration and

equalization pulses are generated on appropriate scan lines. In addition, rise and
fall times of sync, closed-caption data transitions, and the burst envelope are
internally controlled. Figures 1-4–1-12 show the timing characteristics for various

Bt864A/865A modes of operation.

Figure 1-4. Interlaced 525-Line (NTSC) Video Timing

NOTE(S): SMPTE line numbering convention rather than ITU-R BT.470-3 is used. EVBI = 0

227654

3

BURST PHASE

21

525524523

Analog
FIELD 1

Analog
FIELD 2

272271270269268267263262261 266265264

285

Analog
FIELD 3

BURST PHASE

Analog
FIELD 4

Burst Begins with Positive Half-Cycle

Burst Phase = Reference Phase = 180° Relative to B–Y

Burst Begins with Negative Half-Cycle
Burst Phase = Reference Phase = 180° Relative to B–Y

89

10

227654

321

525524523

89

10

272271270269268267263262261 266265264 285

RESET*

VSYNC*

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.5 Video Timing

100138B Conexant 1-9

Figure 1-5. Interlaced 525-Line (PAL-M) Video Timing

NOTE(S): SMPTE line numbering convention rather than ITU-R BT.470-3 is used. EVBI = 0.

RESET*

VSYNC*

227654

3

Burst Phase

21

525524523

Analog
FIELD 1

Analog
FIELD 2

272271270269268267263262261 266265264

Analog
FIELD 3

Burst Phase

Analog
FIELD 4

89

10

7654

321

525524523

89

272271270269268267263262261 266265264

Burst Phase = Reference Phase = 135° Relative to U
PAL Switch = 0, +V Component

Burst Phase = Reference Phase + 90° = 225° Relative to U
PAL Switch = 1, –V Component

11

12

22

11

12

285

274

273

285

274

273

10

1.0 Circuit Description Bt864A/865A

1.5 Video Timing YCrCb to NTSC/PAL Digital Video Encoder

1-10 Conexant 100138B

Figure 1-6. Interlaced 625-Line (PAL–B, D, G, H, I, Nc) Video Timing

NOTE(S): EVBI = 0.

2476543

– U PHASE

21622621620

Analog
FIELD 1

625624623 23

Analog
FIELD 2

337320318317316315314309308 312311 336

319

337320317316315314308 313312311 336319

310 313

309 318310

247654321622621620 625624623 23

FIELD One

FIELD Two

FIELD Three

FIELD Four

Burst
Blanking
Intervals

Burst Phase = Reference Phase = 135° Relative to U
PAL Switch = 0, +V Component

Burst Phase = Reference Phase + 90° = 225° Relative to U
PAL Switch = 1, –V Component

Analog
FIELD 3

Analog
FIELD 4

RESET*

VSYNC*

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.5 Video Timing

100138B Conexant 1-11

Figure 1-7. Interlaced 625-Line (PAL–B, D, G, H, I, Nc) Video Timing

NOTE(S): EVBI = 0.

2476543

– U PHASE

21622621620 625624623 23

337320318317316315314309308 312311 336319

337320317316315314308 313312311 336319

310 313

309 318310

247654321622621620 625624623 23

FIELD Five

FIELD Six

FIELD Seven

FIELD Eight

Burst
Blanking
Intervals

Burst Phase = Reference Phase = 135° Relative to U
PAL Switch = 0, +V Component

Burst Phase = Reference Phase + 90° = 225° Relative to U
PAL Switch = 1, –V Component

Analog
FIELD 6

Analog
FIELD 7

Analog
FIELD 8

Analog
FIELD 5

VSYNC*

1.0 Circuit Description Bt864A/865A

1.5 Video Timing YCrCb to NTSC/PAL Digital Video Encoder

1-12 Conexant 100138B

Figure 1-8. Interlaced 625-Line (PAL–N) Video Timing

NOTE(S): EVBI = 0.

247654321622621620 625624623 23

337320318317316315314309308 312311 336

337320317316315314308 313312311 336

24754321621620 625624623 23

– U PHASE

Analog
FIELD 1

Analog
FIELD 2

FIELD One

FIELD Two

FIELD Three

FIELD Four

Burst
Blanking
Intervals

Burst Phase = Reference Phase = 135° Relative to U
PAL Switch = 0, +V Component

Burst Phase = Reference Phase + 90° = 225° Relative to U
PAL Switch = 1, –V Component

Analog
FIELD 3

Analog
FIELD 4

RESET*

VSYNC*

310309

622

310 313 319

6

318 319

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.5 Video Timing

100138B Conexant 1-13

Figure 1-9. Interlaced 625-Line (PAL–N) Video Timing

NOTE(S): EVBI = 0.

2476543

– U PHASE

21622621620 625624623 23

337320318317316315314309308 312311 336319

337320317316315314308 313312311 336319

310 313

309 318310

247654321622621620 625624623 23

FIELD Five

FIELD Six

FIELD Seven

FIELD Eight

Burst
Blanking
Intervals

Burst Phase = Reference Phase = 135° Relative to U
PAL Switch = 0, +V Component

Burst Phase = Reference Phase + 90° = 225° Relative to U
PAL Switch = 1, –V Component

Analog
FIELD 6

Analog
FIELD 7

Analog
FIELD 8

Analog
FIELD 5

VSYNC*

1.0 Circuit Description Bt864A/865A

1.5 Video Timing YCrCb to NTSC/PAL Digital Video Encoder

1-14 Conexant 100138B

Figure 1-10. Noninterlaced 262-Line (NTSC) Video Timing

NOTE(S): CCIR 624 line numbering convention. EVBI = 0.

187651262261260 234259258

VSYNC*

RESET*

Figure 1-11. Noninterlaced 262-Line (PAL-M) Video Timing

NOTE(S): CCIR 624 line numbering convention. EVBI = 0.

18

7651

234 8 9262261260259258

VSYNC*

RESET*

10

Figure 1-12. Noninterlaced 312-Line (PAL-B, D, G, H, I, N, Nc) Video Timing

NOTE(S): EVBI = 0.

651311310309308 2 3 4312 22 2423

VSYNC*

RESET*

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.5 Video Timing

100138B Conexant 1-15

1.5.1 Reset

If the RESET* pin is held low during a single rising edge of CLK, the subcarrier
phase is set to zero, and the horizontal and vertical counters are held to the first
pixel and second line of FIELD1. Counting resumes on the first rising edge of
CLK after rising RESET*.

A software reset will occur immediately after writing a 1 to register SRESET.

This will reset all software-programmable register bits to zero.

On power-up, the Bt864A/865A will automatically perform a timing and
software reset. The power-up state has the following configuration: interlaced,
NTSC CCIR601 black burst (no active video), and zero chroma scaling. Setting
register EACTIVE will enable active video. On power-up, the DACs are disabled
for 8 fields or until register 0x67 (0xCE as 8-bit address) is written.

1.5.2 Sync and Burst Timing

Table 1 -2 lists the resolutions and clock rates for the various modes of operation.

Table 1 -3 lists the horizontal counter values for the end of horizontal sync,

start of color burst, end of color burst, and the first active pixel for the various
modes of operation. The front porch is the interval before the next expected
falling HSYNC* when outputs are automatically blanked.

The horizontal sync width is measured between the 50% points of the falling
and rising edges of horizontal sync.

The start of color burst is measured between the 50% point of the falling edge
of horizontal sync and the first 50% point of the color burst amplitude (nominally
+20 IRE for NTSC/PAL–M and 150 mV for PAL–B, D, G, H, I, N, Nc above the
blanking level).

The end of color burst is measured between the 50% point of the falling edge
of horizontal sync and the last 50% point of the color burst envelope (nominally
+20 IRE for NTSC/PAL–M and 150 mV for PAL–B, D, G, H, I, N, Nc above the
blanking level).

Table 1-2. Field Resolutions and Clock Rates for Various Modes of Operation

Operating Mode

Active Luminance Resolution

(pixels)

Total Resolution (pixels)

Luminance

Pixel

Frequency

(MHz)

Horizontal Vertical Horizontal Vertical

Porch = 0

Non

Interlaced

Field

Interlaced

Frame

Non

Interlaced

Interlaced

NTSC/PAL–M CCIR601
PAL–B, D, G, H, I, N, Nc
CCIR601
NTSC/PAL–M Square Pixel
PAL–B, D, G, H, I, N, Nc Square
Pixel

711
702
647
767

241
287
241
287

482
575
482
575

858 ± 1
864 ± 1
780 ± 1
944 ± 1

262 ± 1/4
312 ± 1/4
262 ± 1/4
312 ± 1/4

262.5 ± 1/4

312.5 ± 1/4

262.5 ± 1/4

312.5 ± 1/4

13.5000

13.5000

12.2727

14.7500

NOTE(S):

1. Tolerances apply to slave mode. Cumulative errors over color frame interval may result in subcarrier glitches.

2. Due to upsampling filter response, pixels near the boundary of the active definition will be reduced in amplitude due to
averaging with the blank level.

1.0 Circuit Description Bt864A/865A

1.5 Video Timing YCrCb to NTSC/PAL Digital Video Encoder

1-16 Conexant 100138B

1.5.3 Master Mode

Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are generated from
internal timing and from optional software bits. HSYNC* and VSYNC* are
output following the rising edge of CLK.

The HSYNC* output may be configured to have standard video timing (4.7

µs

wide, asserted at start of a line default after RESET cycle) or it may be
programmed to specify the start of HSYNC* (10-bit value) and the end of
HSYNC* (10-bit value). VSYNC* is asserted for 3 scan lines for 262/525 line
formats and 2.5 scan lines for 312/625 line formats (except for PAL-N which is 3
scan lines). When HSYNC* is configured for standard video timing, coincident
falling edges of HSYNC* and VSYNC* indicate the beginning of the first field
(CCIR convention). Auto mode detection is not applicable under master mode
operation.

Table 1-3. Horizontal Counter Values for Various Video Timings

Operating Mode

Horizontal Counter Value

Equalizatio

n Pulse

Width

Horizontal/

Serration

Pulse Width

Start of

Burst

Duration of

Burst

Back Porch

Front

Porch

(1)

HCN

T

µs

HCN

T

µs

HCN

T

µs

HCN

T

µs

HCN

T

µs

HCN

T

µs

NTSC CCIR601 32 2.3

7

63 4.6

7

72 5.3

3

34 2.52127 9.41 20 1.4

8

PAL–M CCIR601 32 2.3

7

63 4.6

7

78 5.7

8

34 2.52127 9.41 20 1.4

8

NTSC Square 29 2.3

6

58 4.7

3

65 5.3

0

31 2.53115 9.37 18 1.4

7

PAL–M Square 29 2.3

6

58 4.7

3

71 5.7

9

31 2.53115 9.37 18 1.4

7

PAL-B CCIR601 32 2.3

7

63 4.6

7

76 5.6

3

30 2.22142 10.5

2

20 1.4

8

PAL–N

c

CCIR601 32 2.3

7

63 4.6

7

76 5.6

3

34 2.52142 10.5

2

20 1.4

8

PAL–B Square 35 2.3

7

69 4.6

8

83 5.6

3

33 2.24155 10.5

1

22 1.4

9

PAL-N

c

Square

(2)

35 2.3

7

69 4.6

8

83 5.6

3

37 2.51155 10.5

1

22 1.4

9

NOTE(S):

(1)

In slave mode, since Front Porch timing is triggered by the previous HSYNC pulse, any deviation from nominal line length
can affect the front porch duration.

(2)

PAL-Nc refers to the PAL format used in Argentina (Combination N).

3. HCNT refers to the number of luminance pixel periods; there are twice as many CLK periods as HCNT periods.

4. Odd counts at front porch transitions indicate invalid chroma framing.

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.5 Video Timing

100138B Conexant 1-17

1.5.4 Slave Mode

The horizontal counter is incremented on every other rising edge of CLK. A
falling edge of HSYNC* resets it to one, indicating the start of a new line.

The vertical counter is incremented on the falling edge of HSYNC*. A falling
edge of VSYNC* resets it to one, indicating the start of a new field (interlaced
operation) or frame (noninterlaced operation).

A falling edge of VSYNC* that occurs within

±1/4 of a scan line from the

falling edge of HSYNC* indicates the beginning of FIELD 1. A falling edge of
VSYNC* that occurs within

±1/4 scan line from the center of the line indicates

the beginning of FIELD 2. Referring to Figures 1-4–1-12, start of VSYNC*
occurs on the falling HSYNC* at the beginning of the next expected FIELD 1 and
halfway between expected falling HSYNC* edges at the beginning of the next
expected FIELD 2.

HSYNC* and VSYNC* must remain low for at least 2 CLK cycles. The
operating mode (NTSC/PAL, interlaced/noninterlaced, square pixel/CCIR601,
and setup) is automatically determined when configured as a slave when the
SETMODE bit is zero. 525-line operation is assumed, unless 625-line operation
is detected by the number of lines in a field. Interlaced operation is detected by
observing the sequence of FIELD 1 or FIELD 2; if the field timing (odd follows
odd, even follows even) is repeated, then noninterlaced mode is assumed. The
frequency of operation (square pixels or CCIR) is detected by counting the
number of clocks per line. The pixel rate is assumed to be 13.5 MHz unless the
exact horizontal count for square pixels, ±1 count, is detected in between two
successive falling edges of HSYNC*.

NOTE: Square pixel 625-line operation with this sequence requires one frame to

stabilize.

By setting SETMODE = 1, the video format control register bits (VIDFORM
[3:0], SETUPDIS, NONINTL, and SQUARE) will determine the operating mode.

1.5.5 FIELD Output

The FIELD output indicates whether FIELD 1 (logical zero) or FIELD 2 (logical
one) is being generated. This corresponds directly to the “bottom/top” convention
of some MPEG decoders. Field changes occur one CLK cycle after the falling
edge of VSYNC*. FIELD is output following the rising edge of CLK. Unless
special HSYNC* timing is programmed, FIELD output transitions low four CLK
periods following the falling edge of HSYNC* at the beginning of FIELD 1.

To invert the sense of the FIELD output, set the FIELDI bit to a logical one.

1.5.6 Pixel Blanking

BLANK* is registered on the rising edge of CLK. For video outputs, BLANK* is
pipelined to match the luminance and chrominance paths and is applied to the
digital video before analog conversion. The automatic horizontal blanking
sequence described in Table 1-3 takes precedence over the BLANK* input.

1.0 Circuit Description Bt864A/865A

1.5 Video Timing YCrCb to NTSC/PAL Digital Video Encoder

1-18 Conexant 100138B

1.5.7 Burst Blanking

For interlaced NTSC, color burst information is automatically disabled on scan
lines 1–9 and 264–272, inclusive. (SMPTE line numbering convention.)

For interlaced PAL-M color burst information is automatically disabled on
scan lines 1–11 and 263–273 and 525 of FIELD 1 and FIELD 2 and scan lines
1–10 and 262–272 of FIELDs 3 and 4.

For interlaced PAL–B, D, G, H, I, N, Nc, color burst information is
automatically disabled on scan lines 1–6, 310–318, and 623–625, inclusive, for
FIELDs 1, 2, 5, and 6. During FIELDs 3, 4, 7, and 8, color burst information is
disabled on scan lines 1–5, 311–319, and 622–625, inclusive.

For noninterlaced NTSC, color burst information is automatically disabled on
scan lines 1–6 and 260–262, inclusive.

For noninterlaced PAL-M, color burst information is automatically disabled
on scan lines 1–10 and 260–262.

For noninterlaced PAL–B, D, G, H, I, N, Nc, color burst information is
automatically disabled on scan lines 1–6 and 310–312, inclusive. See

Figures 1-4–1-12.

1.5.8 Digital Processing

The input is scaled to YUV format. For the CVBS, Y, and C outputs, the UV
components are low-pass filtered with a filter response shown in Figures 1-13 and

1-14 (linearly scalable by clock frequency). The Y and filtered UV components

are upsampled to CLK frequency by a digital filter whose response is shown in

Figures 1-15 and 1-16. For the RGB outputs, the scaled YUV is color space

converted and output.

1.5.9 Chrominance Disable

The chrominance subcarrier may be turned off by setting the DCHROMA bit to a
logical one. This kills burst as well, providing luminance only signals on the
CVBS outputs and a static blank level on the C/R output (RGBOUT = 0).

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.5 Video Timing

100138B Conexant 1-19

Figure 1-13. Three-Stage Chrominance Filter

Figure 1-14. Three-Stage Chrominance Filter (Passband)

Attenuation (dB)

Frequency (MHz)

CLK = 27 MHz

Attenuation (dB)

Frequency (MHz)

CLK = 27 MHz

1.0 Circuit Description Bt864A/865A

1.5 Video Timing YCrCb to NTSC/PAL Digital Video Encoder

1-20 Conexant 100138B

Figure 1-15. Luminance 2X Upsampling Filter Response

Figure 1-16. Luminance 2X Upsampling Filter Response (Passband)

Attenuation (dB)

Frequency (MHz)

CLK = 27 MHz

Attenuation (dB)

Frequency (MHz)

CLK = 27 MHz

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.5 Video Timing

100138B Conexant 1-21

1.5.10 Subcarrier Phasing

In order to maintain correct SC-H phasing, the subcarrier phase is set to zero on
the falling edge of HSYNC* associated with VSYNC* every four (NTSC) or
eight (PAL) fields, unless the SCRESET bit is set to a logical one.

In slave mode, falling HSYNC* may lag falling VSYNC* by 1/4 scan line but
cannot precede falling VSYNC* by more than seven CLK periods for correct
SC-H reset.

Setting SCRESET to one may be useful in situations where the ratio of CLK/2
to HSYNC* edges in a color frame is noninteger, which could produce a
significant phase impulse by resetting to zero.

1.5.11 Vertical Blanking Intervals

For interlaced NTSC/PAL–M, if EVBI = 0, scan lines 1–21 and 263–284,
inclusive, are always blanked regardless of the BLANK* input (SMPTE line
numbering convention).

For interlaced PAL–B, D, G, H, I, N, Nc, if EVBI = 0, scan lines 1–23,
311–335, and 624–625, inclusive, are always blanked regardless of the BLANK*
input.

For noninterlaced NTSC/PAL–M, if EVBI = 0, scan lines 1–17 and 261–262,
inclusive, are always blanked regardless of the BLANK* input. For noninterlaced
PA L –B, D, G, H, I, N, Nc, if EVBI = 0, scan lines 1–22 and 311–312, inclusive,
are always blanked regardless of the BLANK* input.

Alternately, all displayed lines in the vertical blanking interval (10–21 and
273–284 for interlaced NTSC/PAL–M; 6–23 and 320–335 for interlaced PAL–B,
D, G, H, I, N, Nc; 10–21 for noninterlaced NTSC/PAL–M, 7–23 for noninterlaced
PA L –B, D, G, H, I, N, Nc) may be enabled by setting the EVBI bit to a logical one
(except for caption lines controlled by bits ECCF1 or ECCF2, or the Macrovision
process).

1.5.12 BLANK* Pin

The BLANK* pin can be used to BLANK any portion of the active display lines
(including those enabled by EVBI) by driving the pin to a logical zero.

1.5.13 Noninterlaced Operation

When the Bt864A/865A is programmed for noninterlaced master mode, the
Bt864A/865A always displays FIELD 1, meaning that the falling edges of
HSYNC* and VSYNC* will be output coincidentally. FIELD will be held low if
FIELDI = 0. Additionally, a 30 Hz offset will be subtracted from the color
subcarrier frequency while in NTSC mode so that the color subcarrier phase will
be inverted from field to field.

Transition from interlaced to noninterlaced in master mode, occurs during
FIELD 1 to prevent synchronization disturbance. In slave mode, transition occurs
after a subsequent falling edge of VSYNC*.

NOTE: Consumer VCRs can record noninterlaced video with minor noise

artifacts, but special effects (e.g., scan > 2x) may not function properly.

1.0 Circuit Description Bt864A/865A

1.6 Power Saving Modes YCrCb to NTSC/PAL Digital Video Encoder

1-22 Conexant 100138B

1.6 Power Saving Modes

In SLEEP power-down mode (SLEEP pin set to 1), all analog and digital circuitry
is disabled, and total device current consumption approaches 0 mA. Register
states are preserved, but other chip functionality (including I

2

C communication)
is disabled. This mode should be set when the Bt864A/865A may be subjected to
clock and data frequencies outside its functional range.

In DACOFF power-down mode, (DACOFF register is set to 1) all DACs are
disabled and analog current is reduced to approximately 0 mA. All other digital
circuitry remains operational, permitting system timing and other functions to
continue.

When DACs are disabled by either SLEEP or DACOFF, VREF will go to
approximately 0.5 V below VAA.

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.7 Pixel Input Ranges and Colorspace Conversion

100138B Conexant 1-23

1.7 Pixel Input Ranges and Colorspace
Conversion

1.7.1 YC Inputs (4:2:2 YCrCb)

Y has a nominal range of 16–235; Cb and Cr have a nominal range of 16–240,
with 128 equal to zero. Values of 0 and 255 are interpreted as 1 and 254,
respectively. Y values of 1–15 and 236–254, and CrCb values of 1–15 and
241–254, are interpreted as valid linear values.

The SETUPDIS bit will alter pixel scaling and disable or enable the 7.5 IRE
setup. When this bit is enabled, PAL–B, D, G, H, I, N, Nc video can be generated
using NTSC/PAL–M blanking levels and 7.5 IRE setup, and NTSC/PAL–M pixel
scaling is performed (Y range of 16–235 represents 7.5–100 IRE); or,
NTSC/PAL–M video can be generated using PAL–B, D, G, H, I, N, Nc scaling (Y
range of 16–235 represents 0–100 IRE) without the 7.5 IRE setup. NTSC/PAL–M
mode with setup disabled has 2% less black-to-white range than NTSC/PAL–M
mode with setup enabled.

For RGBOUT mode, 4:2:2 YCrCb digital component video will be upsampled
to 4:4:4 and used to generate composite video and will be converted to the RGB
colorspace to drive the RGB DACs. The Y input range of 16–235 will produce a
range of 0.7 V at the output. Since YC values outside of the nominal range are
allowed, the black level is raised above zero volts to allow for Y values less than
16, and the output range of the DACs can exceed 0.7 V to allow for Y values
above 235. The conversion is linearly scaled in the overshoot and undershoot
regions. The following matrix, based on CCIR601, is used to convert YCrCb to
RGB:

R = Y + 1.371*Cr

G = Y – 0.699*Cr – 0.337*Cb

B = Y + 1.733*Cb

Values are rounded to 9 bits at the DAC.

1.7.2 DAC Coding

For all video formats, the input luma and chroma values are scaled internally such
that, after sync and setup (if enabled) are added, the output from sync to 100%
white (for CVBS/Y outputs) is approximately 1.00 V.

In addition, the chroma is boosted to compensate for the sinx/x rolloff due to
the DAC (see Figures 1-17 and 1-18). The amount of boost is determined by
SETUPDIS. Ta bl e 1- 4 summarizes the blank, black, and 100% white DAC codes
and chroma gain values as a function of SETUPDIS.

Table 1-4. DAC Coding

SETUPDIS Blank Black 100% White Chroma Gain

0 228 272 801 1.02944

1 224 224 800 1.0458

1.0 Circuit Description Bt864A/865A

1.7 Pixel Input Ranges and Colorspace Conversion YCrCb to NTSC/PAL Digital Video Encoder

1-24 Conexant 100138B

Figure 1-17. DAC Sinx/x Response

Figure 1-18. DAC Sinx/x Response (Passband)

Attenuation (dB)

Frequency (MHz)

CLK = 27 MHz

Attenuation (dB)

Frequency (MHz)

CLK = 27 MHz

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.8 Closed Captioning

100138B Conexant 1-25

1.8 Closed Captioning

The Bt864A/865A encodes NTSC/PAL–M closed captioning on scan line 21 and
NTSC/PAL–M extended data services on scan line 284. Four 8-bit registers
(CCF1B1, CCF1B2, CCF2B1, and CCF2B2) provide the data while bits
ECCF1and ECCF2 enable display of the data. A logical zero corresponds to the
blanking level of 0 IRE, while a logical one corresponds to 50 IRE above the
blanking level.

Closed captioning for PAL–B, D, G, H, I, N, Nc is similar to that for NTSC.
Closed caption encoding is performed for 625-line systems according to the
system proposed by the National Captioning Institute; clock and data timing is
identical to that of NTSC system, except that encoding is provided on lines 22
and 335.

The Bt864A/865A generates the clock run-in and appropriate timing
automatically. Pixel inputs are ignored during CC encoding. See FCC Code of
Federal Regulations (CFR) 47 Section 15.119 (10/91 edition or later) for
programming information. EIA608 describes ancillary data applications for
FIELD 2 Line 21 (line 284).

When CCF1B2 is written, CCSTAT1 is set; when CCF2B2 is written
CCSTAT2 is set (CCSTAT1 and CCSTAT2 are defined in Table 2-1). After the
closed-caption bytes for FIELD 1 are encoded, CCSTAT1 is cleared; after the
closed-caption bytes for FIELD 2 are encoded, CCSTAT2 is cleared. If the
ECCGATE bit is set, no further encoding will be performed until the appropriate
registers are again written; a NULL with odd parity will be transmitted on the
appropriate closed caption line in that case. User must set the odd parity bit. If the
ECCGATE bit is not set, the user must rewrite the closed-caption registers prior to
reaching the closed-caption line, otherwise the last bytes will be re-encoded.

Closed-caption will override EVBI inserted data on lines 21 and 284 for
525-line formats, and lines 22 and 335 for 625-line formats. Closed-caption will
be overridden by teletext if teletext is enabled on these lines.

Closed caption data registers are double buffered and can be loaded without
the risk of corrupting data as it is being encoded onto the appropriate video line
(line 21 or 284 for 525-line formats, line 22 or 335 for 625-line formats).

1.0 Circuit Description Bt864A/865A

1.9 Teletext YCrCb to NTSC/PAL Digital Video Encoder

1-26 Conexant 100138B

1.9 Teletext

Teletext encoding is accomplished via a two-wire interface, TTXDAT and
TTXREQ, and internal registers that are programmed through the I

2

C interface.
Teletext encoding in the Bt864A/865A conforms to Teletext B for 625/50
television systems. See “Recommendation 653-1 Teletext Systems” for further
information about the standard. Teletext should be disabled for 525-line television
systems.

The internal registers allow for the enable/disable of teletext and the
programming of the start and stop of the TTXREQ signal, the active teletext lines
in an FIELD 1, and the active teletext lines in FIELD 2. Active teletext lines
override closed caption, Macrovision, the BLANK* input, and active video. See
the “Internal Registers” section for more details.

The TTXREQ signal is generated by the encoder to indicate to external
devices when teletext data is required. The start and end of the TTXREQ signal
waveform is determined by the value of registers TXHS and TXHE, respectively.
The values of registers TXHS and TXHE correspond to the internal clock (CLK)
counter (see Figure 1-19). The proper selection of these edges will allow the user
to adjust for the propagation delay of the teletext source, so that the teletext data is
provided to the TTXDAT pin at the proper time. If the falling edge of TTXREQ
does not occur by the end of the video line, the beginning of the new video line
will automatically reset TTXREQ. Legal values for these registers are given in

Table 1 -5 .

The data to TTXDAT is sampled on every rising input clock edge and must
meet the following protocol for proper teletext data insertion. The protocol
demands that the teletext data bit duration is the required number of CLKs.

Internal to the chip is a sequencer and a data shaper to minimize the jitter.
Using the midpoint of the falling edge of the horizontal sync pulse as it appears at
the output Y/CVBS or CVBS/G, the teletext data protocol must begin 262 to 264
CLKs later for CCIR601(13.5 MHz pixel rate) or 286 to 288 CLKs later for
Square Pixel Operation (14.75 MHz pixel rate). Relative to the internally
generated teletext window, the protocol must start 5 to 7 clocks earlier. The
teletext window begins at 10.2 µsec from the horizontal sync pulse's falling edge
and the data rate is the specified 6.9375 Mbits/sec.

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.9 Teletext

100138B Conexant 1-27

Figure 1-19. Teletext Timing for Bt864A/865A Encoder

NOTE(S):

(1)

Placement of rising edge of TTXREQ is definable using register TXHS[10:0].

(2)

Placement of falling edge of TTXREQ is definable using register TXHE[10:0].

(3)

TTXREQ is generated by the encoder using programmable registers TXHS and TXHE. This allows the user to adjust for the
propagation delay (t

PD

) in CLK cycles of the teletext data source.

(4)

TTXDAT is supplied to the encoder at the proper time to be interpolated by the encoder (t

TTXINT

) and inserted into the video

output signals. The Teletext data must follow the correct protocol. See “Te le te xt ” on page 1-26.

(5)

t

TTXOWS

is the start of the teletext output window and is fixed internally by the encoder at 10.2 µsec.

(6)

Luma Delay is set to zero.

(7)

t

TTXIWS

is the start of the teletext input window and is fixed internally.

(8)

If the falling edge of TTXREQ does not occur by the end of a video line, the beginning of a new line will automatically reset
TTXREQ.

(9)

2 clock (CLK) counts = 1 pixel clock count.

10. TXE is enabled and video line is a valid teletext line. See “Teletext” on page 1-26.

TTXREQ

TTXDAT

CVBS/B

(6)

CVBS/G

Y/CVBS

t

PD

(3)

t

TTXINT

(4)

t

TTXOWS

(5)

Internal

t

TTXIWS

(7)

. . .

. . .

2 3 5 . . .4

(8)

2 3 5 . . .4

Horizontal

Reset

Internal

Clock (CLK)

Counter

(9)

(1) (2)

Table 1-5. Legal Values to TXHS and TXHE

Pixel rate TXHS TXHE

Min. Value 13.5 MHz 2 TXHS + 2

Max. Value 13.5 MHz 0X6BE 0X7FF

Min. Value 14.75 MHz 2 TXHS + 2

Max. Value 14.75 MHz 0X75E 0X7FF

1.0 Circuit Description Bt864A/865A

1.9 Teletext YCrCb to NTSC/PAL Digital Video Encoder

1-28 Conexant 100138B

1.9.1 CCIR601 Operation (13.5 MHz pixel rate)

The bit duration follows this pattern which repeats every 37 teletext bits. Each
teletext data bit is carried by four CLKs except bits 10, 19, 28, and 37 which are
three CLKs in duration. This pattern continues until all 360 bits (1402 CLKs)
have been transferred.

1.9.2 Square Pixel Operation (14.75 MHz pixel rate)

This bit pattern repeats after every 111 teletext bits: After every teletext bit that is
carried by five CLKs the next three teletext bits are carried by four CLKs except
for the first bit of the pattern which is five CLKs in duration and only the next two
bits are carried by four CLKs. This pattern continues until all 360 bits (1531
CLKs) have been transferred. The repeating bit duration pattern starting at bit 1
would be:

1.9.3 Teletext Clock Generation

Figure 1-20 shows how to generate a teletext clock using a P:Q ratio counter for

shifting out the teletext data serially to the Bt864A/865A. The diagram is for
illustrative purposes only. The actual implementation is left to the user.

Bit number: 12345678910 11 12 13 14 15...
Duration in CLKs: 5445444544 4 5 4 4 4...

Figure 1-20. PQ Ratio Counter

Table 1-6. Teletext Clock P and Q Values

CLK Pixel Rate P Q

27 MHz 13.5 MHz 37 144

29.5 MHz 14.75 MHz 111 472

CLK

P

MODULO

Q

REGISTER

RSTN

ENABLE_TTX_CLK

Teletext Clock

ADDER

A

B

SUM

CO

DQ

CLK

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.10 Wide Screen Signaling (WSS)/Copy Generation Management System

100138B Conexant 1-29

1.9.4 Teletext Clock Output

The Bt864A/865A can output the teletext clock from the TTXREQ pin by setting
TXRM = 1. In this mode, this teletext clock would only be output on active
teletext lines and each line would have exactly 360 clocks to be used to
synchronize the teletext data to the Bt864A/865A. The rising edge of clock could
be used to latch the data on the output of the device providing the teletext data.
The falling of the clock indicates that the Bt864A/865A has received the teletext
data.

1.10 Wide Screen Signaling (WSS)/Copy
Generation Management System (CGMS)
Encoding

The Bt864A/865A encodes the WSS/CGMS into the appropriate video line
according to EIAJ CPX-1204. The interface consists of 3 8-bit I

2

C registers into
which is written the individual enables for lines 20 and 283 (EWSF1 and EWSF2)
and the 20 bits of data (WSDAT [1:20]). These I

2

C registers are double-buffered
and can be written without corrupting any data actively being encoded on line 20
or 283. When updating any of the WSS/CGMS registers, all 3 8-bit I

2

C registers
should be written at the same time; the internal data transfer occurs after the last
WSS/CGMS register is written. WSS/CGMS encoding will override active video
if enabled by EVBI.

Figure 1-21. Typical WSS/CGMS Waveform

20 bits

70 IRE nom

Word0 Word1 Word2 CRCC

bit1

bit20

2.235 µs

11.2 µs

0 IRE nom

49.1 µs

1.0 Circuit Description Bt864A/865A

1.11 Anticopy Process (Bt865A Only) YCrCb to NTSC/PAL Digital Video Encoder

1-30 Conexant 100138B

1.11 Anticopy Process (Bt865A Only)

The anticopy process contained within the Bt865A is implemented according to
the Macrovision version 7 specification developed by Macrovision Corporation in
Sunnyvale, California. All luminance, chrominance, and composite video
waveforms include the Macrovision Anticopy Process. The Bt865A incorporates
an anticopy process technology that is protected by U.S. patents and other
intellectual property rights. The anticopy process is licensed for noncommercial,
home use only. Reverse engineering or disassembly is prohibited.

Conexant cannot ship Bt865A encoders to any customer until that customer
has been licensed by Macrovision. Contact Macrovision Corporation to facilitate
this license agreement. Parties who have obtained a Macrovision license may
receive the Bt865A Macrovision Supplement by contacting Conexant.

1.12 Internal Color Bars

The Bt864A/865A can be configured to internally generate colorbar test patterns
(100/7.5/75/7.5 with SETUPDIS = 0 for NTSC/PAL-M,N; 100/0/75/0 with
SETUPDIS = 1 for NTSC–Japan, PAL, BDGHI, Nc).

Internal color bars can be enabled by setting the ECBAR bit to a logical one.
In 8-bit YCrCb mode, setting the Y[7] pin to a logical one also enables color bars,
thereby simplifying testing of various modes. Internal color bars can be enabled
in all video formats.

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.13 SCART/PeriTV Support

100138B Conexant 1-31

1.13 SCART/PeriTV Support

RGBOUT mode can be enabled by setting the RGBOUT pin to a logical one, or
by setting register bit RGBO. The Bt864A/865A can generate analog RGB video
signals to interface to a SCART/PeriTV connector (see Table 1 -7 ). Composite
video will be present on the Y/CVBS DAC. RGB outputs are nominally
700 mVpp (black to white without setup).

1.14 I2C Interface

A simplified I2C (7-bit subaddress, 100 Kbps) interface is provided for
programming the registers. CLK must be applied and remain stable for I

2

C

communication. Activating SLEEP or RESET* will disable I

2

C communication.

1.15 Analog Outputs

All digital-to-analog converters are designed to drive standard video levels into a
combined RLOAD of 37.5 ¾. Unused outputs should be connected directly to
ground to minimize supply switching currents. In standard mode, one S-Video
(Y/C), and two composite video outputs are available. In RGBOUT mode, one
composite video output along with analog RGB are available (see Tab le 1 -7 ). If
the SLEEP pin is high or DACOFF = 1, the DACs are essentially turned off and
only the leakage current is present. The D/A converter values for 100%
saturation, 100% amplitude color bars are shown in Figures 1-22–1-27. Both
composite video and analog RGB video (to provide support for SCART/PeriTV)
may be generated simultaneously.

Table 1-7. DAC Output Cross-Reference

DAC Name

Pin Number Pin Function

Signal AGND Std Mode RGB Out Mode

CVBS/B 8 6 CVBS B

CVBS/G 10 7 CVBS G

C/R 12 9 C R

Y/CVBS 13 11 Y CVBS

1.0 Circuit Description Bt864A/865A

1.15 Analog Outputs YCrCb to NTSC/PAL Digital Video Encoder

1-32 Conexant 100138B

1.15.1 Luminance or CVBS (Y/CVBS) Output

Digital luminance information drives the 10-bit D/A converter that generates the
analog Y video output (Figures 1-22 and 1-23 and Ta bles 1 -8 and 1-9). This DAC
can also provide CVBS for SCART/PeriTV synchronization when RGBOUT is
enabled.

1.15.2 Chrominance or Red (C/R) Output

Digital chrominance information drives the 10-bit D/A converter that generates
the analog C video output (Figures 1-24 and 1-25 and Tables 1-10 and 1-11). This
DAC can also provide Red for SCART/PeriTV when RGBOUT is enabled.

1.15.3 Composite Video or Blue (CVBS/B) Output

Digital composite video information drives the 10-bit D/A converter that
generates the analog NTSC or PAL video output (Figures 1-26 and 1-27 and

Tables 1-12 and 1-13). This DAC can also provide Blue for SCART/PeriTV when

RGBOUT is enabled. An optional luminance delay can be enabled on this pin (in
standard mode only) by setting the LUMADLY bits. The luma can be delayed 0 to
3 pixels (up to 200–245 ns) to compensate for group delays introduced in the
chroma path by external filters or vestigial sideband processing.

1.15.4 Composite Video or Green (CVBS/G) Output

Digital composite video information drives the 10-bit D/A converter that
generates the analog video output (Ta ble 1 -1 4). This DAC can also provide Green
for SCART/PeriTV when RGBOUT mode is enabled.

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.15 Analog Outputs

100138B Conexant 1-33

Figure 1-22. Y (Luminance) Video Output Waveform SETUPDIS = 0

NOTE(S): Typical with 37.5 ¾ load, nominal RSET. SMPTE 170 M levels are assumed. 100% saturation color bars

(100/7.5/100/7.5) are shown.

26.68 1.000

mA V

0.00 0.000

9.07 0.340

7.60 0.285

White

Ye l l o w

Cyan

Green

Magenta

Red

Blue

Black

White Level

Black Level
Blank Level

Sync Level

100 IRE

40 IRE

7.5 IRE

801

790

644

583

489

429

332

Table 1-8. Y (Luminance) Video Output Truth Table SETUPDIS = 0

Description Iout (mA) DAC Data Sync Interval BLANK*

(1)

White 26.68 801 0 1

Black 9.07 272 0 1

Blank 7.60 228 0 0

Sync 0 0 1 0

NOTE(S):

(1)

BLANK occurs by external BLANK* pin or internally generated BLANK.

2. Typical with 37.5 ¾ load, nominal RSET, and setup on. SMPTE 170 M levels are assumed. 100% saturation color bars
(100/7.5/100/7.5) are shown.

1.0 Circuit Description Bt864A/865A

1.15 Analog Outputs YCrCb to NTSC/PAL Digital Video Encoder

1-34 Conexant 100138B

Figure 1-23. Y (Luminance) Video Output Waveform SETUPDIS = 1

NOTE(S): Typical with 37.5 ¾ load and nominal RSET. ITU-RBT.470-3 levels are assumed. 100% saturation (100/0/100/0)

color bars are shown.

26.68 1.000

mA V

0.00 0.000

8.0 0.300

White

Ye l l o w

Cyan

Green

Magenta

Red

Blue

Black

White Level

Black/Blank Level

Sync Level

800

736

634

570

470

406

304

Table 1-9. Y (Luminance) Video Output Truth Table SETUPDIS = 1

Description Iout (mA) DAC Data Sync Interval BLANK*

(1)

White 28.68 800 0 1

Black 8.00 240 0 1

Blank 8.00 240 0 0

Sync 0 0 1 0

NOTE(S):

(1)

BLANK occurs by external BLANK* pin or internally generated BLANK.

2. Typical with 37.5 ¾ load and nominal RSET. ITU-RBT.470-3 levels are assumed. 100% saturation (100/0/100/0) color bars
are shown.

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.15 Analog Outputs

100138B Conexant 1-35

Figure 1-24. C (Chrominance) Video Output Waveform SETUPDIS = 0

NOTE(S): Typical with 37.5 ¾ load, nominal RSET, and chroma on. SMPTE 170 M levels are assumed. 100% saturation color

bars (100/7.5/100/7.5) are shown.

White

Ye l l o w

Cyan

Green

Magenta

Red

Blue

Black

Color Burst

(9 Cycles)

20 IRE

20 IRE

28.21 1.058

mA V

5.93 0.222

20.88 0.783

17.07 0.640

13.27 0.498

Blank
Level

Table 1-10. C (Chrominance) Video Output Truth Table SETUPDIS = 0

Description Iout (mA) DAC Data Sync Interval BLANK*

(1)

Peak Chroma (High) 28.21 [25.56] 856 [770] x 1

Burst (High) 20.88 [20.88] 629 [629] x x

Blank 17.07 [17.07] 512 [512] x 0

Burst (Low) 13.27 [13.27] 395 [395] x x

Peak Chroma (Low) 5.93 [8.53] 168 [254] x 1

NOTE(S):

(1)

BLANK occurs by external BLANK* pin or internally generated BLANK.

2. Typical with 37.5 ¾ load, nominal RSET, and chroma on. SMPTE 170 M levels are assumed. 100% saturation color bars
(100/7.5/100/7.5) are shown.

3. Bracketed values indicate expected values when using the internal color bars (100/7.5/75/7.5).

1.0 Circuit Description Bt864A/865A

1.15 Analog Outputs YCrCb to NTSC/PAL Digital Video Encoder

1-36 Conexant 100138B

Figure 1-25. C (Chrominance) Video Output Waveform SETUPDIS = 1

NOTE(S): Typical with 37.5 ¾ load, nominal RSET, and chroma on. ITU-RBT.470-3 levels are assumed. 100% saturation

(100/0/100/0) color bars are shown.

White

Ye l l o w

Cyan

Green

Magenta

Red

Blue

Black

Color Burst

(10 Cycles)

28.88 1.083

mA V

5.27 0.198

21.08 0.791

17.07 0.640

13.07 0.490

Blank
Level

Table 1-11. C (Chrominance) Video Output Truth Table SETUPDIS = 1

Description Iout (mA) DAC Data Sync Interval BLANK*

(1)

Peak Chroma (High) 28.88 [26.06] 877 [785] x 1

Burst (High) 21.08 [21.08] 635 [635] x x

Blank 17.07 [17.07] 512 [512] x 0

Burst (Low) 13.07 [13.07] 389 [389] x x

Peak Chroma (Low) 5.27 [7.97] 147 [239] x 1

NOTE(S):

(1)

BLANK occurs by external BLANK* pin or internally generated BLANK.

2. Typical with 37.5 ¾ load, nominal RSET, and chroma on. ITU-RBT.470-3 levels are assumed. 100% saturation (100/0/100/0)
color bars are shown.

3. Bracketed values indicate expected values when using the internal color bars (100/0/75/0).

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.15 Analog Outputs

100138B Conexant 1-37

Figure 1-26. CVBS (Composite) Video Output Waveform SETUPDIS = 0

NOTE(S): Typical with 37.5 ¾ load, nominal RSET, clipping off, and chroma on. SMPTE 170 M levels are assumed. 100%

saturation color bars (100/7.5/100/7.5) are shown.

32.55 1.221

mA V

0.00 0.000

9.07 0.340

White

Ye l l o w

Cyan

Green

Magenta

Red

Blue

Black

White Level

Black Level

Blank Level

Sync Level

(9 Cycles)

Color Burst

26.68 1.000

34 IRE

100 IRE

20 IRE 7.5 IRE

20 IRE

40 IRE

3.80 0.143

7.60 0.285

11.41 0.423

801

740

644

583

489

429

332

3.20 0.120

Table 1-12. CVBS (Composite) Video Output Truth Table SETUPDIS = 0

Description Iout (mA) DAC Data Sync Interval BLANK*

(1)

Peak Chroma (High) 32.55 [30.38] 988 [922] 0 1

White 26.68 [26.68] 801 [801] 0 1

Burst (High) 11.41 [11.41] 345 [345] 0 x

Black 9.07 [9.07] 272 [272] 0 1

Blank 7.60 [7.60] 228 [228] 0 0

Burst (Low) 3.80 [3.80] 111 [111] 0 x

Peak Chroma (Low) 3.20 [5.32] 85 [149] 0 1

Sync 0 [0] 0 [0] 1 0

NOTE(S):

(1)

BLANK occurs by external BLANK* pin or internally generated BLANK.

2. Typical with 37.5 ¾ load, nominal RSET, clipping off, and chroma on. SMPTE 170 M levels are assumed. 100% saturation
color bars (100/7.5/100/7.5) are shown.

3. Bracketed values indicate expected values when using the internal color bars (100/7.5/75/7.5).

1.0 Circuit Description Bt864A/865A

1.15 Analog Outputs YCrCb to NTSC/PAL Digital Video Encoder

1-38 Conexant 100138B

Figure 1-27. CVBS (Composite) Video Output Waveform SETUPDIS = 1

NOTE(S): Typical with 37.5 ¾ load, nominal RSET, and clipping off. ITU-RBT.470-3 levels are assumed. 100% amplitude,

100% saturation (100/0/100/0) color bars are shown.

32.88 1.233

mA V

0.00 0.000

26.68 1.000

1.80 0.068

4.00 0.150

8.00 0.300

White

Yellow

Cyan

Green

Magenta

Red

Blue

Black

White Level

Black/Blank

SYNC LEVEL

(10 Cycles)

Color Burst

Level

12.01 0.450

800

736

634

570

470

406

304

Table 1-13. CVBS (Composite) Video Output Truth Table SETUPDIS = 1

Description Iout (mA) DAC Data Sync Interval BLANK*

(1)

Peak Chroma (High) 32.88 [30.61] 998 [929] 0 1

White 26.68 [26.68] 800 [800] 0 1

Burst (High) 12.01 [12.01] 363 [363] 0 x

Black 8.00 [8.00] 240 [240] 0 1

Blank 8.00 [8.00] 240 [240] 0 0

Burst (Low) 4.00 [4.00] 117 [117] 0 x

Peak Chroma (Low) 1.80 [3.76] 41 [110] 0 1

Sync 0 [0] 0 [0] 1 0

NOTE(S):

(1)

BLANK occurs by external BLANK* pin or internally generated BLANK.

2. Typical with 37.5 ¾ load, nominal RSET, and clipping off. ITU-RBT.470-3 levels are assumed. 100% amplitude, 100%
saturation (100/0/100/0) color bars are shown.

3. Bracketed values indicate expected values when using the internal color bars (100/0/75/0).

Bt864A/865A 1.0 Circuit Description

YCrCb to NTSC/PAL Digital Video Encoder

1.15 Analog Outputs

100138B Conexant 1-39

Table 1-14. RGB Output Table (RGBOUT = 1)

Description

SETUPDIS = 1 SETUPDIS = 0 BLANK*

(1)

Iout (mA) DAC Data Iout (mA) DAC Data

White 18.68 560 18.68 560 1

Black 0 0 1.47 44 1

Blank 0000 0

NOTE(S):

(1)

BLANK occurs by external BLANK* pin or internally generated BLANK.

2. Iout typical with 37.5 ¾ load, nominal RSET.

1.0 Circuit Description Bt864A/865A

1.15 Analog Outputs YCrCb to NTSC/PAL Digital Video Encoder

1-40 Conexant 100138B

100138B Conexant 2-1

2

2.0 Internal Registers

A read-back bit map is given in Ta ble 2-1, and a register bit map is given in Ta ble 2 -2 . Bit descriptions and
detailed programming information follow the bit map. All registers are write-only and are set to zero following
a software reset. A software reset is always performed at power-up; after power-up, a reset can be triggered by
writing the SRESET register bit. Figure 3-5 illustrates timing required for I

2

C communications.

2.1 Essential Registers

The power-up state is defined to be black burst CCIR601 NTSC video. To enable active video, the EACTIVE
register bit must be set.

2.2 Important Registers

The default video format is interlaced 8-bit CCIR601 NTSC. Other video formats can be enabled only by
programming the four following registers: 0x53, 00x65, 0x66, and 0x67. Other registers may need to be
programmed to get the desired timing of the synchronization pins; these include HSYNCF[9:0] and
HSYNCR[9:0].

Table 2-1. Read-back Bit Map

ESTATUS 7 6 5 4 3 2 1 0

0 ID[2:0] VERSION[4:0]

1 ID[2:0] CCSTAT[2] CCSTAT[1] FIELD[2:0]

NOTE(S): The ID[2:0] bits indicate the part number: 4 is returned from the Bt864A; 5 is returned from the Bt865A. The version

number is indicated by bits VERSION[4:0]. For this revision, VERSION[4:0] = 0x11. The CCSTAT[2] bit is high if closed-caption
data has been written for the even field; it is low immediately after the clock run-in on line 284 or 335. The CCSTAT[1] bit is high
if closed-caption data has been written for the odd field; it is low immediately after the clock run-in on line 21 or 22. The
FIELD[2:0] bits represent the field number, where 000 indicates the first field.

2.0 Internal Registers Bt864A/865A

2.3 Writing Addresses YCrCb to NTSC/PAL Digital Video Encoder

2-2 Conexant 100138B

2.3 Writing Addresses

Following a start condition, writing to slave address 0x8A initiates access to subaddresses. Alternative slave
address 0x88 must be written if the ALTADDR pin is high.

2.4 Reading Information

Following a start condition, writing 0x8B initiates the read-back sequence, during which 8 bits of information
can be read from the SDA pin, MSB first. Alternative address 0x89 is required if the ALTADDR pin is high.
The first three bits indicate the part type (Bt864A or Bt865A). The lower five bits indicate either the version
number or the status bits.

Table 2-2. Register Bit Map (1 of 2)

7-Bit

Subaddr

8-Bit

Subaddr

D7 D6 D5 D4 D3 D2 D1 D0

0X50 0XA00 EWSF2 EWSF1

Reserved

(1)

WSDAT[1:4]

0X51 0XA2 WSDAT[5:12]

0X52 0XA6 WSDAT[13:20]

0x53 0xA6 SRESET

Reserved

(1)

0x54 0xA8

Reserved

(1)

0x55 0xAA

Reserved

(1)

0x56 0xAC TXHS[7:0]

0x57 0xAE TXHE[7:0]

0x58 0xB0 LUMADLY[1:0] TXHE[10:8] TXHS[10:8]

0x59 0xB2

Reserved

(1)

TXRM TXE TXEF2[8] TXBF2[8] TXEF1[8] TXBF1[8]

0x5A 0xB4 TXBF1[7:0]

0x5B 0xB6 TXEF1[7:0]

0x5C 0xB8 TXBF2[7:0]

0x5D 0xBA TXEF2[7:0]

0x5E 0xBC ECCF2 ECCF1 ECCGATE

Reserved

(1)

DACOFF YC16 CBSWAP PORCH

0x5F 0xBE CCF2B1[7:0]

0x60 0xC0 CCF2B2[7:0]

0x61 0xC2 CCF1B1[7:0]

0x62 0xC4 CCF1B2[7:0]

0x63 0xC6 HSYNCF[7:0]

Bt864A/865A 2.0 Internal Registers

YCrCb to NTSC/PAL Digital Video Encoder

2.4 Reading Information

100138B Conexant 2-3

0x64 0xC8 HSYNCR[7:0]

0x65 0xCA SYNCDLY FIELDI SYNCDIS ADJHSYNC HSYNCF[9,8] HSYNCR[9,8]

0x66 0xCC SETMODE SETUPDIS VIDFORM[3:0] NONINTLSQUARE

0x67 0xCE ESTATUS RGBO DCHROMA ECBAR SCRESETEVBI EACTIVE ECLIP

0x68 0xD0

Reserved

(1)

PAL-N

0x69 0xD2

Reserved

(1)

••• •••

Reserved

(1)

0x7F 0xFE

Reserved

(1)

NOTE(S):

(1)

Must be zero for normal operation. This is the default software reset state.

2. All subaddresses are hexadecimal. The 8-bit subaddress reflects a left-shift 7-bit subaddress with zero added as the LSB.

Table 2-2. Register Bit Map (2 of 2)

7-Bit

Subaddr

8-Bit

Subaddr

D7 D6 D5 D4 D3 D2 D1 D0

2.0 Internal Registers Bt864A/865A

2.5 Programming Detail YCrCb to NTSC/PAL Digital Video Encoder

2-4 Conexant 100138B

2.5 Programming Detail

EWSF1 0 = Disable WSS/CGMS encoding in field 1.

1 = Enable WSS/CGMS encoding in field 1 (line 20).

EWSF2 0 = Disable WSS/CGMS encoding in field 2.

1 = Enable WSS/CGMS encoding in field 2 (line 283).

WSDAT [1:20] WSS/CGMS data.

SRESET When set to logical one, this will reset all registers, including itself, to logical zero.

TXHS[10:0] Relative position of rising edge on the TTXREQ pin.

TXHE[10:0] Relative position of falling edge on the TTXREQ pin.

LUMADLY[1:0] This 2-bit value can be used to program the luminance delay on the CVBS/B output.

TXRM 0 = REQUEST mode, TTXREQ pin outputs request.

1 = CLOCK mode, TTXREQ pin outputs teletext clock.

TXE 0 = Disable teletext.

1 = Enable teletext.

TXBF1[8:0] First line of teletext, field one; TXBF1 + 1 = Std. PAL line number.

TXEF1[8:0] Last line of teletext, field one; TXEF1= Std. PAL line number.

TXBF2[8:0] First line of teletext, field two; TXBF2 + 313 = Std. PAL line number.

TXEF2[8:0] Last line of teletext, field two; TXEF2 + 312 = Std. PAL line number.

ECCF2 0 = Disable closed-caption encoding on field 2.

1 = Enable closed-caption encoding on field 2.

ECCF1 0 = Disable closed-caption encoding on field 1.

1 = Enable closed-caption encoding on field 1.

ECCGATE 0 = Normal closed-caption encoding.

1 = Enable closed-caption encoding constraints. After encoding, future encoding is disabled until a complete
pair of new data bytes is received. This prevents encoding of redundant or incomplete data.

DACOFF 0 = Normal operation.

1 = Disable DAC output current and internal voltage reference. This will limit power consumption to just the
digital circuits.
The DACOFF bit is forced high after power-up until either 8 fields have been output or register 0x67 (0xCE in
8-bit subaddress) has been written.

YC16 0 = 8-bit mode: YCrCb data is input on P[7:0] as 8-bit multiplexed video.

1 = 16-bit mode: YCrCb data is input on P[7:0] and Y[7:0], where multiplexed CrCb is input on P[7:0].

D7 D6 Function

00 No delay

0 1 1 pixel clock delay

1 0 2 pixel clock delay

1 1 3 pixel clock delay

Bt864A/865A 2.0 Internal Registers

YCrCb to NTSC/PAL Digital Video Encoder

2.5 Programming Detail

100138B Conexant 2-5

CBSWAP 0 = Normal pixel sequence.

1 = The Cb and Cr pixels can be swapped at the input of the pixel port. Refer to the pixel sequence section for
more information.

PORCH 0 = Front and back porch timing conforms to ITU-RBT.470-3. Front porch is 1.5 µs and back porch is 9.4 µs

for M-systems or 10.5 µs for PAL-systems. The active video region is therefore smaller than the 720 pixels
specified in CCIR601.
1 = Redefine porch timing per CCIR601. This setting allows the full picture with 720 pixels to be encoded by
using a portion of both the front and back porch for active video.

CCF2B1[7:0] This is the first byte of closed-caption information for the FIELD 2, line 284 for NTSC or line 335 for PAL. Data

is encoded LSB first.

CCF2B2[7:0] This is the second byte of closed-caption information for the FIELD 2, line 284 for NTSC or line 335 for PAL.

Data is encoded LSB first.

CCF1B1[7:0] This is the first byte of closed-caption information for the FIELD 1, line 21 for NTSC or line 22 for PAL. Data is

encoded LSB first.

CCF1B2[7:0] This is the second byte of closed-caption information for the FIELD 1, line 21 for NTSC or line 22 for PAL. Data

is encoded LSB first.

HSYNCF[9:0]
HSYNCR[9:0]

When ADJHSYNC is enabled, these 10 bit registers can be used to program the placement of the falling and
rising edges of HSYNC* relative to the internal horizontal pixel clock. This variable horizontal timing mode is
available in master mode only. For more detail, see the Pixel Input Timing section.

SYNCDLY 0 = Normal sync timing.

1 = Delayed sync timing.

FIELDI 0 = A “1” on FIELD pin indicates a FIELD 2.

1 = A “1” on FIELD pin indicates a FIELD 1.

SYNCDIS 0 = Normal HSYNC* operation.

1 = Disable HSYNC* edges during VBI (master mode only).

ADJHSYNC 0 = Output hsync pulse on HSYNC*. The standard hsync pulse falls at the start of a new line and remains low

for 4.7 µs.
1 = Output a programmable hsync pulse on HSYNC*. By programming HSYNCR and HSYNCF, HSYNC* can
rise and fall at any desired time during each line.

SETMODE This bit is ignored in master mode (automatic mode detection is not applicable in slave mode).

0 = By default, in slave mode, the video mode is automatically detected. This is further explained in the SLAVE
mode section.
1 = Override automatic mode-detection in slave mode. The mode will be set according to the VIDFORM[3:0],
NONINTL, and SQUARE register bits.

SETUPDIS 0 = Setup on. The 7.5 IRE setup is enabled for active video lines.

1 = Setup off. The 7.5 IRE setup is disabled.

VIDFORM[3:0] Configures the device for various worldwide video formats

D5 D4 D3 D2 Format Typical Market

0000NTSC normal USA/Japan

0010

NTSC-60 Hz

(1)

USA–HDTV

1100PAL-M normal Brazil

1110PAL-M–60 HZ Brazil - HDTV

1001PAL-BDGHIN W. Europe

1101 PAL-Nc Argentina

NOTE(S):

(1)

SCRESET must be “1”.

2.0 Internal Registers Bt864A/865A

2.5 Programming Detail YCrCb to NTSC/PAL Digital Video Encoder

2-6 Conexant 100138B

NONINTL 0 = Interlaced operation.

1 = Noninterlaced operation.

SQUARE 0 = CCIR601 operation.

1 = Square pixel operation.

ESTATUS

0 = The I

2

C read-back information contains the version number.

1 = The I

2

C read-back information contains closed-captioning status and field number.

RGBO 0 = Normal operation.

1 = Enable RGB outputs.

DCHROMA 0 = Normal operation.

1 = Blank chroma.

ECBAR 0 = Normal operation.

1 = Enable color bars.

SCRESET 0 = Normal operation. The subcarrier phase is reset to zero at the beginning of each color field sequence.

1 = Disable subcarrier reset event at beginning of field sequence.

EVBI 0 = Video is blanked during the vertical blanking interval.

1 = Enable active video during vertical blanking interval. Setup is added during VBI, if SETUPDIS = 0, and
scaling of YCrCb pixels is always based on 100% blank to white, i.e., normal PAL input scaling.

EACTIVE 0 = Black burst (only if ECBAR = 0).

1 = Enable normal video.

ECLIP 0 = Normal operation.

1 = Enable clipping; DAC values less than 31 are made 31. This limit corresponds to roughly one-fourth of the
sync height.

PAL-N 0 = PAL-BDGHI operation when VIDFORM[3:0] set appropriately.

1 = PAL-N operation when VIDFORM[3:0] set appropriately.

100138B Conexant 3-1

3

3.0 PC Board Considerations

The layout should be optimized for lowest noise on the power and ground planes
by providing good decoupling. The trace length between groups of VAA and
GND pins should be as short as possible to minimize inductive ringing.

A well-designed power distribution network is critical to eliminating digital
switching noise. The ground plane must provide a low-impedance return path for
the digital circuits. A PC board with a minimum of four layers is recommended,
with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for ground and
power, respectively.

3.1 Component Placement

Components should be placed as close as possible to the associated pin.
Whenever possible, components should be placed so traces can be connected
point to point.

The optimum layout enables the Bt864A/865A to be located as close as
possible to the power supply connector and the video output connector.

3.2 Power and Ground Planes

Separate digital and analog power planes are recommended. The digital power
plane should provide power to all digital logic on the PC board, and the analog
power plane should provide power to the VAA power pin, protection diodes,
RF modulator, VREF, VBIAS, and COMP decoupling. There should be at least a
1/8-inch gap between the digital and analog power planes, connected by a single
point through a ferrite bead, as illustrated in Figures 3-1 and 3-2. The ground
plane should be a single unified plane overlapping both analog and digital power
planes. The path back to the power supply should be with the lowest impedance
possible with only one possible return path. This layout eliminates noise on the
analog signals caused by cross-currents from digital switching.

This bead should be located within 3 inches of the Bt864A/865A. The bead
provides impedance to switching currents, which provides increased impedance at
high frequencies. A low-resistance (<0.5 ¾) bead should be used, such as
Ferroxcube 5659065-3B, Fair-Rite 2723021447, or TDK BF45-4001.

3.0 PC Board Considerations Bt864A/865A

3.2 Power and Ground Planes YCrCb to NTSC/PAL Digital Video Encoder

3-2 Conexant 100138B

Figure 3-1. Example Power Plane Layout

CONN

Analog

864A/865A

Ferrite
Bead

13 1

Figure 3-2. Typical Connection Diagram and Parts List

NOTE(S):

(1)

Some modulators may require AC coupling capacitors (10 µF).

VAA

COMP

VREF

AGND

C6

C7

C2

FSADJUST

RSET

CVBS/G

CVBS/B

Y/CVBS

C/R

Analog Power Plane

P

P

P

P

LPF

LPF

LPF

To Vi de o
Connector

Ground
(Power Supply
Connector)

VCC

VAA

Schottky Diodes

Schottky Diodes

RF Modulator

75

TRAP

RF

Modulator

LPF

22 pF

1.8 µH

270 pF

Bt864A/865A

C9

+

C1

L1

RF MODULATOR

RF

330 pF

GND

To Filter

DAC Output

22 pF

1.8 µH

270 pF

330 pF

Audio

82

ZIN = 1 K

(1)

RLOAD RLOAD RLOAD

RLOAD

GND

VDD

VBIAS

C8

C3–C5

47 µf

Bt864A/865A 3.0 PC Board Considerations

YCrCb to NTSC/PAL Digital Video Encoder

3.2 Power and Ground Planes

100138B Conexant 3-3

Location Description Vendor Part Number

C1–C8 0.1 µF Ceramic Capacitor Erie RPE112Z5U104M50V

C9 47 µF Capacitor Mallory CSR13F476KM

L1 Ferrite Bead - Surface Mount Fair-Rite 2743021447

RSET 1% Metal Film Resistor (75

¾)

Dale CMF-55C

TRAP Ceramic Resonator Murata TPSx.xMJ or MB2 (where x.x = sound carrier frequency in MHz)

Schottky Diodes BAT85 (BAT54F Dual) HP 5082-2305 (1N6263) Siemens BAT 64-04 (Dual)

RLOAD

1% Metal Film Resistor

(1)

Dale CMF-55C

NOTE(S):

(1)

Resistor value is typically 75¾. Conductance combined with the load equals that of a 37.5 ¾ resistor.

2. The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the
performance of the Bt864A/865A.

3.0 PC Board Considerations Bt864A/865A

3.3 Decoupling YCrCb to NTSC/PAL Digital Video Encoder

3-4 Conexant 100138B

3.3 Decoupling

3.3.1 Device Decoupling

For optimum performance, all capacitors should be located as close as possible to
the device, and the shortest possible leads (consistent with reliable operation)
should be used to reduce the lead inductance. Chip capacitors are recommended
for minimum lead inductance. Radial lead ceramic capacitors may be substituted
for chip capacitors and are better than axial lead capacitors for self-resonance.
Values are chosen to have self-resonance above the pixel clock.

3.3.2 Power Supply Decoupling

The best power supply performance is obtained with a 0.1 µF ceramic capacitor
decoupling each group of VDD pins to GND, and the VAA pin to AGND. The
capacitors should be placed as close as possible to the device VAA, VDD, AGND,
and GND pins and connected with short, wide traces.

The 47

µF capacitor shown in Figure 3-2 is for low-frequency power supply

ripple; the 0.1

µF capacitors are for high-frequency power supply noise rejection.

When a linear regulator is used, the power-up sequence must be verified to
prevent latchup. A linear regulator is recommended to filter the analog power
supply if the power supply noise is greater than or equal to 200 mV. This is
especially important when a switching power supply is used, and the switching
frequency is close to the raster scan frequency. About 5% of the power supply
hum and ripple noise less than 1 MHz will couple onto the analog outputs.

3.3.3 COMP Decoupling

The COMP pin must be decoupled to the VAA pin, typically with a 0.1 µF
ceramic capacitor. Low-frequency supply noise will require a larger value. The
COMP capacitor must be as close as possible to the COMP and the VAA pin. A
surface-mount ceramic chip capacitor is preferred for minimal lead inductance.
Lead inductance degrades the noise rejection of the circuit. Short, wide traces will
also reduce lead inductance.

3.3.4 VREF Decoupling

A 0.1 µF ceramic capacitor should be used to decouple this pin to AGND.

3.3.5 VBIAS Decoupling

A 0.1 µF ceramic capacitor should be used to decouple this pin to AGND.

Bt864A/865A 3.0 PC Board Considerations

YCrCb to NTSC/PAL Digital Video Encoder

3.4 Signal Interconnect

100138B Conexant 3-5

3.4 Signal Interconnect

3.4.1 Digital Signal Interconnect

The digital inputs to the Bt864A/865A should be isolated as much as possible
from the analog outputs and other analog circuitry. Also, these input signals
should not overlay the analog power plane or analog output signals.

Most of the noise on the analog outputs will be caused by excessive edge rates
(less than 3 ns), overshoot, undershoot, and ringing on the digital inputs.

The digital edge rates should not be faster than necessary, as feed through
noise is proportional to the digital edge rates. Lower-speed applications will
benefit from using lower-speed logic (3–5 ns edge rates) to reduce data-related
noise on the analog outputs.

Transmission lines will mismatch if the lines do not match the source and
destination impedance. This will degrade signal fidelity if the line length
reflection time is greater than one-fourth the signal edge time. Line termination or
line-length reduction is the solution. For example, logic edge rates of 2 ns require
line lengths of less than 4 inches without use of termination. Ringing may be
reduced by damping the line with a series resistor (30–300

Ω).

Radiation of digital signals can also be picked up by the analog circuitry. This
is prevented by reducing the digital edge rates (rise/fall time), minimizing ringing
with damping resistors, and minimizing coupling through PC board capacitance
by routing the digital signals at a 90 degree angle to any analog signals.

The clock driver and all other digital devices must be adequately decoupled to
prevent digital noise from coupling into the analog circuitry.

3.4.2 Analog Signal Interconnect

The Bt864A/865A should be located as close as possible to the output connectors
to minimize noise pickup and reflections caused by impedance mismatch.

The analog outputs are susceptible to crosstalk from digital lines; digital traces
must not be routed under or adjacent to the analog output traces.

To maximize the high-frequency power supply rejection, the video output
signals should overlay the ground plane.

For maximum performance, the analog video output impedance, cable
impedance, and load impedance should be the same. The load resistor connection
between the video outputs and AGND should be as close as possible to the
Bt864A/865A to minimize reflections. Unused DAC outputs should be connected
to AGND unless the power-down feature is being utilized.

3.0 PC Board Considerations Bt864A/865A

3.5 Applications Information YCrCb to NTSC/PAL Digital Video Encoder

3-6 Conexant 100138B

3.5 Applications Information

3.5.1 ESD and Latchup Considerations

Correct ESD-sensitive handling procedures are required to prevent device
damage. Device damage can produce symptoms of catastrophic failure or erratic
device behavior with leaky inputs.

All logic inputs should be held low until power to the device has settled to the
specified tolerance. DAC power decoupling networks with large time constants
should be avoided; they could delay VAA power to the device. Ferrite beads must
be used only for analog power VAA decoupling. Inductors cause a time constant
delay that induces latchup.

Latchup can be prevented by ensuring that all VAA and VDD pins are at the
same potential, all GND and AGND pins are at the same potential, and that the
VAA and VDD supply voltages are applied before the signal pin voltages. The
correct power-up sequence ensures that any signal pin voltage will never exceed
the power supply voltage.

3.5.2 Clock and Subcarrier Stability

The color subcarrier is derived directly from the CLK input, hence any jitter or
frequency deviation of CLK will be transferred directly to the color subcarrier.
Jitter within the valid CLK cycle interval will result in hue noise on the color
subcarrier on the order of 0.9–1.6 degrees per nanosecond. Random hue noise can
result in degradation in AM/PM noise ratio (typically around 40 dB for consumer
media such as Videodiscs and VCRs). Periodic or coherent hue noise can result in
differential phase error (which is limited to 10 degrees by FCC cable TV
standards). Any frequency deviation of the CLK from nominal will challenge the
subcarrier tracking capability of the destination receiver. This may range from a
few parts-per-million (ppm) for broadcast equipment to 50 ppm for industrial
equipment to a few hundred ppm for consumer equipment. Greater subcarrier
tracking range generally results in poorer subcarrier decoding dynamic range, so
that receivers that tolerate jitter and wide subcarrier frequency deviation will
introduce more noise in the decoded image. Crystal clock sources provide best
stability and lowest jitter, with 50–100 ppm accuracy required by most industrial
or consumer receivors. Note that a 30 ppm tolerance constraint applies for
Teletext and MPEG2.

Some applications call for maintaining correct Subcarrier-Horizontal (SC-H)
phasing for correct color framing, which requires subcarrier coherence within
specified tolerances over a 4-field interval for 525-line systems or 8 fields for
625-line systems. Any CLK interruption (even during vertical blanking interval)
which results in nonstandard pixel counts per line can result in SC-H excursions
outside the NTSC limit of ±40 degrees (reference EIA RS170A) or the PAL limit
of ±20 degrees (reference EBU D23-1984).

Any deviation of the number CLK cycles between HSYNC* falling edges
when in SLAVE mode may result in automatic mode switching unless the internal
control registers VIDFORM, NONINTL and SQUARE are set for the desired
mode of operation.

Bt864A/865A 3.0 PC Board Considerations

YCrCb to NTSC/PAL Digital Video Encoder

3.5 Applications Information

100138B Conexant 3-7

3.5.3 Mutual Inductance Concerns

The designer should prevent a situation where signals from other devices next to
the encoder cause the crystal to generate faulty clocks.

The Conexant encoder and any associated crystal that drives the CLK input
should physically be placed as far as possible from signal lines with excessive
currents. Excessive currents are defined to be greater than the Total Supply
Current figure listed in Table 4 -3 .

In some systems, there are signal lines for controlling motors, LEDs, and
thermal heads. When a large current flows through these traces problematic noise
can result from the phenomenon of mutual inductance (See Figure 3-3).

3.5.4 Reset Precautions

The user should make the length of the traces connected to the RESET* input pin
as short as possible. In addition, Conexant recommends that a 0.1 µF capacitor be
connected across the RESET* input pin and the digital ground pins (GND) for
decoupling purposes.

All of Bt864A/865A’s programmable register bits can be reset through
software (i.e., setting register bit SRESET= 1). Furthermore, both the
Bt864A/865A’s registers and timing can be reset by a low pulse of at least 0.05 µs
(>1 complete period of CLK) input directly to RESET*. If noise, having a pulse
width close to 0.05 µs, is inadvertently input to RESET*, it could cause the
encoder to unintentionally reset the subcarrier phase and/or the horizontal and
vertical counters (see Figure 1-9). This type of timing error could cause faulty
system operation (see Figure 3-4).

Figure 3-3. Example of Mutual Inductance

CLK

GND

Large Current

M

Figure 3-4. Wiring for the Reset Input Pin

RESET*

GND

0.1 µF

Short as Possible

3.0 PC Board Considerations Bt864A/865A

3.5 Applications Information YCrCb to NTSC/PAL Digital Video Encoder

3-8 Conexant 100138B

3.5.5 Filtering RF Modulator Connection

The Bt864A/865A internal upsampling filter alleviates external filtering
requirements by moving significant sampling alias components above 19 MHz
and reducing the sinx/x aperture loss up to the f ilter’s passband cutoff of 5.75
MHz. While typical chrominance subcarrier decoders can handle the
Bt864A/865A output signals without analog filtering, the higher frequency alias
products pose some EMI concerns and may create troublesome images when
introduced to an RF modulator. When the video is presented to an RF modulator,
it should be free of energy in the region of the aural subcarrier (4.5 MHz for
NTSC, 5.5–6.5 MHz for PAL), hence some additional frequency traps may be
necessary when the video signal contains fundamental or harmonic energy (as
from unfiltered character generators) in that region. For example, a pixel rate of

13.5 msps is three times the NTSC-M aural carrier of 4.5 MHz, hence significant
harmonic energy can fall on the FM aural carrier for character cell sizes which are
multiples of three. Where better frequency response flatness is required, some
peaking in the analog filter is appropriate to compensate for residual digital filter
losses with sufficient margin to tolerate 10% reactive components.

A three-pole elliptic f ilter (1 inductor, 3 capacitors) with a 6.75 MHz
passband can provide at least 45 dB attenuation (including sinx/x loss) of
frequency components above 20 MHz and provide some flexibility for mild
peaking or special traps. An inductor value with a self-resonant frequency above
80 MHz is chosen so that its intrinsic capacitance contributes less than 10% of the
total effective circuit value. The inductor itself may induce 1% (0.1 dB) loss, and
worst case subcarrier attenuation (including sinx/x loss) may be 7% with 10%
tolerance reactive components. Any additional ferrites introduced for EMI control
after termination should have less than 5 ¾ impedance below 5 MHz to minimize
additional losses. The capacitor to ground at the Bt864A/865A output pin is
compensated for the parasitic capacitance of the chip plus any protection diodes
and lumped circuit traces (about 22 pF+5 pF/diode). Some filter peaking can be
accomplished by splitting the source impedance across the reactive PI filter
network. However, this will also introduce some chrominance-luminance delay
distortion in the range of 10–20 ns for a maximum of 0.5 dB boost at the
subcarrier frequency.

The filter network feeding an RF modulator may include the aforementioned
trap, which could take two forms depending on the depth of attenuation and type
of resonator device employed. The RF modulator typically has a high input
impedance (about 1 K¾ ± 30%) and loose tolerance. Consequently, the amplitude
variation at the modulator input will be greater, especially when the trap is
properly terminated at the modulator input for maximum effect. Some modulators
video or aural fidelity will degrade dramatically when overdriven, so the value of
the effective termination (nominally 37.5 ¾) may need to be adjusted downward
to maintain sufficient linearity (or depth of modulation margin) in the RF signal.
Where required to maintain better than 40 dB audio dynamic range in the
presence of video energy in the region of the aural carrier, a two section trap with
more than 20 dB attenuation may be warranted. Best gain flatness versus
frequency and luma-chroma delay match can be obtained by active buffering and
use of the variable luma delay on CVBS/B channel. See Figure 3-2.

Bt864A/865A 3.0 PC Board Considerations

YCrCb to NTSC/PAL Digital Video Encoder

3.5 Applications Information

100138B Conexant 3-9

3.5.6 Luminance Delay on CVBS/B

Postfiltering of the video signal can introduce a variable delay between the lower
frequency luminance components and the higher frequency chrominance
subcarrier components. The group delay distortion is often specified in system as
chroma-luma delay inequality or as Sinx/x pulse group delay. Group delay
distortion is commonly induced by postfilters which peak the chrominance level,
by trap circuits intended to reduce video energy in the aural subcarrier frequency
range, and by Vestigial Sideband (VSB) filtering in RF tuners. Since
oversampling encoders greatly reduce the need for peaking filters, delay
compensation of the luminance signal largely benefits the channel through the RF
modulation and tuner path where group delay distortion can amount to several
hundred nanoseconds or several pixels of misregistration.

While flat group delay correction as observed from a Sinx/x pulse spectrum
can require several LC stages with active buffers, a simplified approach where
only luma-chroma delay must be equalized is to shift the luminance signal
through pipeline delays to match any additional group delay induced on the
chrominance components by postfiltering. This alignment of the lower frequency
luminance components with the chrominance components does not strictly satisfy
broadcast quality requirements but provides perceptible improvements in display
registration.

While VSB delays are prescribed in ITU-R BT.470-3 as about 170 ns, the
luminance delay compensation for postfilter aural traps depends on the
attenuation required at the aural carrier frequency. In the case of NTSC signals
sampled at CCIR601 resolution, the coincidence of the aural carrier (4.5 MHz) at
one third of the sample rate means that any video component which transitions at
intervals of every third pixel clock can generate significant energy at the aural
carrier frequency. In the case of hard-edged, unblended characters having a font
cell size which is a multiple of three pixels, harmonic energy at the aural carrier
frequency may be only 15 dB below the maximum video level, or roughly equal
to the power of the sound subcarrier in the RF spectrum.

Trap attenuation of about 20 dB can assure that the resultant interference with
the FM aural signal will degrade the noise level at the monaural decoded receiver
about 1 dB (–44 dB range) with less than 50 ns additional chroma delay
[Multichannel stereo (e.g.,BTSC) or Second Audio Program (SAP) encoder may
require greater attenuation due to lower level subcarriers]. Therefore, luminance
delay compensation of about 225 ns on just the RF feed (e.g. CVBS/B) can
correct for the chroma delay artifacts of additional processing in the RF channel
without compromising the inherently low group delay distortion of the baseband
channels (e.g. CVBS/Y/C).

3.0 PC Board Considerations Bt864A/865A

3.6 I2C Programming YCrCb to NTSC/PAL Digital Video Encoder

3-10 Conexant 100138B

3.6 I2C Programming

3.6.1 Data Transfer on the I2C Bus

An I2C reference manual has been developed and may be obtained upon request.
This provides farther information on I

2

C bus protocol. Figure 3-5 shows the

relationship between SDA and SCL to be used when programming the I

2

C bus. If

the bus is not being used, both SDA and SCL lines must be left high.

Every byte put onto the SDA line should be 8 bits long (MSB first), followed
by an acknowledge bit, which is generated by the receiving device.

Each data transfer is initiated with a start condition and ended with a stop
condition. The first byte after a start condition is always the address byte. If this is
the device’s own address, the device will generate an acknowledge by pulling the
SDA line low during the ninth clock pulse, then accept the data in subsequent
bytes (autoincrementing the subaddress) until another stop condition is detected.

Bit 8 of the address byte is the read/write bit (high = read from addressed
device, low = write to the addressed device) so, for the Bt864A/865A, the address
is only considered valid if the R/W bit is low.

Data bytes are always acknowledged during the ninth clock pulse by the
addressed device. Note that during the acknowledge period the transmitting
device must leave the SDA line high.

Premature termination of the data transfer is allowed by generating a stop
condition at any time. When this happens, the Bt864A/865A will remain in the
state defined by the last complete data byte transmitted. Any master acknowledge
subsequent to reading the chip ID is ignored.

Figure 3-5. I2C Diagram

NOTE(S):

(1)

Acknowledge generated by Bt864A/865A.

1

SCL

23456789

123456789

1234 56 789

Subsequent Bytes and Acknowledge
Interpreted as Data Values for
Autoincremented Subaddress Locations

SDA

MSB

LSB

(1)

Start Condition

Stop Condition

Subaddress

(XX)

Data

(XX)

Main Address

(XX)

(1) (1)

100138B Conexant 4-1

4

4.0 Parametric Information

4.1 DC Electrical Parameters

Table 4-1. Recommended Operating Conditions

Parameter Symbol Min Typ Max Units

Power Supply VAA

5 V 4.75 5.00 5.25 V

3.3 V 3.0 3.3 3.6 V

Ambient Operating Temperature TA 0 70 °C

DAC Output Load RL 37.5 ¾

Nominal RSET RSET 75 ¾

Table 4-2. Absolute Maximum Ratings

Parameter Symbol Min Typ Max Units

VAA and VDD (measured to GND) 7.0 V

Voltage on Any Signal Pin

(1)

GND –0.5 VAA or

VDD + 0.5

V

Analog Output Short Circuit Duration to
Any Power Supply or Common

ISC Indefinite

Storage Temperature TS –65 +150 °C

Junction Temperature TJ +125 °C

Vapor Phase Soldering (1 Minute) TVSOL 220 °C

NOTE(S):

(1)

This device employs high-impedance CMOS structures on all signal pins. It should be handled as an ESD-sensitive device.
Voltage on any signal pin that exceeds the power supply or ground voltage by more than 0.5 V can cause destructive latchup.

2. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

4.0 Parametric Information Bt864A/865A

4.1 DC Electrical Parameters YCrCb to NTSC/PAL Digital Video Encoder

4-2 Conexant 100138B

Table 4-3. DC Characteristics (VDD = 5 V)

Parameter Symbol Min Typ Max Units

Video D/A Resolution 10 10 10 Bits

Output Current-DAC Code 1023 (Iout FS) 34.13 mA

Output Voltage-DAC Code 1023 1.28 V

Video Level Error (Nominal Resistors) 5 %

Output Capacitance 22 pF

Digital Inputs (Except those specified below)

Input High Voltage VIH 2.0 VDD + 0.5 V

Input Low Voltage VIL GND –0.5 0.8 V

Input High Current (Vin = 2.4 V) IIH 1 µA

Input Low Current (Vin = 0.4 V) IIL –1µA

Input Capacitance (f = 1 MHz, Vin = 2.4 V) CIN 7 pF

SCL, SDA

Input High Voltage VIH 0.7 x VDD VDD + 0.5 V

Input Low Voltage VIL GND –0.5 0.3 x VDD V

CLK Input

Input High Voltage VIH 2.4 VDD + 0.5 V

Input Low Voltage VIL GND –0.5 0.8 V

Digital Outputs

Output High Voltage (IOH = –400 µA) VOH 2.4 V

Output Low Voltage (IOL = 3.2 mA) VOL 0.4 V

Three-State Current IOZ 50 µA

Output Capacitance CDOUT 10 pF

NOTE(S): “Recommended Operating Conditions,” NTSC CCIR 601 operation, and CLK frequency = 27 MHz. As the above

parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values
are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V or 3.3 V.

Bt864A/865A 4.0 Parametric Information

YCrCb to NTSC/PAL Digital Video Encoder

4.2 AC Electrical Parameters

100138B Conexant 4-3

4.2 AC Electrical Parameters

Table 4-4. AC Characteristics (VDD = 5 V, VAA = 5 V) (1 of 2)

Parameter

EIA/TIA

250C Ref

CCIR

567

Symbol Min Typ Max Units

Hue Accuracy

(3)

X

(1)

X

(2)

12.5 ± °

Color Amplitude Accuracy

(3)

X

(1)

X

(2)

12.3 ± %

Chroma AM/PM Noise

(4)

1 MHz

Red Field

–64 dB rms

Differential Gain

(3)

6.2.2.1 1 2 % p–p

C3.4.1.3 1.5 % p–p

Differential Phase

(3)

6.2.2.2 0.5 2.2 ° p–p

C3.4.1.3 0.4

5

° p–p

SNR (unweighted 100 IRE Y
Ramp Tilt Correct)

(3)

RMS (5 MHz Bandwidth) 6.3.1 –62 dB rms

Peak Periodic 6.3.2 –60 dB p–p

100 IRE Multiburst (4.0 MHz Packet)

(4)

6.1.1 –2.
3

–3± IRE

Gain/frequency (4.8 MHz Packet) C3.5.4.1 –0.5–0.8 dB

Chroma/Luma Gain Ineq

(4)

5.0 V 6.1.2.2 C3.5.3.1 –2 –2.5 ± IRE

3.3 V 6.1.2.2 C3.5.3.1 –2.
5

± IRE

Chroma/Luma Delay Ineq

(4)

6.1.2 C3.5.3.2 0 10 ns

Short Time Distortion 100IRE/PIXEL

(4)

6.1.6 C3.5.1.4 2.3 3 %

Luminance Nonlinearity

(3)

6.2.1 0.5 %

Chroma/Luma Intermod

(3)

6.2.3 0.2 22 ± IRE

C3.4.1.4 0.8 ± IRE

Chroma Nonlinear Gain

(3)

6.2.4.1 0.2 2 ± IRE

Chroma Nonlinear Phase

(3)

6.2.4.2 0.2 2 ± °

Pixel/Control Setup Time

(5)

17 ns

Pixel/Control Hold Time

(5)

23 ns

4.0 Parametric Information Bt864A/865A

4.2 AC Electrical Parameters YCrCb to NTSC/PAL Digital Video Encoder

4-4 Conexant 100138B

Control Output Delay Time

(5)

5.0 V 3 17 ns

3.3 V 3 35 ns

Control Output Hold Time

(5)

44 ns

CLK Frequency 24.54 27 29.5 MHz

CLK Pulse Width Low Time 8 ns

CLK Pulse Width High Time 8 ns

Pipeline Delay

Input Pixels to Composite Video 52 CLK periods

Input Pixels to RGB Output 52 CLK periods

VAA Supply Current 180 mA

VDD Supply Current

5.0 V 50 mA

3.3 V 30 mA

Total Supply Current

5.0 V 230 mA

3.3 V 210 mA

Power-Down Mode Currents

VAA Supply Current (SLEEP = 1)

(6)

1mA

VDD Supply Current (SLEEP = 1)

(6)

1mA

VAA Supply Current (DAC off =1) 1 mA

VDD Supply Current (DAC off =1) 50 mA

NOTE(S):

(1)

75/7.5/75/7.5 Color bars normalized to burst.

(2)

100/0/100/0 Colorbars normalized to burst.

(3)

Guaranteed by characterization.

(4)

Without post filter. Guaranteed by design.

(5)

Control pins are defined as: P[7:0], Y[7:0],BLANK*, HSYNC*, VSYNC*, FIELD, TTXREQ, TTXDAT.

(6)

All digital inputs at GND or VDD.

7. “Recommended Operating Conditions,” NTSC CCIR 601 operation, and CLK frequency = 27 MHz. Analog output load ð 75 pF.
HSYNC*, VSYNC*, BLANK*, and FIELD output loads ð 75 pF. As the above parameters are guaranteed over the full
temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature,
i.e., room temperature, and nominal voltage, i.e., 5 V. Video input and output timing is shown in Figure 4-1.

Table 4-4. AC Characteristics (VDD = 5 V, VAA = 5 V) (2 of 2)

Parameter

EIA/TIA

250C Ref

CCIR

567

Symbol Min Typ Max Units

Bt864A/865A 4.0 Parametric Information

YCrCb to NTSC/PAL Digital Video Encoder

4.2 AC Electrical Parameters

100138B Conexant 4-5

Figure 4-1. YCrCb Video Input and Output Timing

CLK

16-bit mode, BLANK*,

HSYNC*, VSYNC*

P[7:0] 8-bit mode,

1

2

3

4

CVBS/B, CVBS/G,

Y/CVBS, C/R

1 2

HSYNC*, VSYNC*

FIELD (Output)

Pipeline

2.4

.8

3

4

2.4

.8

TTXDAT

TTXREQ

P[7:0], Y[7:0]

4.0 Parametric Information Bt864A/865A

4.3 Package Drawing YCrCb to NTSC/PAL Digital Video Encoder

4-6 Conexant 100138B

4.3 Package Drawing

Figure 4-2. 52-Pin PQFP

Bt864A/865A 4.0 Parametric Information

YCrCb to NTSC/PAL Digital Video Encoder

4.4 Revision History

100138B Conexant 4-7

4.4 Revision History

Revision Change from Previous Revision

A New Datasheet.

4.0 Parametric Information Bt864A/865A

4.4 Revision History YCrCb to NTSC/PAL Digital Video Encoder

4-8 Conexant 100138B

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