Multiport YCrCb to NTSC / PAL
Digital Video Encoder
The Bt860/861 is a multiport digital video encoder with pixel synchronization and
per-pixel blending capabilities. The three 8-bit YCrCb data ports allow for a variety of
video and graphic overlay configurations useful in video set-top box applications.
The Bt860/861 is specifically designed for video systems requiring composite,
Y/C (S-Video), and simultaneous component YUV or RGB (SCART) video signals.
Worldwide video standards are supported, including NTSC-M (N. America, Taiwan,
Japan), PAL-B,D,G,H,I (Europe, Asia), PAL-M (Brazil), PAL-N (Uruguay, Paraguay),
PAL-Nc (Argentina), PAL-60, NTSC-443, and SECAM. The Bt860 and Bt861 are
functionally identical except that the Bt861 can output the Macrovision 7.x anticopy
algorithm.
Multisource video is a key feature of the Bt860/861. Two general purpose ports
(P and OSD) allow synchronization with sources that can share clock and frame
timing control with the Bt860/861, such as digital video and graphic overlay content
generated by an MPEG video decoder. A third port (VID) is specifically configured to
interface with video decoders such as those in the Conexant VideoStream decoder
family. Any pair of these three ports can be synchronized and blended.
Functional Block Diagram
SICSIDALTADDRRESET*VREF
TTXDAT
TTXREQ
VID[7:0]
VIDCLK
VIDHACT
VIDVACT
VIDVALID
VIDFIELD
HSYNC*
VSYNC*
BLANK*
FIELD
ALPHA[1:0]
P[7:0]
OSD[7:0]
CLKO
XTI
XTO
CLKIN
Teletext
Encoder
Pixel
Sync.
and
Mixing
XTAL
OSC
1.3 MHz
LPF
PLL
Serial
Interface
2x
Upsampling
Clock
Generation
Mod.
and
Mixer
Internal
Internal
VREF
VREF
/
Color
Space
Convert
SECAM
FSADJ1
10
DAC
10
DAC
10
DAC
10
DAC
10
DAC
10
DAC
FSADJ2
COMP1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
COMP2
Distinguishing Features
• Six 10-bit DACs with individual power
management
• Simultaneous output of YUV, S-Video,
and CVBS, or RGB (SCART), S-Video,
and CVBS
• Current drive output DACs for superior
video quality and reduced system cost
• Dynamic video load sensing for reduced
power operation
• Three sharpness filter options (1,2,3.5 dB
gain) and four reduction filter options
• Programmable adjustment of brightness,
contrast, color saturation, and hue
• Glueless interface with a video decoder
• Three 8-bit YCrCb 4:2:2 inputs for overlay
or blending
• ITU-R BT.656, ITU-R BT.601 digital video
input options
• NTSC-M, PAL (B,D,G,H,I), PAL-M, PAL-N,
NTSC-443, PAL-Nc, PAL-60 and SECAM
video output
• 2x upsampling and internal filtering for
reduced cost
• Master or slave video timing with
programmable HSYNC* delay
• Interlaced/noninterlaced operation
• Macrovision 7.x copy protection (Bt861)
• Closed Captioning and Extended Data
Services encoding
• Teletext encoding (WST system B)
• 400 kHz serial programming interface
• On-board voltage reference
• Reduced power modes
• Programmable luma delay (two channels)
• 3.3 V supply, 5 V-tolerant inputs
• Copy Generation Management System
(CGMS) support
• VARIS-II and Wide Screen Signalling
(WSS) multiple aspect ratio support
• Internal color bar generation
• Blue field generation
• 80-pin MQFP package
Related Products
• Bt852, Bt868/869, Bt864A/865A,
Bt866/867
• Bt835, Bt829A/B
Applications
• Digital cable television systems
• Satellite TV receivers (DBS/DVB/DSS)
• DVD players
• Video CD players
• Digital cameras
• PC add-on cards
• Video editing
Data SheetD860DSA
July 27, 1999
Page 2
Ordering Information
Model NumberPackageOperating Temperature
Bt860KRF80–Pin MQFP0
Bt861KRF80–Pin MQFP0
C–70 °C
°
C–70 °C
°
Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is
assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant
products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without
notice.
Conexant products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a
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such improper use or sale.
Conexant and “What’s Next in Communications Technologies” are trademarks of Conexant Systems, Inc.
This device is protected by U .S . patent numbers 4,631,603, 4,577,216, and 4,819,098, and other intellectural property rights. The use
of Macrovision’s copy protection technology in the device must be authorized by Macrovison and is intended for home and other
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P[7:0]I22-19, 16-13Primary video input port (TTL compatible)
(1)
. Accepts pixel data in 8-bit YCrCb 4:2:2
format in either ITU-R BT.601 or ITU-R BT.656 control formats. A higher index
corresponds to a greater bit significance. By default, data is latched on the rising
edge of the system clock
(2)
.
CLKOO702x pixel clock output. The clock generated by the PLL is produced at this pin when
register bit CLKO_DIS = 0.
VSYNC*I/O24Vertical sync input/output (TTL compatible). As an output (master mode operation),
VSYNC* follows the rising edge of the system clock. As an input (slave mode
operation), VSYNC* is, by default, registered on the rising edge of the system
(2)
. The VSYNCI register bit controls the polarity of this signal.
clock
HSYNC*I/O25Horizontal sync input/output (TTL compatible). As an output (master mode
operation), HSYNC* follows the rising edge of the system clock. As an input (slave
mode operation), HSYNC* is, by default, registered on the rising edge of the system
(2)
. The HSYNCI register bit controls the polarity of this signal.
clock
BLANK*I23Composite blanking control input (TTL compatible). By default, BLANK* is
registered on the rising edge of the system clock
(2)
. The video data inputs are
ignored while BLANK* is a logical 0. The BLANKI register bit controls the polarity of
this signal.
FIELDO26Field control output (TTL compatible). FIELD transitions after the rising edge of the
system clock, two clock cycles following a falling HSYNC*. The FIELDI register bit
controls the polarity of this signal. The state of this pin at power-up determines the
default state of the PCLK_SEL register bit and the initial clock source. If not
externally loaded, this pin will be pulled low with an internal pull-down resistor.
SECONDARY VIDEO PORT
VID[7:0]I6-1, 80-79Secondary video input port (TTL compatible). Accepts pixel data in 8-bit YCrCb
4:2:2 format. A higher index corresponds to a greater bit significance. By default,
data on the VID port is latched by the rising edge of VIDCLK
(1)
VIDCLKI9Pixel clock for secondary video input port
VIDHACTI12Horizontal active display region. A logical 1 indicates data on VID[7:0] is in the
horizontal display region.
The VIDHACTI register bit controls the polarity of this
.
signal. By default, data on VIDHACT is latched by the rising edge of VIDCLK
VIDVACTI11Vertical active display region. The VIDVACTI register bit controls the polarity of this
signal. By default, data on VIDVACT is latched by the rising edge of VIDCLK
(1) (3)
.
(1) (3)
.
(1) (3)
.
VIDFIELDI72Field indicator for video input port. A logical 1 indicates data is from an even field.
The VIDFIELDI register bit controls the polarity of this signal. By default, data on
VIDFIELD is latched by the rising edge of VIDCLK
(1) (3)
.
VIDVALIDI10Video data valid qualifier. A logical 1 indicates data on VID[7:0] is valid data. The
VIDVALIDI register bit controls the polarity of this signal. By default, data on
VIDVALID is latched by the rising edge of VIDCLK
(1) (3)
.
1-2ConexantD860DSA
Page 13
Bt860/8611.0 Functional Description
Multiport YCrCb to NTSC/PAL /SECAM
1.1 Pin Descriptions
Table 1-1. Pin Assignments (2 of 3)
Pin NameI/OPin #Description
GRAPHIC AND BLENDING PINS
OSD[7:0]I40-39, 36-31Dedicated graphic overlay port (TTL compatible.) Accepts pixel data in 8-bit YCrCb
4:2:2 format. Data is latched on the rising edge of the system clock
ALPHA[1:0]I30-29Alpha blend pins. Provides for 1-, 2-, or 4-bit external blend selection between video
and graphic overlay data. Data is latched on the rising edge of the system clock
(1) (2)
.
TELETEXT AND SERIAL CONTROL INTERFACE
TTXDATI74Teletext data input (TTL compatible)
TTXREQO73Teletext request output (TTL compatible).
ALTADDRI/O62Alternate slave address input (TTL compatible). This pin is sampled immediately
following a power-up or pin reset. A logical 1 corresponds to write address of 0x88
and a read address of 0x89, while a logical 0 corresponds to a write address of 0x8A
and a read address of 0x8B. See Chapter 5.0, for more detail. This pin also provides
special SCART signals when register field SCART_SEL≠00.
SIDI/O75Serial programming interface data input/output (TTL compatible). Data is written to
and read from the device via this serial bus.
(1)
.
(1) (2)
.
SICI76Serial programming interface clock input (TTL compatible). The maximum clock rate is
400 kHz.
ANALOG VIDEO
DACAO59DAC A output. See Table 3-9.
DACBO58DAC B output. See Table 3-9.
DACCO57DAC C output. See Table 3-9.
DACDO44DAC D output. See Table 3-9.
DACEO43DAC E output. See Table 3-9.
DACFO42DAC F output. See Table 3-9.
FSADJ1
FSADJ2
VREFO49Voltage reference pin. A 1.0 µF ceramic capacitor must be used to decouple this pin
COMP1
COMP2
I53
48
O54
47
Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these
pins and AGND control the full-scale output current of the DACs. For standard
operation, use the nominal values shown under Recommended Operating
Conditions. FSADJ1 controls DACs A/B/C and FSADJ2 controls DACs D/E/F.
to AGND. The capacitor must be as close to the device as possible to keep lead
lengths to an absolute minimum.
Compensation pin. A 0.1 µF ceramic capacitor must be used to decouple this pin to
VAA. The capacitor must be as close to the device as possible to keep lead lengths
to an absolute minimum.
VBIAS1
VBIAS2
O56
45
DAC bias voltage. Use a 0.1 µF ceramic capacitor to bypass this pin to AGND; the
capacitor must be as close to the device as possible to keep lead lengths to an
absolute minimum.
D860DSAConexant1-3
Page 14
1.0 Functional DescriptionBt860/861
1.1 Pin Descriptions
Multiport YCrCb to NTSC/PAL /SECAM
Table 1-1. Pin Assignments (3 of 3)
Pin NameI/OPin #Description
SYSTEM PINS
CLKINI712x pixel clock input (TTL compatible).
RESET*I63Reset control input (TTL compatible). Setting to zero resets video timing
(horizontal, vertical, subcarrier counters to the start of VSYNC of first field), the
serial control interface, and all registers. RESET* must be a logical 1 for normal
operation. Holding this pin low for 50 clocks or more will ensure that all functions
are properly reset.
XTII67Crystal input for PLL.
XTOO68Crystal output for PLL.
POWER AND GROUND
VAA—55, 46, 52Analog power. See Section 4.1 of this document.
VDD—7, 28, 38, 64, 78Digital power. See Section 4.1 of this document.
AGND—41, 50, 51, 60Analog ground. See Section 4.1 of this document.
GND—8, 17, 27, 37,
Digital ground. See Section 4.1 of this document.
61, 65, 77
VPLL—69Dedicated power supply for PLL.
PGND—66Dedicated ground for PLL.
VDDMAXI18This pin must be tied to the maximum digital input value. Use 3.3 V if only 3.3 V
inputs are used, and 5 V if 3.3/5 V inputs are used.
NOTE(S):
(1)
If these inputs are not used, they should be connected to GND.
(2)
These input are normally sampled on the rising edge of the system clock, but can be sampled on the falling edge by setting
register bit PCLK_EDGE = 1.
(3)
These inputs are normally sampled on the rising edge of VIDCLK, but can be sampled on the falling edge by setting register bit
VIDCLK_EDGE = 1.
1-4ConexantD860DSA
Page 15
Bt860/8611.0 Functional Description
Multiport YCrCb to NTSC/PAL /SECAM
1.2 Functional Overview
The Bt860/861 is a highly programmable 3.3 V multiport digital video encoder
with pixel synchronization and per-pixel blending capabilities. It is equipped with
three 8-bit YCrCb data ports that allow a variety of video and graphic overlay
configurations useful in video set top box applications.
The three 8-bit YCrCb data ports allow two video streams and one
alpha-blended overlay stream. For switching between video sources (such as a
video decoder and an MPEG source), while providing a common OSD interface
using the part’s overlay and alpha capabilities.
The Bt860/861's VID port uses a PLL and FIFO to allow direct interfacing
with asynchronous video sources, such as the Bt835 video decoder.
In slave mode, the Bt860/861 can be configured to accept either
ITU-R BT.656-compliant timing (EAV and SAV codes) or ITU-R BT.601 data
timing (HSYNC* and VSYNC* signals). The Bt860/861 can also act as timing
master, producing ITU-R BT.601 timing.
The Bt860/861 supports worldwide video standards, including:
•NTSC-M (N. America, Taiwan, Japan)
•PAL-B, D, G, H, I (Europe, Asia)
•PAL-M (Brazil)
•PAL-N (Uruguay, Paraguay)
•PAL-Nc (Argentina)
•PAL-60, NTSC-443
•SECAM
The Bt860/861 has six 10-bit current-out video DACs, specifically designed
for video systems requiring the generation of high quality composite, Y/C
(S-Video), and simultaneous component YUV or RGB (SCART) video signals.
Two of the composite output signals can be programmed with a 0–7 clock
luminance delay. The connection status of each DAC can be dynamically
monitored through the serial programming interface.
The Bt860/861 has several low power options, including sleep mode (only the
serial programming interface and PLL are operational), individual DAC disable,
PLL disable, and 3.3 V operation. The 3.3 V digital inputs can be configured to
be 5 V-tolerant.
The luminance upsampling filter is enhanced to provide a narrow transition
region and a low stopband. Programmable luminance sharpness filters provide
0,1, 2, and 3.5 dB peaking options at higher video frequencies, and four reduction
filters are added for smoothed step response. To reduce the complexity of the
required reconstruction filter, 2x upsampling is implemented.
The Bt860/861 can produce internally generated colorbars and blue field
signals.
A 400 kHz serial programming interface (I
system programming.
The Bt860/861 provides support for Closed Captioning (CC) and Extended
Data Services (XDS), Teletext (WST system B), Copy Generation Management
System (CGMS), VARIS-II, and Wide Screen Signaling (WSS).
The Bt860 and Bt861 are functionally identical except that the Bt861 can
output the Macrovision 7.x anticopy algorithm.
1.2 Functional Overview
2
C-compatible) is provided for fast
D860DSAConexant1-5
Page 16
1.0 Functional DescriptionBt860/861
1.2 Functional Overview
Figure 1-2. Detailed Block Diagram
COMP1
FB
FSADJ1
FSADJ2VBIAS1 VBIAS2
VREF
Reference
Internal Voltage
FB
COMP2
Multiport YCrCb to NTSC/PAL /SECAM
DAC B
DAC A
DAC
10
Y
DAC
10
Luma
DAC C
DAC
10
CVBS
Delay
Out
Mux
U/V
DAC D
DAC
10
X
RGB
+
TTXREQTTXDAT
Color
Teletext
and CGMS
Space
Convert
DAC E
DAC
10
X
DLY
CVBS
+
10
DAC F
DAC
X
C
10
Modulator,
Mixer and
M_COMP_F
M_COMP_E
HUE_OFF
SECAM Filt.
M_COMP_D
Serial
Control
SIC
SID
10
Y
Alpha
8
2
8
OSD[7:0]
ALPHA[1:0]
Interface
ALTADDR
CRCB
Mixing
P[7:0]
10
8
656
Decoder
Sync
SYNC_AMP
Video
HSYNC*
Processor
M_Y
Timing
Control
FIELD
BLANK*
VSYNC*
9
+
X
Closed
8
VID[7:0]
Luminance
2x Upsample
Captioning,
Macrovision
Clock
PLL and
Generation
and
FIFO
Locking
VIDCLK
VIDVALID
and
Cross Color
M_CR
Control
VIDVACT
VIDHACT
Peaking Filt.
M_CB
VIDFIELD
and 2X
1.3 MHz LPF
X
XTI
CLKO
CLKIN
Matrix
Upsample/
Multiplication
Burst
XTO
Processor
BST_AMP
861_028
1-6ConexantD860DSA
Page 17
2
2.0 Inputs and Timing
2.1 Reset
The Bt860/Bt861 has the following reset methods:
•power-up reset
•RESET* pin reset
•software reset register bit
Power-up reset occurs when the part is powered-up. A pin reset occurs when
the RESET* pin is held low. (It is recommended that the pin be held low for a
minimum of 50 system clock cycles.) Both power-up and pin reset cause the
initialization of all chip functions, including video timing and serial programming
registers.
Writing a 1 to register bit SRESET (1B[7]) resets all serial programing
registers to their default states, listed in Section 5.0.
2.1.1 Initialization and Power-up Configuration
At power-up all registers reset to their initial values (see Section 5.0).
The state of the FIELD pin at power-up (or pin reset) determines the default
state of the PCLK_SEL register bit and the initial clock source. If the FIELD pin
is pulled high, the initial clock source is the CLKIN pin; if the FIELD pin is
pulled low, the initial clock source is from the PLL and requires a crystal at the
XTI and XTO pins. If not loaded, the FIELD pin is pulled low with the pin’s
internal pull-down resistor.
The power-up configuration is interlaced NTSC-M, 27 MHz black burst
video, as listed in the default values of the register bit map.
To enable active video, black burst video must be turned off by setting
NOTE:
register bit EACTIVE (1D[1]) to 1. Other video configurations must be
programmed using the part’s serial programming interface registers.
D860DSAConexant2-1
Page 18
2.0 Inputs and TimingBt860/861
2.2 Digital Video Ports
Multiport YCrCb to NTSC/PAL /SECAM
2.2 Digital Video Ports
Internally, data to the Bt860/861 is treated as either video, overlay, or alpha data.
Video data is the primary visual program content, while overlay data is used for
informational or navigational content displayed over the visual program. Alpha
data controls the pixel blending of the video and overlay content. Sufficient
flexibility exists in the Bt860/861 to allow for a variety of source and blending
configurations and interesting visual effects.
Video data is supplied by either the P (Primary Video) port, or the VID
(Secondary Video) port. Overlay data can be supplied by either the P port or the
OSD (On Screen Display) port. Alpha data can be supplied by the ALPHA port,
or embedded in the two LSBs of the overlay luminance data. Figure 2-1
illustrates the pixel latching and blending mechanism.
Figure 2-1. Pixel Latching and Blending Mechanism
ALPHA
OSD
2
8
8
P
2
OVERLAY_SEL
2
Overlay
Stream
Blend
Detection
8
4
Pixel
Blender
8
VID
VIDCLK
VIDVALID
VIDHACT
VIDVACT
VIDFIELD
CLKIN
XTI
XTO
CLKO
8
VIDEO_SEL
PLL
and
Clock
Logic
8
Video
Stream
861_042
2-2ConexantD860DSA
Page 19
Bt860/8612.0 Inputs and Timing
Multiport YCrCb to NTSC/PAL /SECAM
2.2.1 The P Port
The P port can accept video data from a variety of digital video sources. It is
designed specifically to interface directly with commercial MPEG video decoders
and D1 digital video sources. The P port supports both ITU-R BT.601 timing
(HSYNC* and VSYNC* signals), and ITU-R BT.656 timing (SAV and EAV
codes).
Data on the P[7:0] pins can be treated as either video or overlay data,
controlled by the VIDEO_SEL (1A[3]) and OVRLAY_SEL (1A[4]) register bits
(see Figure 2-1). Data on this port must be presented in 8-bit YCrCb 4:2:2 digital
video format. The P[7:0] pins are latched using the system clock as configured
using register bits PCLK_SEL (19[7]) and PCLK_EDGE (19[1]).
2.2.2 The VID Port
The VID port is specially configured for broadcast video sources, such as from a
television tuner or local cable system. It can accept a 27 MHz YCrCb 4:2:2 video
stream at the same pixel rate as the other ports, or it can accommodate alternate
clock rates, such as the 8xF
decoders. Since the time base for these sources is external to the system and
therefore asynchronous to the local pixel clock, the Bt860/861 provides a
mechanism that synchronizes these two domains. When using the VID port in
locking mode, the Bt860/861 immediately synchronizes its vertical timing to the
vertical timing presented on the VIDVACT pin, and gradually adjusts its
horizontal timing and clock rate to further synchronize with the VID port.
VIDCLK latches the incoming data into a FIFO, and data is extracted at the
appropriate pixel rate for internal processing.
The average active horizontal pixel count must be equal to the value
programmed into the HACTIVE register field. For example, the Bt835 generates
pixels at a rate of 14.32 Mpix/s when used for NTSC video capture, but the actual
valid pixel count per line is determined by the video mode required. For support
of 27 MHz streams, 720 valid pixels will be delivered per line. This configuration
is compatible with other video devices connected to the Bt860/861 and running
with a continuous pixel rate of 13.5 Mpix/s. The Bt860/861 will generate the
necessary video timing and pixel clock to act as master for the other video device.
The VID port can be configured as the video source by setting register bit
VIDEO_SEL (1A[3]) to 1. Data on this port must be presented in 8-bit YCrCb
4:2:2 digital video format.
2.2 Digital Video Ports
clock rate used by the Bt835 family of video
sc
2.2.3 The OSD Port
The OSD port is functionally very similar to the P port, except that it cannot decode
ITU-R BT.656 timing. As the overlay source, this port can be mixed with the video
stream using one of the alpha-mixing modes described in Section 2.2.5. While
intended as an overlay source, the OSD port can be configured to be the sole image
content by using the appropriate blend programming.
The overlay source is selected by setting register bit OVRLAY_SEL (1A[4])
to 1. Data on this port must be presented in 8-bit YCrCb 4:2:2 digital video
format. The OSD[7:0] pins are latched using the system clock as configured by
register bits PCLK_SEL (19[7]) and PCLK_EDGE (19[1]).
D860DSAConexant2-3
Page 20
2.0 Inputs and TimingBt860/861
2.2 Digital Video Ports
Multiport YCrCb to NTSC/PAL /SECAM
2.2.4 Overlay Modes and Alpha Blending
The Bt860/861 can be configured to display only a single video stream, or to mix
any combination of two data ports (P, VID, and OSD). Programming register field
ALPHAMODE (1A[6:5]) to 00 and register bit BLENDMODE (1A[7]) to 1
selects the internal video bus as the sole source of data, regardless of the alpha
source. In this mode, either the VID port or the P port can be used as the video
source, which is selected by register bit VIDEO_SEL (1A[3]). Other
combinations of the ALPHAMODE and BLENDMODE programming will allow
blending of the video and overlay buses. Table 2-1 lists all valid input modes.
Table 2-1. Alpha Blending Configurations
ConfigurationProgramming
Use
Video source
VIDNoneNoneNone100 1XNo
VIDPALPHA[1:0]1 bit
VIDPALPHA[1:0]2 bit
VIDPALPHA[1:0]4 bit
VIDPP LSBs2 bit
VIDOSDALPHA[1:0]1 bit
VIDOSDALPHA[1:0]2 bit
VIDOSDALPHA[1:0]4 bit
VIDOSDOSD LSBs2 bit
PNoneNoneNone
POSDALPHA[1:0]1 bit
POSDALPHA[1:0]2 bit
POSDALPHA[1:0]4 bit
POSDOSD LSBs2 bit
Data from the overlay source may be applied with varying levels of
transparency, from fully transparent, no overlay, to fully opaque, full overlay. A
4-bit blend multiplier provides sixteen levels of mixing. The value 1111 is a
special case allowing the overlay data to pass completely unmixed. In all other
cases the value applied to the video path is (1 – blend / 16), and the value applied
to the overlay path is (blend / 16), where blend is the 4-bit multiplier value.
Two methods are used to generate the 4-bit multiplier. The multiplier value
can come either from a four-entry by 4-bit lookup table (LUT), or directly from
the ALPHA pins. In both cases, the blend multiplier value will be applied to both
luma and chroma for the co-sited components (Cb0:Y0:Cr0) and a separate
multiplier applied for the (Y1) component.
2-4ConexantD860DSA
Page 21
Bt860/8612.0 Inputs and Timing
Multiport YCrCb to NTSC/PAL /SECAM
2.2.5 Alpha Pin Blending
The ALPHA[1:0] pins are used to select the amount of blending per pixel when
BLENDMODE = 1. The pins are sampled at the system clock rate and samples
during both luma and chroma components may be captured to create 1-, 2-, or
4-bit blend factors. For 1- and 2-bit blend modes, the multiplier LUT (in registers
ALPHA_LUT_0 through ALPHA_LUT_3 is programmed with user-defined
multiplier values.
In 1-bit blend mode, the ALPHA[0] pin indexes registers ALPHA_LUT_0
and ALPHA_LUT_3 to generate the multiplier value. In 2-bit blend mode, the
ALPHA[1:0] pins are used as a 2-bit index for registers ALPHA_LUT_0 through
ALPHA_LUT_3.
In 4-bit blend mode, the four bits required are captured in successive load
clocks from ALPHA[1:0]. The two LSBs of the 4-bit value are latched during the
luma portion of the overlay data load, and the two MSBs are latched during the
chroma component load. These four bits provide a direct multiplier for the
blending module. Figure 2-2 illustrates the alpha blending timing diagram.
1. Shaded areas indicate which video components are affected by each multiplier or index.
2. A blank data packet means this data carries no alpha information.
A[1]
A[0]
A[0]
A[1]
A[0]
3
3
3
2
2
2
2
2
A[1]
A[0]
A[0]
A[1]
A[0]
3
3
3
3
3
861_026
2.2.6 Content-based Blending
Content-based blending uses the two LSBs of the overlay byte associated with the luma
pixel to address the multiplier lookup table (registers ALPHA_LUT_0 through
ALPHA_LUT_3). This method is selected by setting BLENDMODE = 0, and is a
convenient means of using blending when no alpha pins exist from the overlay device.
D860DSAConexant2-5
Page 22
2.0 Inputs and TimingBt860/861
2.3 Configurations and Timing
Multiport YCrCb to NTSC/PAL /SECAM
2.3 Configurations and Timing
The Bt860/861 is capable of various ITU-R BT.601, ITU-R BT.656, and
decoder-locked configurations. Table 2-2 lists several ITU-R BT.601 and
ITU-R BT.656 configurations, and Section 2.3.3 discusses decoder-locked
configurations. In any of these configurations, it is possible to synchronize a
primary video source with an alternate video source. These two sources can then
be alpha-mixed, or independently selected for external display. Alpha mixing is
discussed in detail in Section 2.2.5.
Table 2-2. Configurable Timing States
Description
Bt860/861 is timing master,
HSYNC*, VSYNC*, and FIELD
are outputs.
(1)
Timing
Mode
,
1001
SLAVEEN_656SYNC_CFG
Bt860/861 is timing slave, timing
derived from HSYNC*, VSYNC*,
and BLANK* signals
Bt860/861 is timing slave, timing
derived from ITU-R BT .656 codes.
HSYNC*, and VSYNC* are
unused.
Bt860/861 is timing slave, timing
derived from ITU-R BT .656 codes.
HSYNC*, VSYNC*, and FIELD
are outputs.
NOTE(S):
(1)
Decoder locking using the VID port requires the part to be in timing mode 1, except
SYNC_CFG = 1 is only required if synchronization with other sources is required.
(2)
Either the BLANK* pin or the HBLANK, VBLANK, HACTIVE, and VACTIVE register can be
used for blanking.
3. Configurations not listed are not recommended.
4. X = Don’t care.
(2)
.
(1)
210X
3110
4111
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Page 23
Bt860/8612.0 Inputs and Timing
Multiport YCrCb to NTSC/PAL /SECAM
2.3.1 ITU-R BT.601 Configurations and Timing
Master and slave ITU-R BT.601 configurations are listed in Table 2-2 as timing
modes 1 and 2. Timing mode 1 is the ITU-R BT.601 master mode. An example
connection diagram is illustrated in Figure 2-3. In this example, both video
sources are slaved to the Bt860/861.
.
Figure 2-3. Timing Mode 1 Connection Example
Video SlaveBt860/861
8
Optional OSD Source, Timing Slave
P[7:0]
HSYNC*
VSYNC*
CLKO
FIELD
2.3 Configurations and Timing
(1)
NOTE(S):
(1)
It is not required that the clock be sourced from the Bt860/861.
8
2
OSD[7:0]
ALPHA[1:0]
XTIXTO
861_009
D860DSAConexant2-7
Page 24
2.0 Inputs and TimingBt860/861
2.3 Configurations and Timing
Timing mode 2 is the ITU-R BT.601 slave mode. An example connection
diagram is illustrated in Figure 2-4. In this example, the source feeding the P port
is the timing master, and both the optional OSD source and the Bt860/861 are
timing slaves. Although additional sources are shown in these diagrams, it is not
necessary to have more than one video source.
Figure 2-4. Timing Mode 2 Connection Example
Video MasterBt860/861
Optional OSD Source, Timing Slave
Multiport YCrCb to NTSC/PAL /SECAM
8
8
P[7:0]
HSYNC*
VSYNC*
(1)
CLKIN
BLANK*
OSD[7:0]
NOTE(S):
(1)
It is not required that the clock is sourced external to the Bt860/861.
When the Bt860/861 is configured for ITU-R BT.601 timing, the HSYNC*,
VSYNC*, FIELD, and BLANK* pins synchronize the Bt860/861 to external
video sources. In master mode, HSYNC* field, and VSYNC* are outputs and the
BLANK* pin is not used. All timing is generated internally and blanking is
determined by the HBLANK, VBLANK, HACTIVE, and VACTIVE registers. In
slave mode, HSYNC*, VSYNC* and BLANK* are inputs and the encoder’s
timing is controlled by an external master. Blanking is set either by the internal
HBLANK, VBLANK, HACTIVE, and VACTIVE registers (register bit
BLK_IGNORE = 1) or by a blanking signal on the BLANK* pin (register bit
BLK_IGNORE = 0).
2
ALPHA[1:0]
861_007
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Page 25
Bt860/8612.0 Inputs and Timing
Multiport YCrCb to NTSC/PAL /SECAM
If the registers are used to determine video blanking (register bit
BLK_IGNORE = 1), the first component of the first active pixel of a line should
be presented to the encoder at HBLANK + 2 rising system clock edges after the
falling edge of HSYNC* for master mode, and HBLANK + 3 rising system clock
edges after the falling edge of HSYNC* for slave mode. The correct order of the
pixel components is Cb
timing relationship.
Blanking times (t1) are listed in Tables 3-1 through 3-4. Desired front porch blanking is set by the HBLANK register.
HBLANK = t1 + 14
(2)
The number of active pixels per line (t2) is set by the HACTIVE register.
(3)
The total number of system clocks per line (t3) is set by the HCLK register.
(4)
The first component of the first active pixel of the line should be placed HBLANK + 2 (or 3 for slave mode) rising system
clock edges after falling HSYNC*(t
(5)
When the BLANK* pin is used, the first component of the first pixel must arrive 3 rising system clock edges after the
falling edge of BLANK* (t
).
5
) in order to coincide with the end of horizontal blanking.
4
If the BLANK* signal is used to determine video blanking (in slave mode
only), the first component of the first active pixel of a line should be presented to
the encoder three rising system clock edges after the falling edge of the BLANK*
signal. Figure 2-5 illustrates this relationship.
861_006
D860DSAConexant2-9
Page 26
2.0 Inputs and TimingBt860/861
2.3 Configurations and Timing
The HBLANK register sets the line blanking time from the midpoint of the
falling edge of the analog horizontal sync pulse to the end of blanking. The
HACTIVE register sets the number of active pixels after the horizontal blanking
period has ended. See Tables 3-1 through 3-4 for appropriate HBLANK and
HACTIVE programming values for various NTSC, PAL, and SECAM video
standards.
Pixel and data timing (P, OSD, ALPHA, HSYNC*, VSYNC*, BLANK*) are
by default, latched into the Bt860/861 on the rising edge of the system clock, but
can be latched on the falling edge of the system clock if register bit PCLK_EDGE
(19[1]) is set high. The system clock can be seen on CLKO or CLKIN when
appropriate. Legal setup and hold times must be observed.
2.3.2 ITU-R BT.656 Timing
Data on the P port can be routed through the part’s ITU-R BT.656 timing
translator only when the system clock is 27 MHz, by setting register bit
EN_656 (1A[2]) high. This is accomplished using timing modes 3 or 4 (see
Table 2-2). Figure 2-6 illustrates an example connection diagram. ITU-R BT.656
timing derives vertical and horizontal timing information from the video data
stream (SAV and EAV codes). These codes are internally converted to HSYNC*
and VSYNC* signals, which can be then be produced on the Bt860/861’s
HSYNC*, VSYNC*, and FIELD pins. ITU-R BT.656 timing (also known as D1
timing) is illustrated in Figures 2-7 and 2-8. The resultant video is automatically
aligned to conform to ITU-R BT.656 video and blanking placement. The contents
of the HBLANK, HACTIVE, VACTIVE, and VBLANK registers are ignored,
except when register bit BLK_IGNORE = 1.
Multiport YCrCb to NTSC/PAL /SECAM
Figure 2-6. Timing Mode 3 and 4 Connection Example
CCIR656 Timing, Video MasterBt860/861
OSD Source, Timing Slave
NOTE(S):
(1)
It is not required that the clock is sourced external to the Bt860/861.
8
8
2
P[7:0]
(1)
CLKIN
OSD[7:0]
HSYNC*
VSYNC*
FIELD
ALPHA[1:0]
861_010
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Page 27
Bt860/8612.0 Inputs and Timing
Multiport YCrCb to NTSC/PAL /SECAM
Figure 2-7. 625 Line ITU-R BT.656 Timing
Analog Line n – 1
n
Digital Line
Luminance Samples
717 718
Cr Samples
Cb Samples
– 1Digital Line
719 720721730731 732733862863012
35936036536643101
12
2.3 Configurations and Timing
O
H
Digital Blanking
T
Analog Line
132
n
n
T
35936036536643101
T
: luminance sampling period
Figure 2-8. 525 Line ITU-R BT.656 Timing
Analog Line n – 1
n
Digital Line
Luminance Samples
717 718
Cr Samples
– 1Digital Line
719 720721734735 736737856857012
35936036736842801
16
861_005a
O
H
Digital Blanking
T
Analog Line
122
n
n
T
Cb Samples
35936036736842801
T
: luminance sampling period
861_005b
D860DSAConexant2-11
Page 28
2.0 Inputs and TimingBt860/861
2.3 Configurations and Timing
In this configuration, the Bt860/861 is a slave to the ITU-R BT.656 data
stream. However, the HSYNC*, VSYNC* and FIELD pins can be configured as
outputs for synchronization with a video slave on the OSD port. While in this
configuration, the HSYNC*, VSYNC*, and FIELD timing is identical to
ITU-R BT.601 master mode timing.
2.3.3 VID Port (Video Decoder Locked) Timing
The VID port can accept video signals from a video decoder, such as the Bt835,
and is buffered using a FIFO to support asynchronous video streams. The internal
logic will automatically pulls data from the FIFO when required. The data lines
for the VID port are VID[7:0], and the control lines are VIDCLK, VIDHACT,
VIDVACT, VIDFIELD, and VIDVALID. Figure 2-9 illustrates an example
configuration using the Bt835 and the Bt860. The PLL and the horizontal and
vertical counters are adjusted to track the incoming data on the VID port. The
Bt860/861 can be configured to output HSYNC* and VSYNC* signals in order
to synchronize with the P, OSD, and ALPHA signals. Timing mode 1 must be
used when the VID port is selected in conjunction with a source on the P or OSD
ports. The PLL (using the XTI and XTO inputs) must be selected as the system
clock source.
Multiport YCrCb to NTSC/PAL /SECAM
2-12ConexantD860DSA
Page 29
Bt860/8612.0 Inputs and Timing
Multiport YCrCb to NTSC/PAL /SECAM
Figure 2-9. Video Decoder Connection Example
Bt835 Video DecoderBt860/861
VD[15:8]
CLKX2
VALID
ACTIVE
VACTIVE
FIELD
MPEG-2 Decoder
Graphic Processor
2.3 Configurations and Timing
8
8
8
VID[7:0]
VIDCLK
VIDVALID
VIDHACT
VIDVACT
VIDFIELD
P[7:0]
CLKO
HSYNC*
VSYNC*
FIELD
OSD[7:0]
2
ALPHA[1:0]
XTIXTO
Follow these steps to lock a video decoder to this port:
Connect to the data and control pins as illustrated in Figure 2-9.
1.
Select the correct effective clock frequency using the PLL_FRACT and
2.
PLL_INT registers, and choose the XTAL inputs as the system clock
source using register bit PCLK_SEL (19[7]). See Section 2.4.1, and the
PLL_FRACT and PLL_INT register descriptions.
Set these locking registers to the following values:
3.
FIELD NAMEVALUE
XL_MDSEL[1:0]11
XL_SATEN1
XL_SAT[3:0]1
Set the part for Timing Mode 1 (see Table 2-2).
4.
Initiate locking by setting the LOCK (1C[5]) register bit high and the
5.
LC_RST (1C[6]) register bit low.
861_008
When unlocking the Bt861 to a source on the VID port, set the
NOTE:
LOCK (1C[5]) register bit low and the LC_RST (1C[6]) register bit high.
D860DSAConexant2-13
Page 30
2.0 Inputs and TimingBt860/861
2.4 Clock Selection
2.4 Clock Selection
The internal pixel clock (PCLK) can be derived from either the CLKIN input or
the crystal inputs. The PCLK_SEL register bit (19[7]) controls which of these
two inputs will become the pixel clock.
2.4.1 Crystal Inputs and the PLL
The crystal inputs (XTI and XTO) drive a buffered oscillator to create a clock.
This clock is routed through the PLL if register bit BY_PLL (1D[3]) is 0, and
bypasses the PLL untouched if BY_PLL is 1. Figure 2-10illustrates the clock
block diagram. If PCLK_SEL is low, this becomes the system clock.
The PLL_FRACT and the PLL_INT registers determine the PLL clock
frequency multiplier. The default setting generates a 27.0 MHz clock, using a
14.31818 MHz crystal.
If the VID port is enabled using the LOCK (1C[5]) register bit, the PLL is
controlled by the tracking servo mechanism.
The frequency programmed through PLL_FRACT and PLL_INT is used as a
base around which the VID port locking mechanism adjusts the system clock.
The PLL_FRACT and PLL_INT registers remain unaffected by the locking
mechanism, and when locking is disabled (through the LOCK bit), the
PLL_FRACT and PLL_INT registers once again determine the exact PLL
frequency.
Multiport YCrCb to NTSC/PAL /SECAM
Figure 2-10. Timing and Clock Block Diagram
OSD[7:0]
P[7:0]
HSYNC*
VSYNC*
BLANK*
CLKIN
XTI
XTO
CLKO
VIDCLK
VID[7:0]
8
8
CCIR656
8
Timing
Translator
3
Xtal
Inverter
and Buffer
88
FIFO
3
1
0
EN_656
PLL
OSD[7:0]
P[7:0]
VID[7:0]
3
Encoder
Timing
Block
SLAVE
1
0
BY_PLL
System
Block
PCLK_SEL
1
0
CLKO_DIS
System
Clock
861_025
2-14ConexantD860DSA
Page 31
3.1.1 Video Standards
3
3.0 Digital Processing and Functionality
3.1 Video
The Bt860/861 supports worldwide video standards, including NTSC-M
(N. America, Taiwan, Japan), PAL-B, D, G, H, I (Europe, Asia), P AL-M (Brazil),
PAL-N (Uruguay, Paraguay), PAL-Nc (Argentina), PAL-60, NTSC-443, and
SECAM.
Table 3-1 lists the target video timing and amplitude used to generate the
appropriate register programming for various forms of NTSC, PAL, and SECAM
as listed in Tables 3-2, 3-3, and 3-4 respectively. These tables provide the
programming values of only those registers required to create that particular
video standard. Ancillary data, input configuration, and ignored or common value
register values are not shown. Video parameter registers which are not relevant to
a particular standard are described as such in the register detail section of this
document.
Table 3-2 lists the register values required to program the various forms of
PAL and NTSC in ITU-R BT.601 resolution, and Table 3-3 lists the register
values required to program the various forms of PAL and NTSC in square pixel
resolution. Table 3-4 lists register values required to program the encoder for
SECAM output, with and without synchronization bottleneck pulses.
Internal timing and the values programmed into the registers reference the analog VSYNC pulse (O
Parameter
Description
Interlace Off
Phase Alternation
Subcarrier Phase
Offset
Subcarrier Reset
SETUP
Sync Tip to Blank
Amplitude
Number of Active
Lines
Number of Blanked
Lines from O
Analog and Digital
Vertical Sync
Table 3-3. Register Programming Values for NTSC and PAL Video Standards (Square Pixel) (2 of 2)
Cb Multiplier
Cr Multiplier
Y Multiplier
Subcarrier
Increment
Duration
NOTE(S):
D860DSAConexant3-7
Page 38
Bt860/861
3
Multiport YCrCb to NTSC/PAL /SECAM
Table 3-4. Register Programming Values for SECAM
System Clock Frequency
Parameter DescriptionRegister NameRegister Number
(MHz)
2729.5
Number of Lines625 Line16[5]11
Width of Analog Horizontal Sync PulseAHSYNC_WIDTH08[7:0]7F8B
Cross Color Filtering OffCR0SSFILTID[0]00
Upper Db LimitDB_MAX34[1:0]/33[7:0]5A3529
Lower Db LimitDB_MIN36[1:0]/35[7:0]49F43B
Upper Dr LimitDR_MAX30[1:0]/2F[7:0]5A3529
Lower Dr LimitDR_MIN32[1:0]/31[7:0]49F43B
Bottleneck PulsesFIELD_ID1B[6]
(1)
0
FM ModulationFM16[2]11
Number of Active Pixels per LineHACTIVE07[1:0]/06[7:0]2C0300
Number of System Clocks from O
to
H
HBLANK0C[1:0]/0B[7:0]128140
Active Video
Beginning of SubcarrierHBURST_BEG09[7:0]97A5
Number of System Clocks Per LineHCLOCK05[3:0]/04[7:0]6C0760
Cb MultiplierM_CBA2949A
Cr MultiplierM_CRC5B5BB
Y MultiplierM_Y22[7:0]A4A4
Subcarrier Increment for DbMSC_DB2D[7:0]/2C[7:0]
284BDA1324E1A08B
2B[7:0]/2A[7:0]
Subcarrier Increment for DrMSC_DR29[7:0]/28[7:0]
29C71C72263CBEEA
27[7:0]/26[7:0]
Interlace OffNI16[1]00
Phase AlternationPAL16[3]00
Programmable Subcarrier ModePROG_SC1A[1]00
Subcarrier AmplitudeSC_AMP868685
Subcarrier Phase PatternSC_PATTERN1A[0]00
SetupSETUP16[4]00
Sync Tip to Blank AmplitudeSYNC_AMP1E[7:0]F0F0
Number of Active LinesVACTIVE0F[0]/0E[7:0]11F11F
Number of Blanked Lines from O
(2)
V
VBLANK0D[7:0]1717
Analog and Digital Vertical Sync DurationVSYNC_DUR16[6]11
NOTE(S):
(1)
(2)
To enable synchronization bottleneck pulses, this bit must be 1.
Internal timing and the values programmed into the registers reference the analog VSYNC pulse (OV) as line #1 (see
Figures 3-1 and 3-2).
(1)
0
3-8ConexantD860DSA
Page 39
Bt860/8613.0 Digital Processing and Functionality
3
Multiport YCrCb to NTSC/PAL /SECAM
3.1 Video
3.1.2 Analog Horizontal Sync
3.1.3 Analog and Digital Vertical Sync
3.0 Digital Processing and Functionality
3.1.1
Figure 3-1. NTSC Vertical Timing
3.1 Video
The duration of the horizontal sync pulse is determined by register
HSYNC_WIDTH (12[7:0]). The beginning of the horizontal sync pulse
corresponds to the reset of the internal horizontal pixel counter. The sync rise and
fall times are automatically controlled. The horizontal and vertical sync
amplitude is programmable using register SYNC_AMP (IE[7:0]).
The duration of the analog and digital vertical sync is determined by register bit
VSYNC_DUR (16[6]). If VSYNC_DUR = 0, 3.0 lines are selected; if
VSYNC_DUR = 1, 2.5 lines are selected. Tables 3-2, 3-3, and 3-4 list the
appropriate VSYNC_DUR settings for all supported standards.
Figures 3-1 and 3-2 illustrate 3.0 and 2.5 lines respectively.
(1)
O
V
Odd Field
NOTE(S):
(1)
Internal timing considers this point the start of the field (vertical reset).
Even Field
861_032
D860DSAConexant3-9
Page 40
3.0 Digital Processing and FunctionalityBt860/861
3.1 Video
Figure 3-2. PAL Vertical Timing
(1)
O
V
NOTE(S):
(1)
Internal timing considers this point the start of the field (vertical reset).
Multiport YCrCb to NTSC/PAL /SECAM
Odd Field
Even Field
861_033
3.1.4 Analog Video Blanking
In master mode, and when register bit BLK_IGNORE = 1 in slave mode, register
fields HBLANK, VBLANK, HACTIVE, and VACTIVE control analog video
blanking. Together they define the active region, where pixels will be displayed.
VBLANK defines the number of lines from the leading edge of the analog
vertical sync (O
defines the number of active lines. HBLANK defines the number of system
clocks (minus 14) from the leading edge of horizontal sync to the first active
pixel. HACTIVE defines the number of active pixels per line.
In the slave mode, when BLK_IGNORE = 0, the BLANK* pin determines
analog blanking. The video from the start of horizontal sync through the end of
the burst, as well as the vertical lines with serration and equalization pulses is
automatically blanked.
) to the first active line (see Figures 3-1 and 3-2). VACTIVE
v
3-10ConexantD860DSA
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Bt860/8613.0 Digital Processing and Functionality
Multiport YCrCb to NTSC/PAL /SECAM
3.1.5 Subcarrier and Burst Generation
The Bt860/861 uses a 32-bit subcarrier increment to synthesize the subcarrier.
The value of the subcarrier increment required to generate the desired subcarrier
frequency for NTSC and PAL formats is found by:
M_SC_DR[31:0] = int (2
where f
frequency.
When available, use the relationship between HCLK and the subcarrier frequency
as given in ITU-R BT.470. For example:
Tables 3-2 and 3-3 lists the programming values for common NTSC and P AL
standards.
For SECAM formats, the two subcarrier frequency increments are defined by:
SECAM Dr: M_SC_DR[31:0] = int [(f
SECAM Db: M_SC_DB[31:0] = int [(f
Table 3-4 lists standard programming values for SECAM.
The HBURST_BEG register determines the start of burst (or subcarrier for
SECAM). In PAL and NTSC video formats the HBURST_END register
determines the end of the burst. The BURST_AMP register controls burst
amplitude. The burst is automatically blanked during the horizontal sync to
prevent generation of invalid sync pulses. Burst blanking is automatically
controlled and depends on which video format is selected. Burst rise and fall
times are internally controlled.
The SC_AMP register controls the SECAM subcarrier amplitude. In addition,
generation of the “bottleneck signals” for subcarrier line synchronization may be
enabled using the FIELD_ID register bit. Registers PROG_SC and
SC_PATTERN allow control of active line placement and subcarrier phase
sequencing.
is the encoder system clock rate and fsc is the desired subcarrier
clk
32
× fsc / f
clk
+ 0.5)
/ f
sc
/ f
sc
) × 232 + 0.5]
clk
) × 232 + 0.5]
clk
32
+ 0.5}
3.1 Video
32
+ 0.5}
D860DSAConexant3-11
Page 42
3.0 Digital Processing and FunctionalityBt860/861
3.1 Video
3.1.6 Subcarrier Phasing (SC_H Phase)
For PAL and NTSC video formats, the subcarrier phase is set to 0 on the leading
edge of the analog vertical sync every four (NTSC) or eight (PAL) fields, unless
the SC_RESET bit is set to a logical 1. This is true for both interlaced and
non-interlaced outputs. In addition, the subcarrier phase can be adjusted by the
PHASE_OFF register. Each LSB change of PHASE_OFF corresponds to a
360 / 256 degree change in the phase.
Setting SC_RESET to 1 is useful when the subcarrier phase at the end of a
color field sequence is significantly different from 0.
3.1.7 Noninterlaced Operation
When programmed for noninterlaced master mode, the Bt860/861 always
displays the odd field. The FIELD signal stays low to indicate that the field is
always odd. A 30 Hz offset should be subtracted from the color subcarrier
frequency while in NTSC mode so the color subcarrier phase will be inverted
from field to field. Transition from interlaced to noninterlaced in master mode
occurs during odd fields to prevent synchronization disturbance.
Consumer VCRs can record noninterlaced video with minor noise
NOTE:
artifacts, but special effects (e.g., scan >2x) may not function properly.
Multiport YCrCb to NTSC/PAL /SECAM
3-12ConexantD860DSA
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Bt860/8613.0 Digital Processing and Functionality
Multiport YCrCb to NTSC/PAL /SECAM
3.2 Effects
3.2.1 Chrominance Disable
Setting register bit DCHROMA (17[2]) to 1 turns off the chrominance subcarrier
and colorburst.
3.2.2 Internal Filtering
Once the input data is converted to internal YUV format, the Y and UV
components are filtered and upsampled to the system clock frequency.
The luminance signal is always low-pass filtered using the upsampling filter
response illustrated in Figure 3-3. Additional peaking or reduction filters can be
enabled (see Figures 3-4 and 3-5), using the PKFIL_SEL register field and the
FIL_SEL register bit. When register bit FIL_SEL is set to 0, register field
PKFIL_SEL selects the peaking filters illustrated in Figure 3-7. When register bit
FIL_SEL is set to 1, register field PKFIL_SEL selects the reduction filters
illustrated in Figure 3-6. The peaking filters are optimized for high bandwidth
frequency response, and the reduction filters are optimized for step response
performance.
The default chrominance filter response is illustrated in Figure 3-8, but an
alternate wide bandwidth response can be selected using register bit
CHROMA_BW, as illustrated in Figure 3-9.
SECAM pre-emphasis filter responses are illustrated in Figures 3-10 and 3-11.
.
3.2 Effects
Figure 3-3. Luminance Upsampling FilterFigure3-4. Luminance Upsampling Filter with Peaking
and Reduction Options
0
–10
–20
–30
–40
Amplitude in dB
–50
–60
–70
–80
024681012
Frequency in MHz
861_015
0
–10
–20
–30
Amplitude in dB
–40
–50
–60
024681012
Frequency in MHz
861_016
D860DSAConexant3-13
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3.0 Digital Processing and FunctionalityBt860/861
3.2 Effects
Figure 3-5. Close-Up of Luminance Upsampling Filter
Figure 3-9. Chrominance Wide Bandwidth FilterFigure3-10. SECAM High Frequency Pre-emphasis
Filter
0
–10
–20
–30
Amplitude in dB
–40
–50
–60
0123456
Frequency in MHz
861_023a
6
4
2
0
8
6
Amplitude in dB
4
2
0
3.544.55
Frequency in MHz
861_021
3-14ConexantD860DSA
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Bt860/8613.0 Digital Processing and Functionality
Multiport YCrCb to NTSC/PAL /SECAM
Figure 3-11. SECAM Low Frequency Pre-emphasis
Filter
10
8
6
4
Amplitude in dB
2
0
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91
Frequency in MHz
861_023
3.2.3 Internal Colorbars, Blue Field, and Black Burst
The Bt860/861 can be configured to generate 100% amplitude, 75% saturation
(100/7.5/75/7.5 for NTSC/PAL-M with set-up, 100/0/75/0 for PAL/SECAM)
colorbars by setting register bit ECBAR (17[1]) bit to a 1. The Bt860/861 can also
produce a blue field by setting register bit BLUE_FLD (17[6]) to 1, and black
burst by setting register bit EACTIVE (1D[1]) to 0. Pixel inputs are ignored while
any of these waveforms are being produced.
Example colorbars for different output formats are illustrated in Figures 3-12,
3-13, and 3-14. Specific levels are listed in Tables 3-5 through 3-8.
3.2 Effects
D860DSAConexant3-15
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3.0 Digital Processing and FunctionalityBt860/861
3.2 Effects
Figure 3-12. YUV Video Format (Internal Colorbars)
White
A
wht
A
sync
y
A
wht
V(Pb)
Multiport YCrCb to NTSC/PAL /SECAM
Yellow
A
yel
A
yel
Cyan
A
cyn
A
cyn
Green
A
grn
A
grn
A
mgt
A
Magenta
mgt
Red
A
red
A
red
Blue
A
blu
A
blu
Black
A
blk
A
blk
A
A
wht
yel
U(Pr)
A
cyn
NOTE(S):
All “Ax“ values are relative to black, except for A
blk
and A
, which are relative to blank.
sync
Table 3-5. 100/0/75/0 Colorbars as Described in EIA-770.1. EIA-770.1
(1)
A
sync
Y (volts)
0.2860.7140.4650.3680.3090.2170.1570.0600
–
Pr (volts)000.043
Pb (volts)00
NOTE(S):
(1)
EIA-770.1 states that setup can be either “none or 7.5" IRE.
If setup = 0, then A
2. All “Ax” values are relative to black, except A
A
wht
= 714 V, but if setup = 7.5 IRE, then A
wht
A
yel
0.2620.089
–
blk
–
, and A
A
0.262
cyn
A
grn
0.2200.2200.262
–
0.1740.174
–
= 0.661 V.
wht
which are relative to blank.
sync
A
mgt
A
grn
A
mgt
A
A
0.0890.2620
–
red
red
A
A
blu
blk
A
blu
0.0430
–
861_012
(1)
A
blk
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Bt860/8613.0 Digital Processing and Functionality
Multiport YCrCb to NTSC/PAL /SECAM
Figure 3-13. RGB Video Format (Internal Colorbars)
White
A
wht
R
A
wht
G
3.2 Effects
Yellow
A
yel
A
yel
Cyan
A
cyn
A
cyn
A
A
grn
grn
Green
A
mgt
A
mgt
Magenta
A
A
red
red
Red
Blue
A
blu
A
blu
Black
A
blk
A
blk
wht
A
yel
A
A
cyn
A
grn
A
mgt
A
red
A
blu
A
blk
B
NOTE(S):
All “Ax“ values are relative to black, except for A
blk
and A
, which are relative to blank.
sync
861_013
Table 3-6. 100/0/75/0 Colorbars for a 625-Line System
(1)
A
sync
R (volts)00.7000.525000.5250.52500
G (volts)00.7000.5250.5250.5250000
B (volts)00.70000.52500.52500.5250
NOTE(S):
(1)
The Bt860/861 supports RGB that employes an external sync signal. For external sync, use the composite or S-Video
luminance waveform.
2. Complies with SMPTE 253.
3. All “A
” values are relative to black, except A
x
A
wht
A
yel
blk
, and A
A
cyn
sync
A
grn
which are relative to blank.
A
mgt
A
red
A
blu
A
blk
D860DSAConexant3-17
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3.0 Digital Processing and FunctionalityBt860/861
3.2 Effects
Figure 3-14. Composite and S-Video Format (Internal Colorbars)
White
Yellow
M
yel
A
wht
A
yel
A
cyn
A
wht
A
yel
A
cyn
Composite
M
A
sync
A
sync
b
y
Multiport YCrCb to NTSC/PAL /SECAM
Cyan
Green
Magenta
Red
Blue
Black
M
cyn
M
grn
M
mgt
M
red
A
grn
A
mgt
A
A
red
A
red
A
grn
A
mgt
A
blk
M
blu
blu
A
blu
A
blk
S Video
M
b
M
wht
M
M
cynM
C
yel
NOTE(S):
1. A is the DC (luminance) amplitude referenced to black, except for A
x
2. M numbers are the peak-to-peak amplitudes of the subcarrier waveform.
x
Table 3-7. Composite and Luminance Amplitude
Y and
Composite
A
sync
A
wht
A
yel
A
cyn
Amplitudes
NTSC-M (volts)
NTSC-J (volts)
PAL-B (volts)
NOTE(S):
Ax is the DC (luminance) amplitude referenced to black, except for A
0.2860.6610.4410.3470.2920.2030.1490.0540.0536
–
0.2860.7140.4770.3750.3160.2200.1610.0590
–
0.3000.7000.4650.3680.3080.2170.1570.0600
–
blk
blk
A
grn
and A
M
mgt
grn
and A
sync
, which are referenced to blank.
sync
A
mgt
, which are referenced to blank.
M
M
blu
red
A
red
M
blk
Blank
Level
861_011
A
blu
A
blk
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Bt860/8613.0 Digital Processing and Functionality
Multiport YCrCb to NTSC/PAL /SECAM
Table 3-8. Composite and Chrominance Magnitude
C and
Composite
Magnitudes
NTSC-M (volts)0.28600.4440.6300.5890.5890.6290.4440
NTSC-J (volts)0.28600.4800.6810.6360.6360.6810.4800
PAL-B (volts)0.30000.4700.6630.6200.6200.6640.4700
M
numbers are the peak-to-peak amplitudes of the subcarrier waveform.
x
M
b
M
wht
M
yel
M
cyn
M
grn
M
mgt
M
red
M
3.2 Effects
blu
3.2.4 Setup
Setting the SETUP register bit to 1 places a 0.054 V (7.5 IRE) pedestal between
blank and black. SETUP only affects Composite, Y of S-Video, Y of YUV, and
RGB waveforms.
3.2.5 YUV and RGB Multipliers
M
blk
When the output format of DACs D, E, and F is YUV or RGB, registers
M_COMP_D (23[7:0]), M_COMP_E (25[7:0]) and M_COMP_F (24[7:0]) are
amplitude multipliers. The gain range is from 0x to 2x, where a register value of
0x80 gives a gain of 1.
3.2.6 Programming Values to Comply with YPrPb and RGB
To comply with EIA 770.1 on 525-line systems for YPrPb values (listed in
Table 3-5), start with the programming values listed in Table 3-2, then use these
multipliers:
Value
Register
0x230x800x80
0x240x900x90
0x250x660x66
To attain the RGB values shown in Table 3-6, start with the programming values
listed in Table 3-2, then use these multipliers:
Register
0x230x80
0x240x80
0x250x80
(NTSC-J)
Value
(PAL-B, D, G, H, I)
(NTSC-M)
Value
D860DSAConexant3-19
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3.0 Digital Processing and FunctionalityBt860/861
3.2 Effects
Multiport YCrCb to NTSC/PAL /SECAM
3.2.7 Programmable Video Adjustments Controls
Registers Y_OFF, M_Y, M_CB, M_CR, and PHASE_OFF program video
adjustment controls for hue, brightness, contrast, saturation, and sharpness.
3.2.7.1 Hue AdjustThere are two methods for adjusting the hue. Only one method should be enabled
at any time. While using one method, the registers of the other should be set to
their default values.
Method 1—adjusts the subcarrier phase within the active video region.
Register HUE_ADJUST (3B[7:0]) controls the subcarrier phase. This method
adjusts the hue in composite and S-Video signals for PAL and NTSC waveforms
according to the following equation:
HUE_ADJUST
=
()
phase offset
256
Method 2—uses the four registers MULT_UU, MULT_VU, MULT_UV, and
MULT_VV to matrix multiply the color vectors.
These registers are used to perform a 2x2 matrix multiplication on the U/V
path (or D
path for SECAM). Matrix multiplication transforms the incoming
R/DB
U/V stream into an outgoing U/V stream preceeding the color modulator. The
default values leave the U/V stream unmodified. The parameters are 8-bit twos
complement numbers.
The formulas implemented by these registers are as follows:
360
°⁄×
Uout = (MULT_UU/128) × Uin + (MULT_VU/128) × Vin
Vout = (MULT_UV/128) × Uin + (MULT_VV/128) × Vin
The value 0x7F is a special case which is rounded up internally to +128, or a
factor of 1.00 after the multiplier is divided by 128.
These registers can be loaded with sine and cosine values as follows to
perform a hue rotation on the chrominance values, except a value of +127 is made
128 internally.
To rotate the hue by an angle θ, program the matrix multipliers as follows:
θ
MULT_UU = 128 × cos (
–
MULT_VU =
128 × sin (θ)
MULT_UV = 128 × sin (
MULT_VV = 128 × cos (
)
θ
)
θ
)
Method 2 (matrix multiplication) cannot be used for hue rotation when the
P AL bit is enabled. However, hue rotation can be accomplished for PAL modes in
one of two ways. For component modes, method 2 hue rotation (matrix
multiplication) is effective if register bit PAL (16[3]) is set to 0. For composite
and S-Video modes, in which register bit PAL is enabled, method 1 hue rotation
(subcarrier phase adjust) is effective. Hue rotation cannot be implemented
simultaneously for component and composite PAL modes.
When in SECAM mode, this matrix multiplication occurs in D
R/DB
space,
and, as a result, the angle should be the negative of what one would expect if the
data was in the U/V space for PAL or NTSC.
3.2.7.2 Brightness
Adjust
Brightness adjust is controlled by register Y_OFF (37[7:0]). Y_OFF is a twos
compliment number, such that a value of 0x00 is 0 IRE offset, a value of 0x7F is
+22.14 IRE offset, and a value of 0x80 is –22.31 IRE offset. The luminance level
offset is referenced from black and can be adjusted from –22.31 IRE (below
black) to +22.14 IRE (above black). Active video is added to the offset level.
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Multiport YCrCb to NTSC/PAL /SECAM
3.2.7.3 Contrast AdjustRegister M_Y (22[7:0]) controls contrast adjustment. This modifies the
luminance multiplier, allowing a larger or smaller luminance range.
3.2.7.4 Saturation
Adjust
Registers M_CB (21[7:0]) and M_CR (20[7:0]) control saturation adjustments.
These registers are the chrominance component (Cb and Cr) multipliers. To
maintain the correct Cb/Cr relationship, these registers should be modified
synchronously.
3.2.7.5 Sharpness
Adjust
Register field PKFIL_SEL (1B[4:3]) and register bit FIL_SEL (3C[2]) control
sharpness filters. When FIL_SEL = 0, peaking filters of 0 dB, 1 dB, 2 dB and 3.5
dB gains are selected by register field PKFIL_SEL. When FIL_SEL = 1, four
reduction filters are selected by register field PKFIL_SEL. Figures 3-6 and 3-7
illustrates these filter options.
3.2 Effects
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3.0 Digital Processing and FunctionalityBt860/861
3.2 Effects
3.2.8 Macrovision Encoding (Bt861 Only)
The anticopy process contained within the Bt861 is implemented according to the
version 7.x. Specification, developed by Macrovision Corporation in Sunnyvale,
California. The Macrovision Anticopy process is available only in the Bt861.
Conexant cannot ship Bt861 encoders to any customer until Macrovision has
licensed that customer. Contact Macrovision Corporation to obtain this license
agreement. Parties who have obtained a Macrovision license may receive the
Bt861 Macrovision Supplement by contacting their local Conexant Sales office.
3.2.9 Outputs
Register field OUTMODE (17[5:3]) is used to select one of eight analog output
configurations, as listed in Table 3-9. All DACs are designed to drive standard
video levels into a combined R
minimize supply current, disable unused outputs by setting the corresponding
DIS_DAC_x register bit high.
Table 3-9. DAC Format Options
BitsDAC ADAC BDAC CDAC DDAC EDAC F
Multiport YCrCb to NTSC/PAL /SECAM
of 37.5 Ω (double-terminated 75 Ω) To
load
3.2.10 Luminance Delay
Register field YDELAY can be programmed with up to 7 clocks delay on any
DAC with a CVBS_DL Y label (see Table 3-9). The programable luminance delay
can be used to correct the high frequency chrominance delay caused by
postfiltering.
delayed as controlled by the YDELAY register field.
CVBS_DLY is the composite video signal with an optional luminance component
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Bt860/8613.0 Digital Processing and Functionality
Multiport YCrCb to NTSC/PAL /SECAM
3.2.11 Special SCART Signals
At power-up, the ALTADDR pin is sampled to determine the Bt860/861’s serial
programming address. At all other times the SCART_SEL (3C[1:0]) register field
determines its function. Setting the SCART_SEL register field to 00 will
three-state the AL TADDR pin; setting it to 01 produces a Vertical Blank signal on
the ALTADDR pin; setting it to 10 produces a Composite Sync signal on the
ALTADDR pin; and setting it to 11 produces a Composite Blank signal on the
ALTADDR pin. These signals are 3.3 V TTL signals that are aligned with the
outgoing video, as illustrated in Figure 3-15.
Figure 3-15. SCART Function on ALTADDR Pin
Composite
Video
ALTADDR Pin
(Vertical Blank)
ALTADDR Pin
(Composite Sync)
3.2 Effects
SCART _SEL [1:0]
01
10
ALTADDR Pin
(Composite Blank)
3.2.12 Output Connection Status
DAC connection status can be checked automatically or manually. When the
AUTO_CHECK (1B[2]) register bit is set to 1, the connection status of the DACs
is automatically checked once per frame. When the AUTO_CHECK register bit
is set to 0 (default), setting the CHECK_STAT register bit to 1 initiates a single
check of the DAC connection status. This bit is automatically cleared. The
connection status of the DAC is then represented on the MONSTAT_A through
MONSTAT_F register bits (01[7:2]). A 1 indicates that a properly terminated
load has been detected on that DAC. Because the Bt860/861 checks for a double
terminated load (combined 37.5
misrepresented. The DAC output must be enabled for proper sensing.
11
), improper termination causes the load to be
Ω
861_034a
D860DSAConexant3-23
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3.0 Digital Processing and FunctionalityBt860/861
3.2 Effects
3.2.13 Output Filtering and SINX/X Compensation
The DAC output response is a typical sinx/x response. For the composite video
output, this results in slightly lower than desired burst and chroma amplitude
values. To compensate for this, choose an output filter with high frequency
peaking or program the BST_AMP, M_CR, and M_CB registers higher by a
factor of (x/sinx). The amplitude of the affected signal is calculated by:
f
sc
------- -
sin
π
⋅
f
Amplitude
-----------------------------
=
clk
f
sc
------- -
π
⋅
f
clk
3.2.14 Low Power Features
The Bt860/Bt861 has several power saving features, including 3.3 V operation,
individual DAC disable, sleep mode, and PLL disable.
The Bt860/861 is a 3.3 V part with 5 V-tolerant digital inputs; 5 V tolerance is
obtained by setting the VDDMAX pin to 5 V. If 5 V tolerance is not required,
connect VDDMAX to VDD.
Setting the SLEEP (1B[0]) register bit to 1 puts the part into sleep mode, in
which all blocks are disabled except core serial programming functionality and
the PLL. If CLKIN is the internal clock source, power can be further reduced by
disabling the PLL and oscillator circuitry by setting the DIS_PLL (1D[4]) and
DIS_XTAL (1D[7]) register bit to 1. In sleep mode, only the SLEEP bit is active,
so the PLL must be powered down before sleep is induced if disabling the PLL is
desired. This mode achieves the greatest reduction in power.
All DACs can be disabled individually using the EN_DAC_x (18[5:0])
register bits. This method can be used when not all DACs are required
simultaneously.
Multiport YCrCb to NTSC/PAL /SECAM
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Bt860/8613.0 Digital Processing and Functionality
Multiport YCrCb to NTSC/PAL /SECAM
3.2.15 Teletext Operation of Bt860/861
Teletext encoding in the Bt860/861 is accomplished via a two-wire interface,
TTXDAT and TTXREQ, and several control registers, programmed via the serial
programming interface. The Bt860/861 Teletext output conforms to Teletext B
for 625-line systems; Teletext should be disabled for 525-line systems. For more
details on the Teletext standard, consult ITU-R BT.653 or EACEM Technical
Report No. 8.
The TTXDAT pin is the Teletext data insertion pin, and the TTXREQ pin is
the timing pin. The TTXREQ pin can be configured into two Teletext timing
modes by using register bit TXRM (59[1]). Figure 3-16 illustrates Teletext
timing.
Figure 3-16. Teletext Timing
Composite or
Luminance (Y)
Output
(2)
TTXDAT
3.2 Effects
(1)
t
1
12 3 4 56 7 8 9Bit
Clock Run-In
. . .
TTXREQ
(Timing Mode 1)
TTXREQ
(Timing Mode 2)
HSYNC*
NOTE(S):
(1)
t1 is the start of Teletext. The midpoint of the first Teletext pulse is 10.2 µs from the midpoint of the analog horizontal
sync pulse falling edge.
(2)
The Teletext data on the TTXDAT pin must observe proper set-up and hold times relative to the Teletext timing clock
falling edge (TTXREQ signal in timing mode 1).
(3)
Teletext data is latched on the Teletext timing clock’s falling edge.
(4)
The Teletext timing clock’s first rising edge (t2) occurs 335 system clocks after falling HSYNC* for ITU-R BT.601 timing.
(5)
Placement of the rising edge of the TTXREQ request signal (t3) in Teletext timing mode 2 is definable using register field
TXHS[10:0].
(6)
Placement of the falling edge of the TTXREQ request signal (t4) in Teletext timing mode 2 is definable using register field
(3)
(unchanged note)
(4)
t
2
12 3 4 56 7 8Bit
(5)
t
3
(6)
t
4
. . .
TXHE[10:0].
861_001
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3.0 Digital Processing and FunctionalityBt860/861
3.2 Effects
3.2.15.1 Teletext Timing
Mode 1
3.2.15.2 Teletext Timing
Mode 2
Multiport YCrCb to NTSC/PAL /SECAM
Setting register bit TXRM to 1 puts the Bt860/861 in Teletext timing mode 1. In
this mode, the TTXDAT pin is the Teletext data entry pin, and the TTXREQ pin is
configured as the Teletext timing clock. The T eletext clock timing is fixed
internally and has an average frequency of 6.9375 MHz. The T eletext timing clock
does not have a consistent period, because it is derived from the system clock,
which is not evenly divisible by 6.9375 MHz. The clock period varies from 3–4
system clocks for ITU-R BT.601 timing, and 4–5 system clocks for square pixel
timing. T eletext data is latched on the falling edge of this clock. The first rising
edge occurs 335 system clocks after falling HSYNC* for ITU-R BT.601
timing (27 MHz).
Setting register bit TXRM to 0 puts the Bt860/861 in Teletext timing mode 2. In
this mode, the TTXDAT pin is the Teletext data entry pin, and the TTXREQ pin
is configured as the Teletext data request line. In this mode, the same Teletext
timing clock as in mode 1 is fixed internally. The rising edge of the TTXREQ
signal means start transmitting data, and the falling edge means stop transmitting
data. The 11-bit register fields TTXHS[10:0] and TTXHE[10:0] control the
placement of the rising and falling edges. Each LSB represents a one system
clock count (27 MHz or 29.5 MHz) increment. When the system clock is 27
MHz, there is a 4 clock offset between the falling edge of HSYNC* and the rising
or falling edge of the TTXREQ request signal. For example, a value of 0x001 on
either register places the respective edge at 5 clocks from falling HSYNC*. The
register values of TTXHS and TTXHE cannot be zero, equal to, or greater than
the total number of system clocks per line.
The internal Teletext timing clock can be externally reproduced using a P:Q
ratio counter, such as the one conceptualized in Figure 3-17. Table 3-10 lists
appropriate values for ITU-R BT.601 and square pixel timing.
Figure 3-17. P:Q Ratio Counter Block Diagram
ADDER
A
SUM
P
B
CO
CLK
CLK
DQ
Table 3-10. P:Q Ratio Counter Values
CLKPixel RatePQ
ITU-R BT.601
Square Pixel
27 MHz13.5 MHz37144
29.5 MHz14.75 MHz111472
MODULO
Q
REGISTER
RSTN
ENABLE_TTX_CLK
TELETEXT CLOCK
861_004
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Bt860/8613.0 Digital Processing and Functionality
Multiport YCrCb to NTSC/PAL /SECAM
3.2.15.3 General
Teletext Operation
A logical 1 on the TTXDAT pin corresponds to an analog output value of 66% of
the black-to-white transition (approximately 462 mV above black), and a logical
0 corresponds to black.
The Bt860/861 does not automatically provide any Teletext data, such as the
clock run-in and framing code; the user must provide all data.
Setting register bit TXE to 1 enables Teletext encoding. Register field
TTXBF1[8:0] sets the start Teletext line for field 1, and register field
TTXEF1[8:0] sets the end Teletext line for field 1. Register field TTXBF2 sets
the start Teletext line for field 2, and register field TTXEF2[8:0] sets the end
Teletext line for field 2. These 9-bit registers can be set to any value from 0–311,
but setting the start line before line 7 is not recommended. The start line should be
less than or equal to the end line. If the start and end lines for a field are the same
value, Teletext is disabled for that field. Register bit SQUARE must be set to 0
for ITU-R BT.601 timing (27 MHz system clock), and 1 for square pixel timing
(29 MHz system clock).
The TTX_DIS register field allows the user to disable the T eletext function on
specific lines in the odd and even fields as listed in Table 3-11.
Wide Screen Signaling (WSS) is used in 625-line systems on line 23. WSS data is
14 bits long and is entered on register bits WSS[14:1]. Register bits
WSSDAT[20:15] are ignored. To enable WSS on field 1, line 23, set register bit
EWSSF1 to 1. Register bit EWSSF2 is ignored, because WSS cannot be enabled
on field 2. If the clock is at CCIR clock speeds (27 MHz), set register bit
SQUARE to 0; if the clock is at square pixel speeds (29.5 MHz), set register bit
SQUARE to 1. The clock run-in and start codes are automatically inserted onto
the signal, but CRC data is not.
D860DSAConexant3-27
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3.0 Digital Processing and FunctionalityBt860/861
3.2 Effects
Figure 3-18. WSS Waveform
0.5 V
0.0 V
Multiport YCrCb to NTSC/PAL /SECAM
Figure 3-18 illustrates a typical WSS signal, where WSSDAT[14:1] = 0x00.
Note that WSS uses bi-phase coding of its data bits. The amplitude of the WSS
pulses is 500 mV above black when high, and black when low. For further WSS
details, see specification ETS 300294 or ITU-R BT.1119.
Run-In
Start
Code
Bit 14Bit 1
14 Data Bits
3.2.17 Copy Generation Management System
Copy Generation Management System (CGMS) is used in 525-line systems on
lines 20 and 283 (a.k.a. line 20, field 2). The CGMS data is 20 bits long and is
entered on register bits WSSDAT[20:1].
•Set register bit EWSSF1 to 1 to enable CGMS on field 1, line 20.
•Set register bit EWSSF2 to 1 to enable CGMS on field 2, line 283.
•Set register bit SQUARE to 0 if the clock is at CCIR clock speeds
(27 MHz).
•Set register bit SQUARE to 1 if the clock is at square pixel speeds
(24.5454 MHz).
Although there is no clock run-in in CGMS, a reference pulse is provided
automatically.
861_002
3-28ConexantD860DSA
Page 59
Bt860/8613.0 Digital Processing and Functionality
Multiport YCrCb to NTSC/PAL /SECAM
CRC data is not calculated and must be provided by the user. Figure 3-19
illustrates a typical CGMS signal. Note that bit 1 is closest to the HSYNC pulse
and bit 20 is farthest. The amplitude of the CGMS pulses are 70 IRE when high,
and 0 IRE when low. For further CGMS details, see specifications
EIA-J CPR-1202, EIA-J CPR-1204, and IEC 61880.
Figure 3-19. CGMS Waveform
VIRE
1.0
0.786
0.286
100
70
0
3.2 Effects
Bit No.
Reference123.. .. ..20
0
–40
11.2 µs ± 0.3 µs
3.2.18 Closed Captioning and Extended Data Services
The Bt860/861 can produce Closed Captioning (CC) and Extended Data Services
(XDS) waveforms for NTSC and PAL on the lines specified by CC_SEL (49[3:0])
and XDS_SEL (49[7:4]), as listed in Table 3-12. Tw o bytes of CC data are entered
using registers CCB1 (42[7:0]) and CCB2(43[7:0]), and two bytes of XDS data are
entered using registers XDSB1 (40[7:0]) and XDSB2 (41[7:0]). The data registers
are double buffered to prevent accidental overwriting of the data. T o enable CC, set
register bit ECC (48[0]) high, and to enable XDS, set register bit EXDS (48[1])
high. T o prevent writing partial data sequences, data is not latched until the second
byte of the two-byte data sequence (CCB2 or XDSB2) is written. Therefore, data
must be written in the order Byte 1, then Byte 2.
Table 3-12. Closed Captioning and Extended Data Services Control Bits
The ECCGATE register bit must be 1 for normal operation. When this bit is
set to 1, current data is displayed for one frame, and then the NULL data
sequence is displayed until new data is written to the registers. If ECCGATE is set
to 0, old data is displayed until new data is written to the registers.
Register bits CC_STAT (01[0]) and XDS_STAT (01[1]) allow monitoring of
data latching and encoding. When CC data is latched into the Bt861 registers, the
CC_STAT register bit is set to 1; when the data is encoded, it is set to 0. When
XDS data is latched into the Bt861 registers, the XDS_STAT register bit is set
to 1; when the data is encoded, it is set to 0.
By default, the CC or XDS waveform is placed at an appropriate start point
and has a data frequency of 503.4965 kb/s, however, both the start point and
signal width can be modified using registers fields CCSTART and CC_ADD,
respectively. Figure 3-20 illustrates a typical CC or XDS waveform. The
waveform consists of a clock run-in, a start bit, and two bytes of data, which is
encoded LSB first. The Bt860/861 automatically creates the clock run-in and start
bit, but does not calculate the parity bits. CC and XDS use an NRZ waveform,
where a logical 0 is represented by a black, and a logical 1 is represented as 50
IRE. Pixel data is ignored during active CC and XDS lines, but the CC or XDS
waveforms will be overwritten by T eletext data when Teletext is active on the CC
or XDS line.
Figure 3-20. Closed Captioning or Extended Data Service Waveform (Null Sequence)
50 IRE
3.2.18.1 Closed
Captioning Pass-through
Clock
Run-in
MSB Byte 1
Byte 1Byte 2
2 Bytes of Data
Start
Bit
MSB Byte 2
861_014
There is no explicit means for accepting broadband vertical blanking interval
(VBI) content through the data port. However, by expanding the active video
region to include the CC line, the device can encode this data properly for output.
3-30ConexantD860DSA
Page 61
4
4.0 Applications
4.1 PC Board Considerations
The layout for the Bt860/861 should be optimized for the lowest noise possible
on the power and ground planes by providing good decoupling. The trace length
between groups of power and ground pins should be as short as possible to
minimize inductive ringing. A well-designed power distribution network is
critical for elimination of digital switching noise. The ground plane must provide
a low-impedance return path for the digital circuits. A PC board with a minimum
of four layers is recommended, with layers 1 (top) and 4 (bottom) for signals, and
layers 2 and 3 for ground and power, respectively.
4.1.1 Component Placement
Components should be placed as close as possible to the associated pin so traces
can be connected point-to-point. The optimum layout enables the Bt860/861 to be
located close to both the power supply connector and video output connectors.
4.1.2 Power and Ground Planes
Separate digital and analog power planes are recommended as illustrated in
Figure 4-1. The digital power plane should provide power to all digital logic on
the PC board, and the analog power plane should provide power to the VAA
power pins, protection diodes, and COMP decoupling. There should be at least an
1/8-inch gap between the digital and analog power planes, connected by a single
point through a ferrite bead. The ground plane should be a single unified plane
overlapping both analog and digital power planes. The path back to the power
supply should have the lowest impedance possible with only one possible return
path. This layout eliminates noise on the analog signals caused by cross-currents
from digital switching.
The bead separating the digital and analog power planes should be located
within three inches of the Bt860/861. The bead provides impedance to switching
currents and high frequency noise. Use a low-resistance (<0.5 Ω) bead, such as
Ferroxcube 5659065-3B, Fair-Rite 2723021447, or TDK BF45-4001.
D860DSAConexant4-1
Page 62
4.0 ApplicationsBt860/861
4.1 PC Board Considerations
Figure 4-1. Typical Connection Diagram
(1)
5 V
VDDMAX
VDD
VAA
COMP 1
COMP 2
VBIAS 1
VBIAS 2
VREF
GND
AGND
FSADJ 1
FSADJ 2
DACA
DACB
DACB
DACB
DACB
DACB
P
P
P
P
P
P
Digital Power Plane
Analog Power Plane
C5
C6
C2C3C4
RSET1RSET
Multiport YCrCb to NTSC/PAL /SECAM
L1
C7 – C9
2
R
LOADRLOADRLOADRLOADRLOADRLOAD
C15
LPF
LPF/RF MOD
LPF
LPF/RF MOD
LPF
LPF
C1
3.3 V (VCC)
C10 – C14
Ground
(Power Supply
Connector)
To Video
Connector
LPF
C18
C16C17
NOTE(S):
(1)
This pin must be connected to 5 V if 5 V tolerance is required. If only 3.3 V tolerance is required, this pin should be
connected to VAA.
(2)
Some modulators may require AC coupling capacitors (10 µF).
L2
22 pF
1.8 µH
270 pF
RF Modulator/CVBS Out
75
330 pF
82
Buffer
TRAP
P
Modulator
ZIN = 1 K
CVBS
RF
(2)
Audio
Output
VAA
P
DAC
GND
3. For a typical parts list, see Table 4-1 .
Schottky
Diode
To
Filter
Schottky
Diode
861_035
4-2ConexantD860DSA
Page 63
Bt860/8614.0 Applications
Multiport YCrCb to NTSC/PAL /SECAM
4.1.3 Device Decoupling
For optimum performance, all decoupling capacitors should be located as close as
possible to the device, and the shortest possible leads should be used to reduce the
lead inductance. Chip capacitors are recommended for minimum lead inductance.
Radial lead ceramic capacitors can be substituted for chip capacitors and are
better than axial lead capacitors for self-resonance. Values chosen have
self-resonance above the pixel clock frequency.
4.1.4 Power Supply Decoupling
The best power supply performance is obtained with 0.1 µF ceramic capacitors
decoupling each group of power pins to ground. Place the capacitors as close as
possible to the device power pins and ground pins and connect with short, wide
traces. Table 4-1 is a typical parts list.
The 47 µF capacitor illustrated in Figure 4-1 is for low-frequency power
supply ripple; the 0.1 µF capacitors are for high-frequency power supply noise
rejection.
A linear regulator is recommended to filter the analog power supply if the
power supply noise is excessive. This is especially important when using a
switching power supply.
The COMP1 and COMP2 pins should be decoupled to the closest VAA pin with a
0.1 µF ceramic capacitor. Greater low-frequency supply noise will require a
larger value. The COMP1 and COMP2 capacitors must be as close as possible to
the COMP1, COMP2, and VAA pins.
4.1.6 VREF Decoupling
A 1.0 µF ceramic capacitor should be used to decouple VREF to AGND.
R
load
RSET1,
RSET2
TRAPCeramic ResonatorMurata TPSx.xMJ
XTAL50 ppm, 14.31818 MHz
NOTE(S):
characteristics will not affect BT860/861 performance.
1% 75 Ω Metal Film Resister
1% 301 Ω Metal Film ResistorDale CRCW08053010FRT1
Fundamental Crystal
Vendor numbers are listed only as a guide. Substitution of devices with similar
DALECRCW080575ROFRT1
(where x.x = sound carrier
frequency in MHz)
HoorayH1431818-18
4.1.7 VBIAS Decoupling
A 0.1 µF ceramic capacitor should be used to decouple VBIAS1 and VBIAS2 to
AGND.
4-4ConexantD860DSA
Page 65
Bt860/8614.0 Applications
Multiport YCrCb to NTSC/PAL /SECAM
4.1.8 Digital Signal Interconnect
The digital inputs to the Bt860/861 should be isolated from the analog outputs
and other analog circuitry as much as possible and should not overlay the analog
power plane.
Most noise on the analog outputs is caused by excessive edge rates (less than
3 ns), overshoot, undershoot, and ringing on the digital inputs coupling into the
analog signals. Ringing can be reduced by damping the line with a series resistor
(30–300
Because feed-through noise is proportional to the digital edge rates,
lower-speed logic (3–5 ns edge rates) should be used whenever possible. Route
the digital signals at 90-degree angles to any analog signals.
Ω)
.
4.1.9 Analog Signal Interconnect
Locate the Bt860/861 as close as possible to the output connectors to minimize
noise pickup and reflections caused by impedance mismatch. The video output
signals should overlay the ground plane.
The analog outputs are susceptible to crosstalk from digital lines; digital traces
must not be routed under or adjacent to the analog output traces.
For maximum performance, the analog video output impedance, cable
impedance, and load impedance should be identical. The load resistor connection
between the video outputs and AGND should be as close as possible to the
Bt860/861 to minimize reflections. Turn off all unused analog outputs by setting
the applicable EN_DAC_x register bit to 0.
4.1 PC Board Considerations
4.1.10 ESD and Latchup Considerations
Correct ESD-sensitive handling procedures are required to prevent device
damage, which can produce symptoms ranging from catastrophic failure to erratic
device behavior with leaky inputs.
All logic inputs should be held low until power to the device has settled to the
specified tolerance. DAC power decoupling networks with large time constants
should be avoided; they could delay VAA and VDD power to the device. Ferrite
beads must be used only for analog power VAA decoupling. Inductors cause a
time constant delay that induces latchup, and should not be substituted for ferrite
beads.
Latchup can be prevented by ensuring that all power pins are at the same
potential, all GND pins are at the same potential, and that the VAA and VDD
supply voltages are applied before the signal pin voltages. The correct power-up
sequence ensures that any signal pin voltage will never exceed the power supply
voltage.
D860DSAConexant4-5
Page 66
4.0 ApplicationsBt860/861
4.1 PC Board Considerations
Multiport YCrCb to NTSC/PAL /SECAM
4-6ConexantD860DSA
Page 67
5.0 Serial Programming Interface and Registers
5.1 Serial Interface
The Bt860/861 uses a 2-wire serial programming interface to program the device
registers. The interface operates at 3.3 V or 5.0 V input levels. Figure 5-1
illustrates the timing relationship between Serial Interface Data (SID) and Serial
Interface Clock (SIC) lines. If the bus is not being used, both SID and SIC lines
must be pulled high.
Figure 5-1. Serial Programming Interface Timing Diagram
5
Subsequent Bytes and Acknowledge
Interpreted as Data Values for
Auto-Incrementing Subaddress Locations
SIC
123456789123456789123456789
SID
MSB
Start Condition
NOTE(S):
(1)
Acknowledge generated by Bt860/861.
Slave
Address
(1)
LSB
Subaddress
(1)(1)
Data
Stop Condition
861_024
D860DSAConexant5-1
Page 68
5.0 Serial Programming Interface and RegistersBt860/861
5.1 Serial Interface
5.1.1 Device Address
Multiport YCrCb to NTSC/PAL /SECAM
Every data word put onto the SID line must be 8 bits long (MSB first),
followed by an acknowledge bit, generated by the receiving device. Each data
transfer is initiated with a start condition and ended with a stop condition. The
first byte after a start condition is always the slave address byte. If this is the
device address, the device generates an acknowledge signal by pulling the SID
line low during the ninth clock pulse.
The eighth bit of the address byte is the read/write* bit (high = read from the
addressed device, low = write to the addressed device). Data bytes are always
acknowledged during the ninth clock pulse by the addressed device.
During the acknowledge period, the master device must leave the SID line
NOTE:
high.
Premature termination of the data transfer is allowed by generating a stop
condition at any time. When this happens, the Bt860/861 remains in the state
defined by the last complete data byte transmitted, and any master acknowledge
subsequent to reading the chip ID (subaddress 0x89) is ignored.
The device address is configurable by the state of the ALTADDR pin at reset. If
SCART functionality is not desired, the ALTADDR pin may be tied directly to
power or ground to configure this address. Otherwise, the address should be
configured through a soft-tie resistor to power or ground. Table 5-1 lists how the
ALTADDR pin configures the device address.
5.1.2 Writing Data
Table 5-1. Serial Address Configuration
ALTADDRDevice Address
07’b10001010x8A0x8B
17’b10001000x880x89
Device Address
Byte for Writes
Device Address
Byte for Reads
A write transaction involves sending the device address byte with the read/write*
bit low, and following it with one or more bytes. The first byte following the
device address byte is always assumed to be a register subaddress, and sets an
internal register subaddress pointer. This address is an 8-bit quantity, thus
allowing the addressing of up to 256 b yte-wide re gisters. If a second byte follows
the device address byte, it is assumed to be the write data for the register indexed
in the first byte. Any subsequent bytes are assumed to be write data for registers
whose address follows in ascending order, as the internal subaddress pointer is
incremented at the completion of each register write. The state of this internal
address pointer upon exiting a write transaction is used for any read transactions
that follow.
Figure 5-2 illustrates a typical register write sequence.
1. Master transmits the device address with the read/write* bit low.
2.
Master transmits the desired register subaddress.
3. Master transmits the register write data byte.
4. Subsequent registers are written until a stop condition is detected.
5-2ConexantD860DSA
Page 69
Bt860/8615.0 Serial Programming Interface and Registers
Multiport YCrCb to NTSC/PAL /SECAM
Figure 5-2. Serial Programming Interface Typical Write Sequence
Chip Write
SAA
Address
88 or 8A
Sub Address
S = Start Condition
P = Stop Condition
A = Acknowledge
5.1.3 Reading Data
A read transaction involves sending the device address byte with the read/write*
bit high, and receiving one or more bytes after changing the direction of the bus.
The first byte returned after the device address byte is the contents of the last
indexed register subaddress. Any subsequent data bytes read come from registers
whose address follows in ascending order as the internal subaddress pointer is
incremented at the completion of every read. The initial register subaddress
depends on the state of the pointer at the end of the last write transaction. Because
writing even one data byte to a register will increment the subaddress pointer,
typically one would want to precede a read with a write transaction that sends
only the register subaddress byte.
Figure 5-3 illustrates a typical register read sequence.
Data
5.1 Serial Interface
AAPData
Optional Sequential
Write May be Repeated
From Master
From Bt860/861
861_036
1.
Master transmits the device address with the read/write* bit low.
2. Master transmits the desired register subaddress.
3.
Master generates repeat start.
4.
Master transmits the device address with the read/write* bit high.
5. Slave (Bt860/861) transmits the data byte to master.
6. Subsequent registers are read until a stop condition is detected.
Figure 5-3. Serial Programming Interface Typical Read Sequence
Chip Write
SSr
Address
88 or 8A89 or 8B
AAASub AddressDataANA PData
Chip Read
Address
= Start Condition
S
= Stop Condition
P
= Acknowledge
A
= Repeat Start Condition
Sr
= Not Acknowledged
NA
Optional Sequential
Read May be Repeated
From Master
From Bt860/861
861_037
D860DSAConexant5-3
Page 70
5.0 Serial Programming Interface and RegistersBt860/861
5.2 Internal Registers
5.2 Internal Registers
Registers provide direct control and status of the part. These registers are
accessed by the serial programming interface described in this section. Table 5-2
provides a register bit map. Table 5-3 lists the alpha-sorted register index.
Section 5.4 gives bit descriptions and detailed programming information. All
registers are read/write unless otherwise indicated, and are set to default values
following a software, power, and pin reset. A software reset is always performed
at power-up, and when register bit SRESET (1B[7]) is set to 1.
Number of Lines per Frame
Analog Horizontal Sync Width
39[3:0]
39[7:4]
3A[3:0]
3A[7:4]
46[7:0]
44[7:0]
33[7:0]
35[7:0]
Alpha Blend Lookup T able Elements 0
Alpha Blend Lookup T able Elements 1
Alpha Blend Lookup T able Elements 2
Alpha Blend Lookup T able Elements 3
Alpha Select
Automatic Monitor Status Checking
BLANK* Polarity Control
Blend Select
BLANK Control
Blue Field
Multiplication Factor for the Colorburst Amplitude for NTSC/PAL
Bypass PLL
Closed Captioning Buffer Status
Closed Captioning or Extended Data Services DTO Increment
First Byte of Closed Captioning Information
Second Byte of Closed Captioning Information
Line Position of Closed Captioning Content
Closed Captioning or Extended Data Services Start Placement
Manual Monitor Status Checking
Chrominance Bandwidth
CLKO Disable
SECAM Cross Color Filter
Invert CVBS_DLY Outputs
Upper Boundary for Db Frequency Deviation in SECAM
Lower Boundary for Db Frequency Deviation in SECAM
Upper Boundary for Dr Frequency Deviation in SECAM
Lower Boundary for Dr Frequency Deviation in SECAM
Enable Active Video
Enable Internal Color Bars
Enable Closed Captioning
Closed Captioning Gating
Enable Clipping
Enable 656 Code Translation
Enable DAC A
Enable DAC B
Enable DAC C
Enable DAC D
Enable DAC E
Enable DAC F
Enable WSS or CGMS Function on Field 1
Enable CGMS Function on Field 2
Enable Extended Data Services
Field Number
Enable SECAM Bottleneck Pulses
FIELD Polarity Control
FIFO Overflow Status
FIFO Underflow Status
Filter Select
Field Tolerance
FM Modulation
Number of Active Pixels Per Line
Horizontal Blanking Length
Beginning of Burst
End of Burst
Number of System Clocks Per Line
HSYNC* Offset
HSYNC* Width
HSYNC* Polarity Control
Hue Adjustment by Subcarrier Shift
Part Identification
D860DSAConexant5-9
Page 76
5.0 Serial Programming Interface and RegistersBt860/861
MULT_UU
MUL T_UV
MULT_VU
MULT_VV
NI
OUTMODE[2:0]
OVRLAY_SEL
PAL
PCLK_EDGE
PCLK_SEL
PHASE_OFF[7:0]
PKFIL_SEL[1:0]
PLL_FRACT[18:0]
PLL_INT[4:0]
PLL_LOCK
PROG_SC
Default
(1)
Value
18071[0]
8072[7:0]
11C[6]
01C[5]
8921[7:0]
8023[7:0]
C120[7:0]
284BDA132D[7:0]
21F07C1F29[7:0]
9A22[7:0]
—01[2]
7F5C[7:0]
005D[7:0]
005E[7:0]
7F5F[7:0]
016[1]
01017[5:3]
01A[4]
016[3]
019[1]
119[7]
0038[7:0]
001B[4:3]
OAF8C15[7:5]
0F15[4:0]
102[2]
01A[1]
Multiport YCrCb to NTSC/PAL /SECAM
RegisterDescription
FIFO Window
70[7:0]
Max Adjustment
Locking Reset
Start VID Path Locking
Multiplication Factor for the Cb Component Prior to Modulation
Multiplication Factor for the Component at DAC D
24[7:0]
25[7:0]
Multiplication Factor for the Component at DAC F
Multiplication Factor for the Component at DAC E
Multiplication Factor for the Cr Component Prior to Modulation
Subcarrier Increment for Db for SECAM
2C[7:0]
2B[7:0]
2A[7:0]
Subcarrier Increment for NTSC/PAL or Dr for SECAM
28[7:0]
27[7:0]
26[7:0]
Luminance Multiplication Factor (contrast control)
DAC A Connection Status
01[3]
01[4]
01[5]
01[6]
01[7]
DAC B Connection Status
DAC C Connection Status
DAC D Connection Status
DAC E Connection Status
DAC F Connection Status
Chrominance Matrix Multiplier
Chrominance Matrix Multiplier
Chrominance Matrix Multiplier
Chrominance Matrix Multiplier
Non-Interlace Enable
DAC Output Format Control
Overlay Select
Phase Alternation
Pixel Clock Edge Sample Select
Pixel Clock (system clock) Select
Subcarrier Phase Offset (for SC – H Phase Adjustments)
Luminance Peaking Filter Gain Selection
Fractional Portion of the PLL Multiplier
14[7:0]
13[7:0]
Integer Portion of the PLL Multiplier
PLL Lock Status Bit
SECAM Subcarrier Control
5-10ConexantD860DSA
Page 77
Bt860/8615.0 Serial Programming Interface and Registers
Multiplication Factor for the SECAM Subcarrier Amplitude
SECAM Phase Sequence
Subcarrier Reset
SCART Selection Options
Setup
Master/Slave Control
Sleep
Square Pixel or CCIR Timing Select for Teletext and WSS
Software Reset
Sync Tip to Blank Amplitude
Sync Configuration
T eletext Disable by Line
Teletext Start Line for Field 1
Teletext Start Line for Field 2
Teletext End Line for Field 1
Teletext End Line for Field 2
TTXREQ Falling Edge
TTXREQ Rising Edge
Teletext Enable
TTXREQ Configuration
Number of Active Lines per Field
Vertical Blanking Length
Version Number for the Part
VIDCLK Edge Sample Select
Video Select
VIDFIELD Polarity Control
VIDHACT Polarity Control
VIDVACT Polarity Control
VIDVALID
Polarity
Control
VID Port Locking Status
Analog and Digital Vertical SYNC Duration
VSYNC* Polarity Control
D860DSAConexant5-11
Page 78
5.0 Serial Programming Interface and RegistersBt860/861
Default values in this table refer to hexadecimal values if the register field contains four or more bits; otherwise the value is
binary.
2. Internal timing and the values programmed into the registers reference the analog VSYNC pulse (O
Figures 3-1 and 3-2).
3. System clock = F
Default
(1)
Value
—4C[7:0]
—01[1]
8040[7:0]
8041[7:0]
449[7:4]
773[7:4]
11C[0]
013C[5:4]
273[3:0]
03C[3]
11C[7]
0037[7:0]
00018[7:6]
= 2x luminance sample frequency.
CLK
RegisterDescription
4B[7:0]
4A[3:0]
3C[6]
WSS and CGMS Data Bits
Extended Data Services Buffer Status
First Byte of Extended Data Services Information
Second Byte of Extended Data Services Information
Line Position of Extended Data Services Content
VID Port Locking Status
High if VID port input frequency exceeds tracking range, as programmed by LC_MAXOFF.
PLL Lock Status Bit
0 = Unable to lock to desired PLL frequency.
1 = PLL is able to lock to desired frequency.
FIFO Underflow Status
High if VID port FIFO underflows. Resets to zero on write.
FIFO Overflow Status
High if VID port FIFO overflows. Resets to zero on write.
Register 04–05
Register
Reserved bits should be set to zero when written and will return zero when read.
HCLK[11:0]
Default
Value
04B4HCLK[7:0]
0506ReservedHCLK[11:8]
D7D6D5D4D3D2D1D0
Number of System Clocks Per Line
Register 06–07
Register
Reserved bits should be set to zero when written and will return zero when read.
HACTIVE[9:0]
Default
Value
06C8HACTIVE[7:0]
0702
Number of Active Pixels Per Line
D7D6D5D4D3D2D1D0
Reserved
HACTIVE[9:8]
5-14ConexantD860DSA
Page 81
Bt860/8615.0 Serial Programming Interface and Registers
Multiport YCrCb to NTSC/PAL /SECAM
Register 08
Register
AHSYNC_WIDTH[7:0]
Default
Value
087EAHSYNC_WIDTH[7:0]
D7D6D5D4D3D2D1D0
Analog Horizontal Sync Width
Measured in system clock cycles, from 50% points of sync pulse.
Register 09
Register
HBURST_BEG[7:0]
Default
Value
0990HBURST_BEG[7:0]
D7D6D5D4D3D2D1D0
Beginning of Burst
50% point of burst from the 50% point of the analog horizontal sync falling edge,
measured in system clock cycles.
5.4 Register Detail
Register 0A
Register
HBURST_END[7:0]
Default
Value
0A54HBURST_END[7:0]
D7D6D5D4D3D2D1D0
End of Burst
50% point of burst from the 50% point of the analog horizontal sync falling edge,
measured in system clock cycles – 128.
D860DSAConexant5-15
Page 82
5.0 Serial Programming Interface and RegistersBt860/861
5.4 Register Detail
Multiport YCrCb to NTSC/PAL /SECAM
Register 0B–0C
Register
Reserved bits should be set to zero when written and will return zero when read.
HBLANK[9:0]
Default
Value
0B0CHBLANK[7:0]
0C01ReservedHBLANK[9:8]
D7D6D5D4D3D2D1D0
Horizontal Blanking Length
Determines the number of system clocks between 50% point of the leading edge of the
analog horizontal sync, as well as the relationship between the leading edge of the pulse on
the HSYNC* pin and active video. If HBLANK is even, the relationship between the register
and horizontal blanking in the encoded waveform is:
HBLANK = (desired horizontal blanking in system clocks) + 14
If HBLANK is odd, the relationship is:
HBLANK = (desired horizontal blanking in system clocks) + 15
Because, in either case you will get an even horizontal blanking in the encoded video
waveform, the only reason for having an odd HBLANK value is to align the active video
window with the encoding data stream. The relationship between HBLANK and the position
of active video on the P, OSD, and ALPHA pins is:
HBLANK = [(HSYNC* pin to active video) + 2 + HSYNC_OFF]
HBLANK = [(HSYNC* pin to active video) + 3]
slave mode BLK_IGNORE bit = 1
master mode
Register 0D
Register
VBLANK[7:0]
Default
Value
0D13VBLANK[7:0]
D7D6D5D4D3D2D1D0
Vertical Blanking Length
Line number of first active line (number of blank lines + 1),
measured from (0
) vertical sync
V
(1)
.
Register 0E–0F
Register
Reserved bits should be set to zero when written and will return zero when read.
VACTIVE[8:0]
Default
Value
0EF1VACTIVE[7:0]
0F00ReservedVACTIVE[8]
D7D6D5D4D3D2D1D0
Number of Active Lines per Field
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Bt860/8615.0 Serial Programming Interface and Registers
Multiport YCrCb to NTSC/PAL /SECAM
5.4 Register Detail
Register 10–11
Register
Reserved bits should be set to zero when written and will return zero when read.
HSYNC_OFF[9:0]
Default
Value
1000HSYNC_OFF[7:0]
1100ReservedHSYNC_OFF[9:8]
D7D6D5D4D3D2D1D0
HSYNC* Offset
Defines the offset in system clocks of HSYNC* pulse relative to the internal horizontal
sync in master mode.
This value is twos complement so that:
Pixel Clock (system clock) Select
State of FIELD pin during power-up determines the default value of PCLK_SEL. FIELD = 1
corresponds to PCLK_SEL = 0 as default, while FIELD = 0 corresponds to PCLK_SEL = 1 as
default. If FIELD is not externally loaded, an internal pull-down sets FIELD = 0 at power-up.
0 = Use CLKIN as pixel clock source.
1 = Use PLL as pixel source (derived from XTI and XTO inputs).
VSYNC* Polarity Control
0 = Active low VSYNC* pin.
1 = Active high VSYNC* pin.
HSYNC* Polarity Control
0 = Active low HSYNC* pin.
1 = Active high HSYNC* pin.
FIELD Polarity Control
0 = A 1 on FIELD pin indicates an even field.
1 = A 1 on FIELD pin indicates an odd field.
BLANKI
BLK_IGNORE
PCLK_EDGE
FLDMODE
BLANK* Polarity Control
0 = Active low BLANK* pin.
1 = Active high BLANK* pin.
Blank Control
0 = Use BLANK* pin to indicate the active pixel region in slave mode.
1 = Use HBLANK, HACTIVE, VACTIVE, and VBLANK registers to determine the active pixel
region in slave mode.
Pixel Clock Edge Sample Select
0 = P, OSD, ALPHA, HSYNC*, VSYNC*, BLANK* data sampled at the rising edge of the system clock.
1 = P, OSD, ALPHA, HSYNC*, VSYNC*, BLANK* data sampled at the falling edge of the system clock.
Field Tolerance
0 = A falling edge of VSYNC* that occurs within ±¼ of a scan line from the falling edge of
HSYNC* indicates the beginning of odd field. A falling edge of VSYNC* that occurs
within ± 1/4 scan line from the center of the line indicates the beginning of even field.
1 = A falling edge of VSYNC* that occurs during HSYNC* high indicates the beginning of
odd field. A falling edge of VSYNC* that occurs during HSYNC* low indicates the
beginning of even field.
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5.0 Serial Programming Interface and RegistersBt860/861
Blend Select
0 = Alpha control contained in Y[1:0] of port selected by OVRLAY_SEL.
1 = Alpha control contained in ALPHA[1:0] pins as described by ALPHAMODE [1:0] bits.
See Table 2-1.
Alpha Select (effective only when BLENDMODE = 1)
00 = Disable Alpha blending.
01 = Use ALPHA[0] as 1-bit alpha blend value with look-up table value.
10 = Use ALPHA[1:0] as 2-bit alpha blend value with look-up table value.
11 = Use ALPHA[1:0] over two load clocks to form a 4-bit alpha blend value.
See Table 2-1 and Figure 2-2.
Overlay Select
0 = Select P[7:0] as overlay blend stream.
1 = Select OSD[7:0] as overlay blend stream.
See Table 2-1.
VIDEO_SEL
EN_656
PROG_SC
SC_PATTERN
Video Select
0 = Select P[7:0] as video blend stream.
1 = Select VID[7:0] as video blend stream.
See Table 2-1.
Enable 656 Code Translation
0 = Use HSYNC*, VSYNC*, and BLANK* for video timing information.
1 = Use embedded SAV/EAV codes as defined by ITU-R BT.656 specification from port
P[7:0] as timing source.
See Table 2-2.
SECAM Subcarrier Control
0 = SECAM subcarrier is generated on lines 23
1 = SECAM subcarrier is generated on the active lines defined by VBLANK and VACTIVE.
1 = Enable Accelerated Locking Vertical Realignment Initiation.
When accelerated VID path locking is enabled, a vertical realignment larger than 18 lines will initiate an
accelerated locking adjustment.
Locking Reset
0 = Normal locking operation.
1 = Reset locking logic.
Start VID Path Locking
0 = Disable VID path locking operation.
1 = Normal VID path locking operation.
VIDVACT Polarity Control
0 = Active high VIDVACT pin.
1 = Active low VIDVACT pin.
VIDHACTI
VIDFIELDI
VIDVALIDI
XL_LOCK
VIDHACT Polarity Control
0 = Active high VIDHACT pin.
1 = Active low VIDHACT pin.
VIDFIELD Polarity Control
0 = A 1 on VIDFIELD pin indicates an even field.
1 = A 1 on VIDFIELD pin indicates an odd field.
VIDVALID Polarity Control
0 = Active high VIDVALID pin.
1 = Active low VIDVALID pin.
Accelerated Locking
0 = Accelerated VID path locking off.
1 = Accelerated VID path locking mode.
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Bt860/8615.0 Serial Programming Interface and Registers
0 = Normal operation.
1 = Power down crystal oscillator circuitry.
Disable Automatic Subcarrier Adjust
0 = Normal operation.
1 = Disable automatic subcarrier adjustment during locking.
Sync Configuration
0 = VSYNC* and HSYNC* pins are configured as inputs.
1 = SLAVE and EN_656 registers determine the configuration of VSYNC* and HSYNC* pins.
See Table 2-2.
Sleep PLL
0 = Enable PLL.
1 = Disable PLL.
For lower power consumption, disable PLL when not in use.
BY_PLL
CLKO_DIS
EACTIVE
CROSSFILT
Register 1E
Register
SYNC_AMP[7:0]
Default
Value
1EE5
Bypass PLL
1 = Bypass PLL.
0 = Channel XTAL clock through PLL.
CLKO Disable
0 = Enable CLKO pin.
1 = Disable CLKO pin.
Enable Active Video
0 = Black burst video output.
1 = Enable normal video output.
SECAM Cross Color Filter
0 = Apply SECAM luma cross color reduction filter.
1 = Bypass the filter (turn this off when using NTSC/PAL).
D7D6D5D4D3D2D1D0
SYNC_AMP[7:0]
Sync Tip to Blank Amplitude
Measured in LSB increments.
1 LSB = 1.25 V
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5.0 Serial Programming Interface and RegistersBt860/861
5.4 Register Detail
Register 1F
Register
BURST_AMP[7:0]
Default
Value
1F75BURST_AMP[7:0]
D7D6D5D4D3D2D1D0
Multiplication Factor for the Colorburst Amplitude for NTSC/PAL
This register is ignored when using SECAM.
BURST_AMP = int {BURST
BURST_AMP = int [0.707 × BURST
BURST
SincX = Sin[(
= peak to peak burst amplitude in volts
P–P
π
× F
/ F
SC
CLK
× 2
P–P
) / (π × F
10
/ [(2 × 1.28 SincX + 0.5)]} if PAL = 0
10
× 2
P–P
/ (2 × 1.28 SincX + 0.5)] if PAL = 1
/ F
)]
SC
CLK
Register 20
Register
M_CR[7:0]
Default
Value
20C1M_CR[7:0]
D7D6D5D4D3D2D1D0
Multiplication Factor for the Cr Component Prior to Modulation
This register is used for colorspace conversion and saturation adjustment.
V = (Cr – 128) × M_CR / 256
Multiport YCrCb to NTSC/PAL /SECAM
Register 21
Register
M_CB[7:0]
Default
Value
2189M_CB[7:0]
D7D6D5D4D3D2D1D0
Multiplication Factor for the Cb Component Prior to Modulation
This register is used for colorspace conversion and saturation adjustment.
U = (Cb – 128) × M_CB / 256
Register 22
Register
M_Y[7:0]
Default
Value
229AM_Y[7:0]
D7D6D5D4D3D2D1D0
Luminance Multiplication Factor (contrast control)
M_Y ranges from 0–1.56, such that
M_Y[7:0] = 255 × multiplication factor
1.56
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Bt860/8615.0 Serial Programming Interface and Registers
Multiport YCrCb to NTSC/PAL /SECAM
Register 23–25
Register
M_COMP_D[7:0]
M_COMP_F[7:0]
M_COMP_E[7:0]
Default
Value
2380M_COMP_D[7:0]
2480M_COMP_F[7:0]
2580M_COMP_E[7:0]
D7D6D5D4D3D2D1D0
Multiplication Factor for the Component at DAC D
Multiplication Factor for the Component at DAC F
Multiplication Factor for the Component at DAC E
M_COMP_x = gain, where 0 < gain < 1.99
128
DAC output values are truncated to 1023.
Register 26–29
Register
Default
Value
D7D6D5D4D3D2D1D0
5.4 Register Detail
261FM_SC_DR[7:0]
277CM_SC_DR[15:8]
28F0M_SC_DR[23:16]
2921M_SC_DR[31:24]
M_SC_DR[31:0]
Subcarrier Increment for NTSC/PAL or Dr for SECAM
M_SC_DR[31:0] = int ((FSC / F
where:
FSC = the subcarrier frequency, F
Use relationship between HCLK and the subcarrier frequency as given in ITU-R BT.470.
See Section 3.1.5.
) × 232 + 0.5)
CLK
= system clock (luminance sample frequency)
CLK
Register 2A–2D
Register
Default
Value
2A13M_SC_DB[7:0]
2BDAM_SC_DB[15:8]
2C4BM_SC_DB[23:16]
D7D6D5D4D3D2D1D0
2D28M_SC_DB[31:24]
M_SC_DB[31:0]
Subcarrier Increment for Db for SECAM
M_SC_DB[31:0] = int ((FSC / F
where:
FSC = subcarrier frequency, F
) × 232 + 0.5)
CLK
CLK
= system clock (luminance sample frequency)
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5.0 Serial Programming Interface and RegistersBt860/861
5.4 Register Detail
Register 2E
Register
SC_AMP[7:0]
Default
Value
2E85SC_AMP[7:0]
D7D6D5D4D3D2D1D0
Multiplication Factor for the SECAM Subcarrier Amplitude
Measured in LSB increments.
SC_AMP = (Amp
where Amp
P–P
SincX = Sin[(
× (1023 / 1.28 × SincX)
)
P–P
is the peak to peak amplitude of the subcarrier.
π
× FSC / F
) / (π × FSC / F
CLK
CLK
Register 2F–30
Register
Default
Value
2FA3DR_MAX[7:0]
3005
D7D6D5D4D3D2D1D0
Reserved
Multiport YCrCb to NTSC/PAL /SECAM
)]
DR_MAX[10:8]
Reserved bits should be set to zero when written and will return zero when read.
DR_MAX[10:0]
Upper Boundary for Dr Frequency Deviation in SECAM
DR_MAX = (F
MAX
/ F
CLK
) × 2
13
Register 31–32
Register
Reserved bits should be set to zero when written and will return zero when read.
DR_MIN[10:0]
Default
Value
319FDR_MIN[7:0]
3204
D7D6D5D4D3D2D1D0
Reserved
Lower Boundary for Dr Frequency Deviation in SECAM
DR_MIN = (F
MIN
/ F
CLK
) × 213
DR_MIN[10:8]
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Bt860/8615.0 Serial Programming Interface and Registers
Multiport YCrCb to NTSC/PAL /SECAM
Register 33–34
Register
Reserved bits should be set to zero when written and will return zero when read.
DB_MAX[10:0]
Default
Value
33A3DB_MAX[7:0]
3405
D7D6D5D4D3D2D1D0
Reserved
Upper Boundary for Db Frequency Deviation in SECAM
DB_MAX = (FMAX / F
CLK
) × 2
13
DB_MAX[10:8]
Register 35–36
Register
Default
Value
359FDB_MIN[7:0]
3604ReservedDB_MIN[10:8]
D7D6D5D4D3D2D1D0
5.4 Register Detail
Reserved bits should be set to zero when written and will return zero when read.
DB_MIN[10:0]
Lower Boundary for Db Frequency Deviation in SECAM
DB_MIN = (FMIN / F
CLK
) × 2
13
Register 37
Register
Y_OFF[7:0]
Default
Value
3700Y_OFF[7:0]
D7D6D5D4D3D2D1D0
Luminance Level Offset (brightness control)
The luminance level offset is referenced from black, and can be adjusted from –22.31 IRE
(below black) to +22.14 IRE (above black). Active video will be added to the offset level.
Y_OFF is a twos complement number, such that 0x00 = 0 IRE offset, 0x0F is +22.14 IRE
offset, and 0x10 is –22.31 IRE offset.
Register 38
Register
Default
Value
D7D6D5D4D3D2D1D0
3800PHASE_OFF[7:0]
PHASE_OFF[7:0]
Subcarrier Phase Offset (for SC – H Phase Adjustments)
PHASE_OFF = 256 × phase offset
°
360
Phase offset ranges from 0° – 358.6°.
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5.0 Serial Programming Interface and RegistersBt860/861
5.4 Register Detail
Multiport YCrCb to NTSC/PAL /SECAM
Register 39–3A
Register
ALPHA_LUT_0[3:0]
ALPHA_LUT_1[3:0]
ALPHA_LUT_2[3:0]
ALPHA_LUT_3[3:0]
Default
Value
3950ALPHA_LUT_1[3:0]ALPHA_LUT_0[3:0]
3AFAALPHA_LUT_3[3:0]ALPHA_LUT_2[3:0]
D7D6D5D4D3D2D1D0
Alpha Blend Lookup Table Element 0
Alpha Blend Lookup Table Element 1
Alpha Blend Lookup Table Element 2
Alpha Blend Lookup Table Element 3
Alpha blend multiplier look-up table when using content-based blending.
(BLEND MODE = 0) and when using pin-based blending in either 1-bit or 2-bit modes
(BLEND MODE = 1 and ALPHAMODE = 01 or 10). If 1-bit pin-based alpha is used, a 0 on
ALPHA[0] applies. ALPHA_LUT_0 and a 1 applies ALPHA_LUT_3.
Register 3B
Register
HUE_ADJUST[7:0]
Default
Value
3B00HUE_ADJUST[7:0]
D7D6D5D4D3D2D1D0
Hue Adjustment by Subcarrier Shift
HUE_ADJUST = 256 × (Phase)
360°
The hue adjustment ranges from 0° to 358.6°
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Bt860/8615.0 Serial Programming Interface and Registers
01 = ALTDDR pin is VBLANK signal.
10 = ALTDDR pin is composite sync signal.
11 = ALTDDR pin is composite blank signal.
These signals are synchronized with the DAC outputs. See Figure 3-15.
Register 40–41
Register
XDSB1[7:0]
Default
Value
4080XDSB1[7:0]
4180XDSB2[7:0]
D7D6D5D4D3D2D1D0
First Byte of Extended Data Services Information
Data is encoded LSB first.
XDSB2[7:0]
Second Byte of Extended Data Services Information
Data is encoded LSB first.
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5.0 Serial Programming Interface and RegistersBt860/861
5.4 Register Detail
Register 42–43
Register
CCB1[7:0]
CCB2[7:0]
Default
Value
4280CCB1[7:0]
4380CCB2[7:0]
D7D6D5D4D3D2D1D0
First Byte of Closed
Data is encoded LSB first.
Second Byte of Closed
Data is encoded LSB first.
Captioning
Captioning
Information
Information
Register 44–45
Register
Default
Value
444ACCSTART[7:0]
D7D6D5D4D3D2D1D0
Multiport YCrCb to NTSC/PAL /SECAM
4501
Reserved
Reserved bits should be set to zero when written and will return zero when read.
CCSTART[8:0]
Closed Captioning or Extended Data Services Start Placement
Number of clocks from leading edge of HSYNC* to start of Closed Captioning or Extended Data
Services clock run-in.
Default value is correct for 27 MHz operation.
Register 46–47
Register
Reserved bits should be set to zero when written and will return zero when read.
CCADD[11:0]
Default
Value
468CCCADD[7:0]
4709
D7D6D5D4D3D2D1D0
Reserved
Closed Captioning or Extended Data Services DTO Increment
Defines the width of Closed Captioning or Extended Data Services waveform.
Default value is correct for 27 MHz operation.
CCSTART[8]
CCADD[11:8]
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Bt860/8615.0 Serial Programming Interface and Registers
Multiport YCrCb to NTSC/PAL /SECAM
Register 48
Register
Reserved bits should be set to zero when written and will return zero when read.
ECCGATE
EXDS
ECC
Default
Value
4800
D7D6D5D4D3D2D1D0
Reserved
Closed Captioning Gating
0 = After current CC/XDS data is encoded, send Null data sequence until new data is written to registers.
1 = Repeat current CC/XDS data until new data is written to the registers.
Enable Extended Data Services
0 = Disable Extended Data Services encoding.