Datasheet CN8223, BT8222EPFF, BT8222EPFE Datasheet (CONEX)

Page 1

CN8223

ATM Transmitter/Receiver with UTOPIA Interface

The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network (UNI) and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI Specification 94/0317; Bellcore Specifications TR-TSV-000772, TR-TSV-000773, TR-NWT-000253, and T1S1/92-185; ITU Recommendations I.432, G.707, G.751, G.832, and Q.921; and ETSI prETS 300 213 and 300 214. Both Customer Premise Equipment (CPE) and switching system interface functions are provided. The CN8223 provides DS1, E1, DS3, E3, E4, STS-1, and STS-3c (and STM-1) ATM cell alignment functions. The system interface is via a parallel FIFO port or UTOPIA interface. In addition, the CN8223 terminates the operations and maintenance flows F1, F2, and F3.

The CN8223 provides four FIFO port interfaces and one UTOPIA interface. Each receiver port can be programmed with a particular Virtual Channel Identifier/Virtual Path Identifier (VCI/VPI) address for message routing. VCI/VPI pages can also be selected via masking registers.

The microprocessor can set control registers for insertion of selected header fields by the transmitter on an individual port basis. The microprocessor can also control insertion of all overhead and can insert errors in selected fields for test equipment applications.

Functional Block Diagram

Data

Bus

Port

Control

UTOPIA

or FIFO

Interface

Microprocessor

Address

Cell

FIFO

4-Port

FIFO

Interface

Cell

Generation

Header

Filter

ATM Layer Physical Framing

52 Control Registers

28 Status Registors

Rate

Control

Cell

Validation

Microprocessor

Interface

Data Line Overhead

Cell

Alignment

HEC or

PLCP

HDLC

Data

Link

Framers

DS3 E3 (G.751) E3 (G.832)

STS-1

E4 (G.832)

STS-3c

STM-1

TAXI

ATM UNI

Distinguishing Features

• Integrates 7 line framers with ATM layer processing according to ATM Forum UNI and NNI Specifications

• UTOPIA Level 1 interface

• Internal framers for DS3, E3 (G.751, G.832), E4 (G.832), STS-1, STS-3c, STM-1

• PLCP and G.804 HEC cell alignment for all data rates from 1.544 Mbps to 155 Mbps

• Direct interface to TAXI

or external

T1/E1 framers

• ATM and SMDS cell modes

• 4 FIFO ports with header screening, formatting, and transmit priority controls

• Idle cells generated and screened

• Statistics counts latched on one-second intervals

• Error detection and insertion

• Option insertion or generation of all line and cell overhead

• Serial or parallel line interface

• Available evaluation module reference design and software

• Supports Automatic Protection Switching (APS)

Applications

• WAN equipment

• ATM switches

• Test equipment

• ATM routers and hub

8223_042

Data Sheet 100046C

March 8, 2000

Page 2

Ordering Information

Part Number

Generic Part

Number

28222-13 Bt8222EPFE

28222-14 Bt8222EPFF

28233-11 CN8223EPF

Operating

Temperature

–40

°C to 85 °C

–40

°C to 85 °C

Package

Description

Reduced Features

160-pin PQFP —

160-pin PQFP The CN8223 is based on the Bt8222

device. The only change from the Bt8222 to the CN8223 is the TTL I/O pad ring. The I/O structure allows the CN8223 to function in a

3.3/5 V environment. No new features, errata fixes, etc., have been added to the CN8223 other than TTL threshold inputs.

Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Conexant’s Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever.

THESE MATERIALS ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTIAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.

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The following are trademarks of Conexant Systems, Inc.: Conexant™, the Conexant C™ symbol, and “What’s Next in Communications Technologies”™. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners.

For additional disclaimer information, please consult Conexant’s disclaimer information posted at incorporated by reference.

Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to conexant.tech.pubs@conexant.com. For technical questions, contact your local Conexant applications engineer.

www.conexant.com which is

sales office or field

100046C Conexant

Page 3

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 CN8223 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2.1 Internal Framers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2.2 UTOPIA Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2.3 Programmable Parity Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2.4 Test and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2.5 Microprocessor Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3 Line Framing Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.1 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.2 Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.3 BIP-8 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.3.4 Alarm Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.4 ATM Cell Processing Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.4.1 Cell Generation Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.4.2 Tx Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.4.3 Cell Validation Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.5 FIFO Port/UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.5.1 UTOPIA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.5.2 FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.5.3 ATM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.6 Line Interface Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.7 CN8223 Versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.8 CN8223 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

1.8.1 CN8223 as a DS3 or E3 G.751 Framer without ATM Cell Delineation. . . . . . . . . . . . . . . . 1-16

1.9 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.10 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

10046C Conexant iii

Page 4

Table of Contents CN8223

ATM Transmitter/Receiver with UTOPIA Interface

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.1 8/16-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.2 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Line Framers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2.1 Internally Framed Transmit Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.1.1 High-Speed PECL Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.2.2 Internally Framed Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2.2.1 High-Speed PECL Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.2.2 Receiver Framing Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.3 Externally Framed Transmit Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.4 Externally Framed Receive Line Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.3 Overhead Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.3.1 Internal DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.3.2 Internal G.832 E3/E4 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.3.3 Internal G.751 E3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.3.4 STS-1 and STS-3c/STM-1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.3.5 Transmit Framing Overhead Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.3.6 Receive Framing Overhead Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.4 Status and Alarms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.1 Status and Counter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.2 Alarm Signal Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.4.3 Alarm Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5 Parallel Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.1 TAXI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.2 Transmit Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.5.3 Receive Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.6 ATM Cell Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.6.1 Cell Generation for Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.6.1.1 CELL_GEN_x Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.6.1.2 Cell Generation Status and Status Interrupts for Transmit . . . . . . . . . . . . . . . 2-28

2.6.2 Cell Validation for Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

2.6.2.1 HEC Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2.6.2.2 CELL_VAL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2.6.2.3 Interrupts and Status Counters for Cell Validation. . . . . . . . . . . . . . . . . . . . . 2-32

2.6.3 PLCP Cell Generation for Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

2.6.4 PLCP Cell Validation for Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

2.6.4.1 PLCP Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

2.6.5 PLCP Transmit/Receive Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

iv Conexant 100046C

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CN8223 Table of Contents

ATM Transmitter/Receiver with UTOPIA Interface

2.7 FIFO Port/UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

2.7.1 FIFO Interface Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

2.7.2 Transmit Port Priority Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

2.7.3 Transmit Rate Shaping Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

2.7.4 Receive Port Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

2.7.4.1 Header Screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

2.7.4.2 Output Screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

2.7.5 UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

2.8 FEAC Channel and HDLC Data Link Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

2.8.1 FEAC Channel Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

2.8.2 FEAC Channel Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45

2.8.3 HDLC Data Link Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45

2.8.3.1 Sending a Message. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46

2.8.3.2 Aborting a Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47

2.8.3.3 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47

2.8.3.4 Transmitter Control Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48

2.8.4 HDLC Data Link Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48

2.8.4.1 Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

2.8.4.2 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

2.8.5 Receiver Response Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Registers Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Control Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.3 Configuration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

0x00—CONFIG_1 (Configuration Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

0x01—CONFIG_2 (Configuration Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

0x02—CONFIG_3 (Configuration Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

0x29—CONFIG_4 (Configuration Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

0x31—CONFIG_5 (Configuration Control Register 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

0x2B—UTOPIA_1 (Utopia Port Control Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

0x2C—UTOPIA_2 (Utopia Port Control Register 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.4 Transmit Control Registers

0x03—TXFEAC_ERRPAT (Transmit FEAC/Error Pattern Register) . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

0x60—DL_CTRL_STAT (HDLC Data Link Control and Status Register) . . . . . . . . . . . . . . . . . . . . . 3-15

0x04–0x07—CELL_GEN_x (Cell Generation Control Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

0x08—TX_RATE_23 (Transmit Rate Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

0x09—TX_RATE_01 (Transmit Rate Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

0x0A—TX_IDLE_12 (Transmit Idle Header Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

0x0B—TX_IDLE_34 (Transmit Idle Header Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

0x2A—IDLE_PAY (Transmit Idle Cell Payload Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

0x0C–0x13—TX_HDRx_12, TX_HDRx_34 (Transmit Header Registers) . . . . . . . . . . . . . . . . . . . . 3-18

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

100046C Conexant v

Page 6

Table of Contents CN8223

ATM Transmitter/Receiver with UTOPIA Interface

3.5 Receive Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

0x14—CELL_VAL (Cell Validation Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

0x15–0x1C—HDR_VALx_12, HDR_VALx_34 (Receive Header Value Register) . . . . . . . . . . . . . . . 3-21

0x1D–0x24—HDR_MSKx_12, HDR_MSKx_34 (Receive Header Mask Register) . . . . . . . . . . . . . . 3-22

0x25, 0x26—RX_IDLE_12, RX_IDLE_34 (Receive Idle Header Registers) . . . . . . . . . . . . . . . . . . . 3-23

0x27, 0x28—IDLE_MSK_12, IDLE_MSK_34 (Receive Idle Header Mask Register) . . . . . . . . . . . . 3-23

3.6 Interrupt Enable Control Registers

0x2D—EN_LINE_INT (Enable Line Interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

0x2E—EN_EVENT_INT (Enable Event Interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

0x2F—EN_OVFL_INT (Enable Overflow Interrupts). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

0x30—EN_CELL_INT (Enable Cell Interrupts). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

0x32—TX_K1K2 (Transmit K1 and K2 Value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

0x33—RX_K1K2 (Receive K1 and K2 value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

3.7 Status Register Overview

0x38—LINE_STATUS (Line Framer/PHY Interrupt Status Register) . . . . . . . . . . . . . . . . . . . . . . . . 3-29

0x39—EVENT_STATUS (Event Interrupt Status Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

0x3A—OVFL_STATUS (Counter Overflow Interrupt Status Register) . . . . . . . . . . . . . . . . . . . . . . . 3-37

0x3B—CELL_STATUS (Interrupt Status Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

0x3C—RXFEAC_VER (Receive FEAC/Part Number/Version Number Register) . . . . . . . . . . . . . . . . 3-38

3.8 Event/Error Counters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

4.0 Electrical and Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Power Requirements and Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.1 Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.2 Line Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3.3 FIFO Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.3.4 UTOPIA Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

4.3.5 TAXI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

4.4 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Appendix A:Transmit FIFO Port Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.1 Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.2 Port Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

A.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Appendix B:Acronym List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

vi Conexant 100046C

Page 7

CN8223 List of Figures

ATM Transmitter/Receiver with UTOPIA Interface

List of Figures

Figure 1-1. CN8223 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Figure 1-2. Line Framer Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Figure 1-3. CN8223 Cell Processing Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Figure 1-4. FIFO Port/UTOPIA Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10

Figure 1-5. Line Interface Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Figure 1-6. CN8223 Connected to CAT 5 or PMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Figure 1-7. CN8223 Connected to Bt8360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-14

Figure 1-8. CN8223 Connected to Bt8510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15

Figure 1-9. CN8223 Connected to Bt8370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15

Figure 1-10. CN8223 Connected to TDK 78P7200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Figure 1-11. CN8223 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

Figure 1-12. CN8223 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Figure 2-1. CN8223 Receiver Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

Figure 2-2. CN8223 Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Figure 2-3. Internal Framer Transmitter Interface Timing with Line Encoding. . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-4. Internal Framer Transmitter Interface Timing Without Line Encoding. . . . . . . . . . . . . . . . . 2-5

Figure 2-5. Internal Framer Receiver Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Figure 2-6. Timing for Internal Framer Receiver, Encoder Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Figure 2-7. DS1 Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Figure 2-8. E1 Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Figure 2-9. DS3 Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Figure 2-10. E3 Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Figure 2-11. Receiver DS1 Line Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12

Figure 2-12. Transmit Framing Overhead Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Figure 2-13. Receive Framing Overhead Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Figure 2-14. Transmit Parallel Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

Figure 2-15. Receive Parallel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Figure 2-16. Transmit FIFO Port Interface Timing, 53-Octet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

Figure 2-17. Receive FIFO Port Interface Timing, 53-Octet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

Figure 3-1. LINE_STATUS and OOF Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

Figure 3-2. Register Summary, Cheat Sheet 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

Figure 3-3. Register Summary, Cheat Sheet 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47

Figure 4-1. Local Processor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Figure 4-2. Line Interface Timing—DS1, E1, DS3, E3 External Framers . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Figure 4-3. Line Interface Timing–Internal Framers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Figure 4-4. Parallel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Figure 4-5. Overhead Port Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

100046C Conexant vii

Page 8

List of Figures CN8223

ATM Transmitter/Receiver with UTOPIA Interface

Figure 4-6. FIFO Port Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Figure 4-7. UTOPIA Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

Figure 4-8. TAXI Port Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

Figure 4-9. CN8223 160-Pin Plastic Quad Flat Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

viii Conexant 100046C

Page 9

CN8223 List of Tables

ATM Transmitter/Receiver with UTOPIA Interface

List of Tables

Table 1-1. CN8223 Version Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Table 1-2. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Table 2-1. Valid CONFIG_1 Line Mode Settings, Bits 7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Table 2-2. Internal Framer Transmitter Interface Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Table 2-3. Internal Framing Unencoded Transmitter Connections (STS-3c, STM-1, E4) . . . . . . . . . . . 2-5

Table 2-4. Internal Framer Receiver Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 2-5. Connections for Internal Framer Rx, Encoder Disabled (STS-3c, STM-1, E4). . . . . . . . . . . 2-7

Table 2-6. Serial External Framer Transmitter Interface Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Table 2-7. External Framing Mode Receiver Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Table 2-8. DS3 Overhead Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Table 2-9. G.832 E3 and E4 Overhead Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Table 2-10. G.751 E3 Overhead Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Table 2-11. C1 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Table 2-12. STS-1, STS-3c, and STM-1 Overhead Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Table 2-13. Status Indications for All Modes (Register 0x38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

Table 2-14. Pin Connections between TAXI Chipset and CN8223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

Table 2-15. Transmit Parallel Interface Mode Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

Table 2-16. Receive Parallel Interface Mode Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Table 2-17. Cell Generation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

Table 2-18. Overhead Field Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

Table 2-19. Status Octet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

Table 2-20. PT Header Field and User Data Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-31

Table 2-21. FEBE Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

Table 2-22. C1 Octet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

Table 2-23. FIFO Interface Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

Table 2-24. FIFO Transmit Pin Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

Table 2-25. FIFO Receive Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

Table 2-26. Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

Table 2-27. UTOPIA Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

Table 2-28. Byte Transmission Times for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46

Table 3-1. ATM Transmitter/Receiver Status Registers, Counters, and Data Link Control . . . . . . . . . . 3-1

Table 3-2. ATM Transmitter/Receiver Microprocessor Control Registers . . . . . . . . . . . . . . . . . . . . . . . 3-2

Table 3-3. Valid Combinations of CONFIG_1, Bits 0–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Table 3-4. Alarm Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Table 3-5. Alarm Transmission—STS–1/STS–3c/STM–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Table 3-6. Overhead Generation Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Table 3-7. CELL_GEN_x Control Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

Table 3-8. Tx_HDRx Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18

Table 3-9. HDR_VALx Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

100046C Conexant ix

Page 10

List of Tables CN8223

ATM Transmitter/Receiver with UTOPIA Interface

Table 3-10. HDR_MSKx Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

Table 3-11. ATM Transmitter/Receiver Status Registers, Counters, and Data Link Control . . . . . . . . . 3-28

Table 3-12. STS-1,STS-3c, STM-1 LINE_STATUS Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

Table 3-13. DS3 PLCP and Direct Mapping Mode LINE_STATUS Bit Definitions. . . . . . . . . . . . . . . . . 3-31

Table 3-14. E3 G.832, E4 G.832 LINE_STATUS Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

Table 3-15. E3 G.751 LINE_STATUS Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

Table 3-16. External Framer, 57-Octet Mode, LINE_STATUS Bit Definitions . . . . . . . . . . . . . . . . . . . . 3-34

Table 3-17. Status Indications for All Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35

Table 3-18. Line and Interface Events/Errors Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

Table 3-19. Counted Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40

Table 3-20. Internal STS-1, STS-3c Event/Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

Table 3-21. Internal DS3 PLCP and Direct Mapping Modes Event/Error Counters. . . . . . . . . . . . . . . . 3-42

Table 3-22. Internal G.832 E3/E4 Event/Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43

Table 3-23. Internal G.751 E3 Event/Error Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44

Table 3-24. External Framer, 57-Octet Mode Event/Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45

Table 4-1. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Table 4-2. Microprocessor Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Table 4-3. Line Interface Timing—DS1, E1, DS3, E3 External Framers . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Table 4-4. Line Interface Timing—Internal Framers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Table 4-5. Parallel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Table 4-6. Overhead Port Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Table 4-7. FIFO Port Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

Table 4-8. UTOPIA Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Table 4-9. TAXI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

Table A-1. Cell Thresholds (1 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

x Conexant 10046C

Page 11

1.0 Product Description

The CN8223 ATM Physical Interface (PHY) device is a transmitter/receiver which converts several types of frames to ATM cells and vice versa. The device contains framers for DS3, E3, E4, STS-1, STS-3c, and STM-1. This chapter provides an overview of the CN8223, describing its primary features and applications. A block diagram and a logic diagram are included.

1.1 Block Diagram

Figure 1-1 is a detailed block diagram of the CN8223. The host system transmits

octet-wide data to the CN8223 via the UTOPIA or FIFO ports. This data is assembled into ATM cells by the PHY and formatted for serial line transmission by the CN8223’s line framers. In the receive direction, serial network data is framed into octets by either internal or external line framers and passed to the ATM cell processing block. Octet data is then aligned into ATM cells, checked, and sent through the UTOPIA or FIFO ports to the host system.

The line framer block connects to external interfaces for line reception and transmission. The line framer has interfaces for seven data rates and provisions for external serial or parallel framers. Also included are overhead interfaces, data links, and event counters.

The HEC/PLCP ATM cell alignment block accepts octet data from the line framer block. It generates cells for transmission and validates received cells. Included are HEC/PLCP generators and detectors, data scramblers, and counters.

The FIFO Port/UTOPIA interface communicates with the next layer of ATM processing, usually residing in the host system. It directs received cell traffic to four ports, controls transmit priority and rate, and has counters for events and errors.

100046C Conexant 1-1

Page 12

1.0 Product Description CN8223

1.1 Block Diagram ATM Transmitter/Receiver with UTOPIA Interface

Figure 1-1. CN8223 Detailed Block Diagram

PRCLK

CS~ AS~

W/R~

OE~

SEL8BIT

TMRKR

TOVH_CLK A[7:1]

TXOVH

DL_INT

STAT_INT D[15:0]

TCLKO_HS

TXOUT_HS

TXCKI_HS± RXCKI_HS±

RXIN_HS±

TCLKO

TXOUT

TXCKI

RXCKI

RXIN

RCV_HLD

LOCD

TXOUT[7:0]

RXIN[7:0]

Interrupt Control

and PLCP

Framer

and PLCP

Framer

Section

Cell Counters

Performance

Monitoring

Generation,

and Priority

Validation

Rx VPI/VCI

Screening

Clock and

Control

ONESECI

8KCKI

NTEST

TEST1, 3

RESET

Microprocessor

Interface

Tx Cell

Tx Rate

Rx Cell

ONESECO

FIFO Data Ports Section

4-Port

FIFO Data

Interface

UTOPIA Interface

and

4-Cell

Buffers

Port 0 Ctrl

Port 1 Ctrl

Port 2 Ctrl

Port 3 Ctrl

UTOPIA Ctrl

CN8223

FCTRL_OUT[16:0] FCTRL_IN[7:0]

FDAT_IN

FDAT_OUT

8223_001

± ±

Line

Interfaces

High

Speed

Medium

Speed

Parallel

Interface

Line Framer Section Cell Processing

HDLC

FEAC

DS3, E3, E4, STS-1

STS-3c, STM-1

G.832

Transmit Framer

DS3, E3, E4, STS-1

STS-3c, STM-1

G.832

Receive Framer

FEAC

Overhead

Insert

Overhead

Extract

RMRKR

ROVH_CLK

Transmit G.832

Receive G.832

RXOVH

1-2 Conexant 100046C

Page 13

CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

1.2 CN8223 Features

The CN8223 ATM Transmitter/Receiver provides a single-access ATM service termination for UNI and NNI. It conforms to the following specifications and recommendations:

• ATM Forum UNI Specification 94/0317

• Bellcore Specifications TR-TSV-000772, TR-TSV-000773,

TR-NWT-000253, and T1S1/92-185

• ITU Recommendations I.432, G.707, G.751, G.832, and Q.921

• ETSI draft standards prETS 300 213 and 300 214

Both terminal and switching system interface functions are provided. The CN8223 provides DS1, E1, DS3, E3, E4, STS-1, and STS-3c (STM-1) Physical Layer Convergence Procedure (PLCP) functions. It optionally provides for the generation and validation of AAL3/4 and AAL5 ATM cell payloads. The system interfaces to the ATM layer through either a UTOPIA-compatible port or a parallel FIFO port. Provisions for source rate control are included in the transmitter circuitry.

1.2 CN8223 Features

1.2.1 Internal Framers

1.2.2 UTOPIA Port

Internal framers are included for DS3 C-bit parity format, G.751 E3 format, G.832 E3 and E4 formats, and STS-1/STS-3c/STM-1 formats. Cell delineation is via either PLCP framing overhead or G.832 Header Error Control (HEC) alignment. The CN8223 parallel line interface allows octet recovery/transmission externally for 100 Mbps TAXI or other interfaces.

The DS1, DS3, E1, and E3 data stream interfaces connect directly to Conexant framers (Bt8360C for DS1, Bt8510B for E1, Bt8370 for E1/T1 with integral Line Interface Unit (LIU), and Bt8330B for DS3 and E3). DS1 and DS3 PLCP functions conform to Bellcore Standard TR-TSV-000773; E1 PLCP conforms to ETSI draft standard prETS 300 213; and E3 PLCP conforms to ETSI draft standard prETS 300 214. Transmit and receive functions are provided for all line rates up to 155 Mbps.

The UTOPIA port conforms to the ATM Forum UTOPIA Level 1 Specification (Version 2.01) and provides both octet- and cell-based handshaking. The interface contains transmit and receive buffer FIFOs with a depth of four cells programmable for reduced latency requirements per ATM Forum document 94/0317. This interface conforms to the Saturn Compliant Interface for ATM PHY Devices Specification.

The microprocessor can set control registers for insertion of selected header fields by the transmitter on an individual port basis. Also, the processor can control insertion of all overhead and can insert errors in selected fields for test equipment applications.

100046C Conexant 1-3

Page 14

1.0 Product Description CN8223

1.2 CN8223 Features ATM Transmitter/Receiver with UTOPIA Interface

1.2.3 Programmable Parity Protection

Programmable parity protection is available on the system interface. Read and write strobes allow addressing of up to four distinct data sources and output to four distinct destinations. Each transmitter port has a programmable priority level. If the priority levels are the same, the ports are addressed in sequence. Each receiver port can be programmed with a particular VCI/VPI address for message routing. Also, VCI/VPI pages can be selected via masking registers. Cells can be routed to multiple ports for broadcast capability and enhanced test, diagnostic, and maintenance functions. Also, the cell validation function can be programmed to correct single-bit header errors.

1.2.4 Test and Diagnostic Functions

The CN8223 provides access to the ATM protocol at all levels for test and diagnostic functions. Octet-wide simultaneous interfaces are provided for transmit and receive access to PLCP slots (57 octets), ATM cells (53 octets), cells without HEC (52 octets), or cell payload only (48 octets). This interface allows the implementation of test and diagnostic systems. Also, per-cell status can be optionally provided in place of the HEC octet on Port 3 in a special output mode.

1.2.5 Microprocessor Interface Features

All control and status functions are provided via a direct microprocessor interface. Also, the microprocessor can control the external framers as required. The microprocessor interface can be used with either an 8- or 16-bit data bus with separate address and data signals. Interrupt outputs are provided for status information on cell and physical layer performance and for data link operations. The interface is a clocked 8- or 16-bit data interface with an address strobe and a single read/write control.

1-4 Conexant 100046C

Page 15

CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

1.3 Line Framing Functions

The CN8223 provides framers for DS3, E3 (both G.751 and G.832), E4 (G.832), STS-1, and STS-3c/STM-1 formatted serial streams. The line receive circuitry recovers the frame location from the serial stream and provides cell octets to the physical layer block for cell delineation. The transmit circuitry receives cell octets from the cell generation or physical layer blocks and adds line framing overhead information as required. The LIU receive interface detects both Loss-of-Signal (LOS) and Line Code Violations (LCVs). The active edge of the transmit output clock is selectable. Figure 1-2 illustrates the line framer functions of the CN8223.

Figure 1-2. Line Framer Diagram

TCLKO_HS

TXOUT_HS

TXCKI_HS±

RXCKI_HS±

RXIN_HS±

TCLKO

TXOUT

TXCKI

RXCKI

RXIN

RCV_HLD

LOCD

TXOUT[7:0]

RXIN[7:0]

± ±

Line

Interfaces

High

Speed

Medium

Speed

Parallel

Interface

TMRKR

TOVH_CLK

HDLC

DS3, E3, E4, STS-1

Transmit Framer

DS3, E3, E4, STS-1

STS-3c, STM-1

Receive Framer

HDLC

FEAC

STS-3c, STM-1

FEAC

1.3 Line Framing Functions

TXOVH

Overhead

Insert

CN8223 Cell Processing

Overhead

Extract

RMRKR

ROVH_CLK

RXOVH

8223_002

CN8223 line framing functions include the following:

• STS-1, STS-3c, STM-1, DS3, E3, E4, TAXI

• External framer interface

• Parallel interface

• Unframed serial interface

• HDB3/B3ZS encode/decode

• Line overhead insertion/extraction

• SONET scrambling

• Error insertion

• Alarm detection/generation

100046C Conexant 1-5

Page 16

1.0 Product Description CN8223

1.3 Line Framing Functions ATM Transmitter/Receiver with UTOPIA Interface

1.3.1 Interfaces

The CN8223 has a serial external framer interface for T1, E1, T3, and E3. The internal B3ZS/HDB3 encoder/decoder can be bypassed in any mode for direct input/output of NRZ data and clock.

The line signal interface consists of clock, serial or octet data, and sync signals from either the internal or external framers. Both framed and unframed modes are usable at DS1, E1, DS3, and E3 line rates. In framed mode, the frame/overhead bit positions of the transmission format are located through a synchronization signal and are generated as idle bits or ignored. In unframed mode, a serial signal that contains no line overhead bit positions is expected.

The transmitter interface has a clock signal input and provides a serial or octet data output. The receive signal interface consists of input clock and serial or octet data from the transmission physical layer framer. Also, synchronization inputs are provided for use with external framers. The transmit and receive sections of the interface are clocked independently.

A parallel line interface is available for external framers and other devices. It consists of a receive clock and octet and a transmit clock and octet. This interface permits clocking externally recovered octets directly to and from the cell delineation function block. Use of the parallel interface assumes all line overhead information has been removed externally and proper octet alignment has been recovered.

1.3.2 Line Loopback

A line loopback connects the receive clock and data inputs directly to the transmit clock and data outputs. LCVs are preserved in this loopback. Raw yellow alarm indications and Out-of-Frame (OOF) events are integrated to provide yellow alarm and Loss-of-Frame (LOF) indications, respectively. PHY error counters can be programmed to accumulate errors over one-second periods and latch the results. Line framing functions are described in detail in Section 2.2.

1-6 Conexant 100046C

Page 17

CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

1.3.3 BIP-8 Code

The octet Bit Interleaved Parity (BIP-8) code is checked and error status generated for the Far End Block Error (FEBE) function and yellow alarm. BIP-8 code violations and framing-octet errors are counted. OOF events are detected and counted. The transmitter output can be looped to the receiver input for test purposes and to perform startup self-tests and diagnostics.

In all PHY modes, an OOF input from the internal or external framer can be used to indicate that the received signal is not being received correctly. This input inhibits cell validation functions and initiates cycle stuffing, when required.

1.3.4 Alarm Detection/Generation

All line alarm and error conditions including BIP codes are monitored and reported in status registers and event counters. Alarms and errors can be configured to generate an interrupt to the microprocessor. The CN8223 can transmit alarm and error conditions under microprocessor control.

1.3 Line Framing Functions

100046C Conexant 1-7

Page 18

1.0 Product Description CN8223

1.4 ATM Cell Processing Functions ATM Transmitter/Receiver with UTOPIA Interface

1.4 ATM Cell Processing Functions

Figure 1-3 illustrates the CN8223 cell processing block, which assembles

received octet data from the line framers into ATM cells. During transmit, this block constructs ATM cells for the line transmitter circuits. The ATM cell processing block can generate or receive either the 57-octet framed PLCPs or the 53-octet direct-mapped formats. Status indications include 16-bit counters for PLCP OOF or Loss-of-Cell (LOC) delineation events, framing-octet errors, and BIP-8 code violations for both the near and far end. All alarm indications are provided and can be programmed to generate interrupts.

Figure 1-3. CN8223 Cell Processing Block

Transmit G.832

and PLCP

Framer

Line Framers

Block

Receive G.832

and PLCP

Framer

Tx Cell

Generation,

Tx Rate

and Priority

FIFO/UTOPIA Ports Block

Rx Cell

Validation

Rx VPI/VCI

Screening

CN8223 cell processing block features include the following:

• Selectable HEC or PLCP alignment

• HEC calculation for ATM or SMDS

• HEC correction

• HEC Coset generation

• PLCP overhead control

• PLCP events and alarms control

• AAL3/4 CRC and length check support

• SONET scrambling

• ATM payload scrambling

• Error insertion

8223_003

1-8 Conexant 100046C

Page 19

CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

1.4.1 Cell Generation Functions

The CN8223 ATM cell processing block provides flexible control for cell generation. Cell generation is the formatting of 48-octet payload segments into 53-octet ATM cells, and the generation of appropriate header octets, HEC, and payload Cyclic Redundancy Check (CRC) calculations as required by the AAL formats. The CN8223 provides modes that perform this cell generation function, along with modes that allow insertion of any or all of the various header fields from either the FIFO interface or from microprocessor control registers. Four cell generation modes are available in the CN8223. Cell generation functions are described in detail in Section 2.6.

1.4.2 Tx Rate Control

Two Rate Control registers [0x08, 0x09] are provided for each of the four ports to allow programmable rate shaping of cell transmission. The ratio of active to idle cells is programmable with 0.4 % granularity. Status counts of non-idle cells transmitted are maintained for each of the four sources.

1.4.3 Cell Validation Functions

1.4 ATM Cell Processing Functions

Cell validation refers to the checking of cells coming in from the PHY block for proper format. The CN8223 provides modes that deliver 48-, 52-, or 53-octet cells, or 57-octet PLCP slots to the FIFO output ports. The validation process is described in detail in Section 2.6.

Protocol verification includes HEC validation with ATM or SMDS/802.6 coverage, validation of payload length per segment type, and correct payload CRC value. Status reporting of validation steps is via error counters and status register indications. Status bits can be programmed to generate interrupts to the microprocessor. Each validation step can be individually disabled.

100046C Conexant 1-9

Page 20

1.0 Product Description CN8223

1.5 FIFO Port/UTOPIA Interface ATM Transmitter/Receiver with UTOPIA Interface

1.5 FIFO Port/UTOPIA Interface

The CN8223 FIFO Port/UTOPIA interface is the data connection for the host system. Figure 1-4 illustrates the functions in this block. This block has two modes for interfacing with ATM cells: four FIFO ports or one ATM Forum Level 1 Compliant UTOPIA port.

Figure 1-4. FIFO Port/UTOPIA Interface Block

ATM Cell

Processing

Block

Rx VPI/VCI

1.5.1 UTOPIA Mode

Screening

Port 0 Ctrl

4-Port

FIFO Data

Interface

UTOPIA Interface

and

4-Cell

Buffers

FIFO port/UTOPIA interface block features include the following:

• Four byte-wide FIFO ports

• UTOPIA port with four-cell buffer

• Port rate and priority control

• Idle cell TX/Rx

• Per-port ATM header screening

• 48-, 52-, 53-, and 57-octet cell modes

Port 1 Ctrl

Port 2 Ctrl

Port 3 Ctrl

UTOPIA Ctrl

FCTRL_OUT[16:0] FCTRL_IN[7:0]

FDAT_IN FDAT_OUT

ATM Layer

Cell Processing

FIFO

8223_004

UTOPIA mode implements a single 25 MHz, 8-bit plus parity bidirectional interface with four cells of internal FIFO in both directions. Parity is optional. When the UTOPIA interface mode is used, only 53-octet output is available.

1.5.2 FIFO Ports

Cells are routed to one of four output ports if a match to that port’s programmable header value is made. This can be used to route received VCI/VPIs to a chosen port. Four modes are available for FIFO port cell output:

• A test mode writes the entire 57-octet PLCP slot to the FIFO interface.

• A 53-octet mode writes the 53-octet ATM cell to the FIFO interface.

• A 52-octet mode writes the ATM cell without the HEC octet to the FIFO

interface.

• A final mode delivers 48-octet cell payloads to the FIFO interface.

1-10 Conexant 100046C

Page 21

CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

1.5.3 ATM Interface

Each cell is sent to a buffer to allow for header processing before being output to the ATM interface. The buffer length is 10 octets for G.751 PLCP modes, and 6 octets for HEC alignment. A “cell-valid” output is provided to indicate that none of the enabled error checks detected an error. The UTOPIA internal FIFO or external circuitry is notified to discard the cell when the valid indication goes inactive. Idle cells are automatically deleted from the ATM layer output. Parity and control/delineation signals are provided with each octet at the port interface. The microprocessor receives status and error counts as cell validation proceeds.

All event and error counters can be programmed to cause an interrupt on overflow. Reading the interrupt source register allows the microprocessor to identify overflows and thus update internal counts. All counters can be read by the microprocessor and are cleared when read.

1.5 FIFO Port/UTOPIA Interface

100046C Conexant 1-11

Page 22

1.0 Product Description CN8223

1.6 Line Interface Applications ATM Transmitter/Receiver with UTOPIA Interface

1.6 Line Interface Applications

With minimal glue logic, the CN8223 provides interfaces to STS-3c, STM-1, DS3, E3, TAXI, DS1, or E1 equipment. Multiple line rates can be supported with a single design if the line interface is on a daughter card. Figure 1-5 illustrates the configuration for several line interfaces.

Figure 1-5. Line Interface Applications

SONET

Fiber

Copper

Line

Fiber or

Copper

Line

STS-3c, STM-1 Interface

Optical

Transceiver

DS3, E3 Interface

Line

Transformer

TAXI Interface

Optical or Electrical

Interface

DS1 or E1 Interface

Line

Transformer

Clock

Recover

Line Interface Unit Chip

AMD TAXI

Chipset

Bt8360 or Bt8510 or

Bt8370

CN8223 High-Speed Serial Line Interface

CN8223 Low-Speed Serial Line Interface

CN8223 External Framer Parallel Interface

CN8223 External Framer Serial Interface

CN8223 Signal Names

TXCKI_HS+/–, TCLKO_HS+/–, TXOUT_HS+/–, RXCKI_HS+/–, RXIN_HS+/–

TXCKI, TCLKO, TXPOS, TXNEG, RXCKI, RXPOS, RXNEG, RXLOS

TXCKI, TCLKO, TXIN, TXOUT[8:0], RXCKI, RXIN, TXOUT[8:0], RCV_HLD

TXCKI, TXIN, TXOUT[3], RXCKI, RXIN[0,3,4]

8223_005

1-12 Conexant 100046C

Page 23

CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

1.7 CN8223 Versions

Table 1 -1 describes the revision history of the Bt8222 device. The Bt8222 is the

predecessor of the CN8223.

Table 1-1. CN8223 Version Descriptions

Version Description

Bt8222KPF Baseline version (derived from the Bt8220/1).

Bt8222KPFB All Bt8222KPF functionality plus:

The version number was changed to 62H in the lower byte of the RX_FEAC_VER register. A software reset was added to CONFIG_5, bit 7. When active high, this is a software equivalent

to pin 118.

Additional overhead insertion capability for STS-3c, STM-1: G1, K2 #1, and Z2 #3 can be inserted from the external overhead bus. It is controlled by CONFIG_3, bit 6. This is used for automatic protection switching.

CONFIG_5 has a new receive status indication. CONFIG_5, bit 9 now shows octet G1, bit 5 of received frames.

1.7 CN8223 Versions

Bt8222KPFC All Bt8222KPFB functionality plus:

The version number was changed to 63H in the lower byte of the RX_FEAC_VER register.

The STM-1 C2 transmit octet = 0x13. The C2 receive octet is checked for 0x01 or 0x13.

Bt8222KPFD or

Bt8222EPFD

Bt8222EPFE All Bt8222KPFD/EPFD functionality plus:

Bt8222EPFF All Bt8222EPFE functionality plus:

Legend for Version Numbers:

K = Temperature range 0

°C to 85 °C

E = –40 PF = Package code = 160-pin PQFP A/B/C/D/E = Product version

All Bt8222KPFC functionality plus:

The version number was changed to 64H in the lower byte of the RX_FEAC_VER register.

TAXI command strobe timing eliminates the need for an external buffer.

The G1 octet complies with T1.105. The RDI alarm includes bit 7.

The K1/K2 registers were added to provide further support for SONET APS.

HEC integration was removed.

The device complies with a footnote in the UTOPIA specification that allows RxENB~ to be permanently asserted by the ATM layer.

Disable HEC Check (bit 9 in CELL_VAL) was changed when in UTOPIA mode to be consistent with FIFO mode.

Payload checking will comply with the ATM standards (lengths 8-44).

When switching to PLCP mode dynamically, the device will go to an OOF state.

FIFO read strobes are forced inactive (high) during hardware or software resets.

RMRKR[1] was changed to be an 8 kHz output synchronized to the received PLCP frame.

Line Loopback (bit 9) in the CONFIG_3 register (0x02) is cleared upon assertion of RESET (pin

118).

Receive STS/SDH pointer processing complies with standards.

°C to 70 °C

100046C Conexant 1-13

Page 24

1.0 Product Description CN8223

1.8 CN8223 Applications ATM Transmitter/Receiver with UTOPIA Interface

1.8 CN8223 Applications

The CN8223 can be connected to several types of framers and PMDs. Figure 1-6 illustrates a general application where the CN8223 is connected to either a CAT 5 or Fiber Optic PMD. Figure 1-7 illustrates an example implementation of the CN8223 using a Bt8360 External T1 Framer.

Figure 1-6. CN8223 Connected to CAT 5 or PMD

UTOPIA

Tx Bus

CN8223

UTOPIA

Rx Bus

Control Bus

Figure 1-7. CN8223 Connected to Bt8360

CN8223

TXCKI

ATM

Layer

Cells

TXIN

TXOUT[3]

RXCKI

RXIN[3]

RXIN[0]

RXIN[4]

TXDATO

RXDATI

RXLOS*

RxData ±

RxCLK ±

TxCLK ±

(Analog Devices

AD6116)

(Cypress

Semiconductor

CX7B952)

Signal

TXCKI

TXSYI

RXCKI

RXSYI

TxData ±

Loss of Signal

Clock Recovery

Circuit

19.44 MHz Oscillator

XBCKI

XCKI

XBSFSYO

XPCMI

SLSYI

RCKO/SLCKI

RFSYO/SLFSYO

RPCMO/SLPCMO

Bt8360

Pin Pin

29 43

37/49

38/41

36/55

Raw RD ±

CAT 5 UTP

Engineering

(PE-68532G or

PE-68538G)

Transceiver

(Sumitomo

SDM 4201-XC)

XPOSO

XNEGO

XCKO

RPOSI

RNEGI

RCKI

Pulse

Fiber

Module

8223_006

Tx Data

LIU

Rx Data

Derived

Tx Clock

System Clock

8223_007

1-14 Conexant 100046C

Page 25

CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

Figure 1-8 illustrates an example implementation of the CN8223 using a

Bt8510 External E1 Framer. Figure 1-9 illustrates an example implementation of the CN8223 using a Bt8370 External T1/E1 Framer.

Figure 1-8. CN8223 Connected to Bt8510

CN8223

ATM

Layer

Cells

TXCKI

TXIN

TXOUT[3]

RXCKI

RXIN[3]

RXIN[0]

Signal

TXCKI

TXSYI

T XPAT O

RXCKI

RXSYI

RXDATI

System Clock

XCKI

XSYNCO

XPCMI

RCKO

RSYNCO

RPCMO

Bt8510

1.8 CN8223 Applications

8223_008

Figure 1-9. CN8223 Connected to Bt8370

ATM

Layer

Cells

CN8223

TXOUT[3]

RXIN[3]

RXIN[0]

TXCKI

TXIN

RXCKI

System Clock

Signal

TXCKI

TXSYI

T XPAT O

RXCKI

RXSYI

RXDATI

TSBCKI

TCKI

TMSYNC

TPCMI

RCKO

RMSYNC

RPCMO

Bt8370

8223_009

100046C Conexant 1-15

Page 26

1.0 Product Description CN8223

1.8 CN8223 Applications ATM Transmitter/Receiver with UTOPIA Interface

Figure 1-10 illustrates an example implementation of the CN8223 using a

TDK 78P7200 T3 LIU. Unused pins on the CN8223 must be tied as follows: unused RXIN_8:0 pins tie to ground, PECL inputs RXCKI_HS±, RXIN_HS±, and TXCKI_HS± tie to +5 V.

Figure 1-10. CN8223 Connected to TDK 78P7200

ATM

Layer

Cells

CN8223

TCLKO

TXOUT[2]

TXOUT[1]

RXCKI

RXIN[2]

RXIN[1]

RXIN[4]

TXCKI

Signal

System Clock (44.736 MHz)

TDK 78P7200

TCLK

TNEG

TPOS

RCLK

RNEG

RPOS

LOWSIG

8223_010

1.8.1 CN8223 as a DS3 or E3 G.751 Framer without ATM Cell Delineation

The CN8223 can be used as a DS3 or an E3 G.751 framer with parallel input and serial output by making the following changes:

• Set the configuration registers for transparent operation.

• Disable the parallel interface.

• Disable line loopback.

In this setup, the receive frame sync pulse is on pin 43, TXOUT[5]. Data is received on pin 56, TXOUT[6]. The receive clock is derived from the LIU device. Data is transmitted through the parallel UTOPIA interface.

1-16 Conexant 100046C

Page 27

CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

1.9 Logic Diagram

The CN8223 is a single CMOS integrated circuit, packaged in a 160-pin Plastic Quad Flat Pack (PQFP). Figure 1-11 illustrates a CN8223 logic diagram. The line framer/PHY interface consists of 33 pins. The framing overhead interface consists of 22 pins. The FIFO interface consists of 18 data pins, 8 control inputs, and 17 control outputs. The microprocessor interface consists of 8 clock and control inputs, a 16-bit data bus, a 7-bit address bus, and 2 interrupt outputs. Additionally, there are 11 power and 12 ground pins. Detailed pin descriptions are given in Table 1 -2 .

Clock and control inputs consist of an external 8 kHz reference for the PLCP at E3 and DS3 rates, a one-second input to synchronize status collection timing in multiple-port applications, a “hold receiver” input that can externally disable cell validation when an external framer loses frame or signal, three test inputs, and a reset input. A one-second clock output is provided to allow synchronization of status collection for multiple CN8223s or for CN8223s and framers. When a single CN8223 is used, ONESECO should be connected to ONESECI. This timing output is derived from the external 8 kHz reference clock input on 8KCKI. An 8 kHz clock from the line receiver is available on RMRKR[1], pin 8.

1.9 Logic Diagram

NOTE: RMRKR[1] is not available in DS-3 direct cell mapping mode.

100046C Conexant 1-17

Page 28

1.0 Product Description CN8223

1.9 Logic Diagram ATM Transmitter/Receiver with UTOPIA Interface

Figure 1-11. CN8223 Logic Diagram

Receive Clock Input Receive Clock In PECL

Receive Serial In PECL

Receive Input

Transmit Clock Input

Transmit Clock In PECL

Transmit Input

Transmit Overhead

Bus In

FIFO Data Bus In

FIFO Control Input

8/16-Bit Mode Select

Processor Clock

Chip Select

Address Strobe

Write/Read Control

Output Enable

Processor Data Bus

Address Bus

I I

I I I

I/O

10 11,12

20,21

15–19,

154,155

22,25

30 23,24

44–51

98–105,

108

109–116

97 96 94 95 92

65,

68–79,

82–84

85–91

RXCKI

RXCKI_HS RXIN_HS±

RXIN[8:0] TXCKI TXCKI_HS TXIN

Line Framer/PHY

Framing Overhead

TXOVH[7:0]

UTOPIA/FIFO

FDAT_IN[8:0]

FCTRL_IN[7:0]

SEL8BIT PRCLK

CS AS~ W/R~ OE~

D[15:0] A[7:1]

Microprocessor

Interface

FCTRL_OUT[16:0]

Interface

TCLKO

TXOUT[8:0]

TCLKO_HS TXOUT_HS±

LOCD

RXOVH[7:0]

RMRKR[1:0]

ROVH_CLK[1:0]

TOVH_CLK

TMRKR

FDAT_OUT[8:0]

DL_INT

STAT_INT

31 33–36,

42,43, 56–58

28,29 38,39

122

2–5, 156–159

8,9 6,7

55 52

143–145, 148–153

124–132, 135–142

63 64

Transmit Clock Output

Transmit Outputs

Transmit Clock Out PECL

Transmit Serial Out PECL

Loss of Cell Delineation

Receive Overhead Bus Out

Receive Overhead Markers

O O

Receive Overhead Clocks Transmit Overhead Clock

Transmit Overhead Marker

FIFO Data Bus Out

FIFO Control Outputs

OOFEAC/HDLC Interrupt

Status/Counter Interrupt

8 kHz Clock Input

One-Second Clock Sync

Receiver Hold Input

Test Input

Test Inputs

Reset

I I I I

117,

I I

123

119

118

8KCKI ONESECI RCV_HLD NTEST TEST1, TEST3 RESET

Clock and Control

I = Input, O = Output

ONESECO

O One-Second Output

8223_011

1-18 Conexant 100046C

Page 29

CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

1.10 Pin Definitions

Figure 1-12 is a pinout diagram for the 160-pin ATM Transmitter/Receiver. Table 1 -2 lists pin names and numbers. Generally, all unused input pins should be

connected to ground and unused outputs should be left unconnected. However, if pins TXOVH_7 to TXOVH_0 or RXIN_8 to RXIN_0 are not used, they must be tied to a logic low level. Some of the RXIN pins may be used depending on the configuration. If PECL inputs, RXCKI_HS±, RXIN_HS±, or TXCKI_HS±, are not used, they must be tied to +5 V power.

Figure 1-12. CN8223 Pinout Diagram

FDAT_IN[8]

FCTRL_IN[3]

FCTRL_IN[2]

FCTRL_IN[1]

FCTRL_IN[0]

VCC

112

111

110

109

108

107

Transmitter/Receiver

10111213141516171819202122232425262728293031323334353637383940

GND

LOCD

RCV_HLD FCTRL_OUT[0] FCTRL_OUT[1] FCTRL_OUT[2] FCTRL_OUT[3] FCTRL_OUT[4] FCTRL_OUT[5] FCTRL_OUT[6] FCTRL_OUT[7] FCTRL_OUT[8]

GND

VCC

FCTRL_OUT[9]

FCTRL_OUT[10] FCTRL_OUT[11] FCTRL_OUT[12] FCTRL_OUT[13] FCTRL_OUT[14] FCTRL_OUT[15] FCTRL_OUT[16]

FDAT_OU T[0] FDAT_OU T[1] FDAT_OU T[2]

GND

VCC FDAT_OU T[3] FDAT_OU T[4] FDAT_OU T[5] FDAT_OU T[6] FDAT_OU T[7] FDAT_OU T[8]

RXIN[7]

RXIN[8] RXOVH[0] RXOVH[1] RXOVH[2] RXOVH[3]

VCC

TEST3

119

121

120 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160

123456789

RESET

118

TEST1

117

FCTRL_IN[7]

116

FCTRL_IN[6]

115

FCTRL_IN[5]

114

FCTRL_IN[4]

113

GND

106

FDAT_IN[7]

105

FDAT_IN[6]

104

FDAT_IN[5]

FDAT_IN[4]

FDAT_IN[3]

FDAT_IN[2]

FDAT_IN[1]

FDAT_IN[0]

PRCLK

CS*

W/R*

AS*

GND

OE*

A[7]

A[6]

99989796959493929190898887868584838281

103

102

101

100

AT M

CN8223

1.10 Pin Definitions

A[5]

A[4]

A[3]

A[2]

A[1]

D[15]

D[14]

D[13]

GND

VCC

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

VCC

GND

D[0]

STAT_INT

DL_INT

8KCKI

ONESECI

ONESECO

NTEST

TXOUT[8]

TXOUT[7]

TXOUT[6]

TOVH_ CLK

VCC

GND

TMRKR

TXOVH[7]

TXOVH[6]

TXOVH[5]

TXOVH[4]

TXOVH[3]

TXOVH[2]

TXOVH[1]

TXOVH[0]

TXOUT[5]

TXOUT[4]

GND

VCC

GND

RXOVH[4]

RXOVH[5]

RXOVH[6]

RXOVH[7]

RXCKI

RMRKR[1]

RMRKR[0]

ROVH_CLK[1]

ROVH_CLK[0]

RXIN[0]

RXIN[2]

RXIN[3]

RXIN[4]

RXIN[5]

RXIN_ HS–

RXIN_ HS+

RXIN[1]

RXCKI_HS–

RXCKI_HS+

VCC

GND

RXIN[6]

TXCKI_HS–

TXCKI_HS+

TXIN

TXCKI

TCLKO

TXOUT[0]

TXOUT[1]

TCLKO_HS–

TCLKO_HS+

TXOUT[2]

VCC

SEL8BIT

TXOUT[3]

TXOUT_HS–

TXOUT_HS+

8223_012

100046C Conexant 1-19

Page 30

1.0 Product Description CN8223

1.10 Pin Definitions ATM Transmitter/Receiver with UTOPIA Interface

Table 1-2. Hardware Signal Definitions (1 of 5)

Pin Label Signal Name No. Type I/O Definition

RXCKI Receive Clock

Input

RXCKI_HS– RXCKI_HS+

RXIN_HS– RXIN_HS+

RXIN[0] RXIN[1] RXIN[2] RXIN[3] RXIN[4] RXIN[5] RXIN[6] RXIN[7] RXIN[8]

TXCKI Transmit Clock

TXCKI_HS– TXCKI_HS+

TXIN Transmit Inputs 32 CMOS/TTL I Transmit serial data input for all modes except

Line Framer/PHY Interface

TCLKO Transmit Clock

Receive Clock Input

Receive Serial Input

Receive Input 15

Input

Transmit Clock Input

Output

10 CMOS/TTL I Receive clock for all line rates except STS-3c,

STM-1, and E4.

11 12

20 21

16 17 18 19 22

25 154 155

30 CMOS/TTL I Transmit clock for all modes except STS-3c,

31 CMOS/TTL O Transmit clock output for all modes except

PECL PECL

CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL

PECL PECL

IIDifferential PECL level for high-speed modes.

Receive clock for STS-3c, STM-1, and E4. Tie to +5 V if not used.

IIDifferential PECL level for high-speed modes.

Serial data in for STS-3c, STM-1, and E4. Tie to +5 V if not used.

Receive parallel and TAXI mode data inputs. Tie

to a logic low level if not used. I I I I I I I

STM-1, and E4.

IIDifferential PECL level for high-speed modes.

Transmit clock for STS-3c, STM-1, and E4. Tie to

+5 V if not used.

STS-3c, STM-1, and E4.

TXOUT[0] TXOUT[1] TXOUT[2] TXOUT[3] TXOUT[4] TXOUT[5] TXOUT[6] TXOUT[7] TXOUT[8]

TCLKO_HS+ TCLKO_HS–

TXOUT_HS+ TXOUT_HS–

LOCD Loss of Cell

Tra ns m it Output 3 3

Transmit Clock Out 28

Transmit Serial Out 38

Delineation

CMOS/TTL

PECL

122 CMOS/TTL O Asserted when cell synchronization is lost.

PECL

PECL PECL

Transmit parallel and TAXI mode data outputs.

O O O O O O O O

OODifferential PECL level. Transmit clock output for

STS-3c, STM-1, and E4.

OODifferential PECL level. Transmit serial data

output for STS-3c, STM-1, and E4.

1-20 Conexant 100046C

Page 31

CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

Table 1-2. Hardware Signal Definitions (2 of 5)

Pin Label Signal Name No. Type I/O Definition

TXOVH[0] TXOVH[1] TXOVH[2] TXOVH[3] TXOVH[4] TXOVH[5] TXOVH[6] TXOVH[7]

RXOVH[0] RXOVH[1] RXOVH[2] RXOVH[3] RXOVH[4] RXOVH[5] RXOVH[6] RXOVH[7]

RMRKR[1] RMRKR[0]

Framing Overhead Interface

Transmit Overhead Bus

Receive Overhead Bus

Receive Overhead Markers

44 45 46 47 48 49 50 51

156 157 158 159

2 3 4 5

8 9

CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL

CMOS/TTL CMOS/TTL

1.10 Pin Definitions

Transmit bus input for I

STS-1/STS-3c/STM-1/G.832 overhead. Tie to a I

logic low level if not used. I I I I I

Receive bus output for

STS-1/STS-3c/STM-1/G.832 overhead.

O O O O O O

OOUsed for overhead bus output. RMRKR[1] is an

8 kHz output synchronized to the received PLCP

frame. RMRKR[1] is not available in DS-3 direct

cell mapping mode.

ROVH_CLK[1] ROVH_CLK[0]

TOVH_CLK Transmit Overhead

TMRKR Transmit Overhead

Receive Overhead Clocks

Clock

Marker

CMOS/TTL

55 CMOS/TTL O Used for bus input.

52 CMOS/TTL O Used for bus input in modes 4, 5, 6 and 7 (OC3,

OOUsed for overhead bus output.

OC1, E4 and G.832 E3).

100046C Conexant 1-21

Page 32

1.0 Product Description CN8223

1.10 Pin Definitions ATM Transmitter/Receiver with UTOPIA Interface

Table 1-2. Hardware Signal Definitions (3 of 5)

Pin Label Signal Name No. Type I/O Definition

FDAT_IN[0] FDAT_IN[1] FDAT_IN[2] FDAT_IN[3] FDAT_IN[4] FDAT_IN[5] FDAT_IN[6] FDAT_IN[7] FDAT_IN[8]

FCTRL_IN[0] FCTRL_IN[1] FCTRL_IN[2] FCTRL_IN[3] FCTRL_IN[4] FCTRL_IN[5] FCTRL_IN[6] FCTRL_IN[7]

FDAT_OUT[0] FDAT_OUT[1] FDAT_OUT[2] FDAT_OUT[3] FDAT_OUT[4] FDAT_OUT[5] FDAT_OUT[6] FDAT_OUT[7]

UTOPIA/FIFO Interface

FDAT_OUT[8]

FCTRL_OUT[0] FCTRL_OUT[1] FCTRL_OUT[2] FCTRL_OUT[3] FCTRL_OUT[4] FCTRL_OUT[5] FCTRL_OUT[6] FCTRL_OUT[7] FCTRL_OUT[8] FCTRL_OUT[9] FCTRL_OUT[10] FCTRL_OUT[11] FCTRL_OUT[12] FCTRL_OUT[13] FCTRL_OUT[14] FCTRL_OUT[15] FCTRL_OUT[16]

FIFO Data Bus 98

99 100 101 102 103 104 105 108

FIFO Control Input 109

110 111 112 113 114 115 116

FIFO Data Bus Out 143

144 145 148 149 150 151 152 153

FIFO Control Outputs

124 125 126 127 128 129 130 131 132 135 136 137 138 139 140 141 142

CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL

CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL

CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL

CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL

I I I I I I I I I

I I I I I I I I

O O O O O O O O O

O O O O O O O O O O O O O O O O O

FIFO interface input data bus for transmit. See

Section 2.7.1.

FIFO interface empty/full flag inputs. See

Section 2.7.1.

FIFO interface output data bus for receive. See

Section 2.7.1.

FIFO interface strobe and control outputs. See

Section 2.7.1.

1-22 Conexant 100046C

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CN8223 1.0 Product Description

ATM Transmitter/Receiver with UTOPIA Interface

Table 1-2. Hardware Signal Definitions (4 of 5)

Pin Label Signal Name No. Type I/O Definition

SEL8BIT 8/16 Bit Mode

Select

PRCLK Processor Clock 97 CMOS/TTL I Clock input to the microprocessor interface. All

CS~ Chip Select 96 CMOS/TTL I Must be logic low to address chip. Must be low

AS~ Address Strobe 94 CMOS/TTL I If this pin is low, a new address is loaded on the

37 CMOS/TTL I If asserted, this pin selects an 8-bit

microprocessor bus. If not asserted, it selects a 16-bit bus.

inputs are synchronous to this clock except OE~. All read and write operations require two cycles of PRCLK. PRCLK must run continuously at a minimum frequency of 2 times the cell rate.

to enable a read or write operation and should be stable throughout the cycle.

rising edge of PRCLK for the operation in the following clock period. If this pin is high and CS~ is low, a read or a write operation is executed. The address strobe can stay low for multiple clock periods. Address strobe cannot stay high with CS~ low for multiple clock periods.

1.10 Pin Definitions

W/R~ Write/Read Control 95 CMOS/TTL I If this pin is low when CS~ is low, the following

cycle is a read operation. If this signal is high when CS~ is low, the data presented at the end of the following clock cycle will be written if CS~ is still low on that cycle.

OE~ Output Enable 92 CMOS/TTL I This signal must be low to enable the data

Microprocessor Interface

DL_INT FEAC/HDLC

Interrupt

STAT_INT Status/Counter

Interrupt

D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15]

Processor Data Bus

63 CMOS/TTL O Active-low data link channel interrupt output

64 CMOS/TTL O Active-low status/counter interrupt with open

CMOS/TTL

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

output for a read cycle. Data bus outputs are three-stated if this signal is high. The data is valid between clock edges on a read cycle when this pin is low. This pin may be connected directly to ground, if desired.

with open drain.

drain.

This signal is a 16-bit bidirectional data bus for read and write data.

100046C Conexant 1-23

Page 34

1.0 Product Description CN8223

1.10 Pin Definitions ATM Transmitter/Receiver with UTOPIA Interface

Table 1-2. Hardware Signal Definitions (5 of 5)

Pin Label Signal Name No. Type I/O Definition

A[1] A[2] A[3] A[4] A[5] A[6] A[7]

Microprocessor Interface

8KCKI 8 kHz Reference

ONESECI One-Second Clock

RCV_HLD Receiver Hold

NTEST Test Input 59 CMOS/TTL I Connect to Vcc for normal operation.

TEST1 TEST3

Clock and Control

RESET Reset 118 CMOS/TTL I Active-high pulse on power-up for at least

ONESECO One-Second

Address Bus 85

62 CMOS/TTL I Used to synchronize PLCP, and drive ONESECO.

Clock Input

61 CMOS/TTL I 1 Hz input used to latch line status every one

Sync

123 CMOS/TTL I If asserted, this pin stops the cell receiver.

Input

Test I n p u ts 1 1 7

119

60 CMOS/TTL O One-second count derived from count of 8 kHz

Output

CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL

CMOS/TTL CMOS/TTL

Seven-bit address input for addressing registers

within the chip. Addresses are loaded when AS~

is low. I I I I

second.

IIConnect to ground for normal operation.

100 ns. This pin resets the internal state

machines. It does not affect the contents of the

registers, except bit 9 of register 0x02.

input.

VCC Supply Voltage 14

GND Ground 1

Supply Voltage

27 40 54 67

80 107 120 134 147 160

93 106 121 133 146

CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL

CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL CMOS/TTL

—

Eleven pins are provided for supply voltage.

— — — — — — — — — —

—

Twelve pins are provided for ground.

— — — — — — — — — — —

1-24 Conexant 100046C

Page 35

2.0 Functional Description

This chapter describes the CN8223 architecture and functional blocks. Figure 2-1 and Figure 2-2 illustrates detailed signal paths of the receiver and transmitter.

Figure 2-1. CN8223 Receiver Block Diagram

Clock, Sync, Serial Data

Serial Bipolar Data

Serial NRZ Data

Parallel Input Octet, Clock

MUX

Enable

B3ZS/HDB3

DS-3/G.751

E3 Framer

STS-1/

STS-3c/

G.832

STM-1

Serial/Parallel

100 Mbps

TAXI Interface

External

Framer

Figure 2-2. CN8223 Transmitter Block Diagram

Mode

MUX

STS-1/

STS-3c/

STM-1

G.832

Framer

Serial/

Parallel

Octets

MUX

PHY

Mode

Overhead Output

PLCP

Framer

HEC

Align.

Framer

MUX

Alignment

Mode

AT M

Cell

Receiver

8223_013

AT M

Cell

Gen.

Overhead Input

PLCP

Gen.

STS-1/

STS-3c/

STM-1 G.832

Gen.

DS3/

G.751 E3

Gen.

MUX

B3ZS/ HDB3

Encode

Serial/

Parallel

Data Out

MUX

8223_014

100046C Conexant 2-1

Page 36

2.0 Functional Description CN8223

2.1 Microprocessor Interface ATM Transmitter/Receiver with UTOPIA Interface

2.1 Microprocessor Interface

All control and status functions are provided via a direct microprocessor interface. Address maps for the microprocessor are given in Chapter 3.0. There are two types of address spaces:

• Read and write control registers

• Read-only status registers and counters

Write operations are fully decoded. Write operations to undefined addresses have no effect. Read operations from undefined addresses have undefined results.

The microprocessor interface to the CN8223 consists of 31 pins (detailed in

Table 1 -2 ). The CN8223 connects to the microprocessor as if it were clocked

RAM memory. For timing diagram details, see Section 4.3.1.

2.1.1 8/16-Bit Interface

2.1.2 Interrupts

The CN8223 supports an 8-bit or 16-bit microprocessor interface. To select the 8-bit data bus, connect the SEL8BIT pin to VCC. This configures all control and status registers in the part for byte-wide operation. Byte addressing is accomplished by using the D15 pin as the byte high/low select. When D15 is low, the low byte of the addressed register is read or written, and the high byte is unaffected. When D15 is high, the high byte of the addressed register is read or written, and the low byte is unaffected. When reading register locations, the high byte of the addressed location is internally latched so that it can be read in the next operation. Therefore, the low byte of a word address should be read first, then the high byte, to prevent loss of data. When SEL8BIT is low, the interface is configured with a 16-bit bus.

The CN8223 is designed for an interrupt-driven environment. After initialization, status events, error events, and counter overflows generate interrupts that run appropriate interrupt service routines.

Two active-low interrupt pins are provided for the microprocessor interface. STAT_INT provides interrupts for all status and error conditions. DL_INT provides interrupts for the Far End Alarm Control (FEAC) channel contained in the internal DS3 framer and for the internal High-Level Data Link Control (HDLC) formatter used for various data links. Both interrupt pins are configured as open drain to facilitate external wire-OR connections.

Each interrupt source has a bit in an interrupt enable register and in an interrupt status register. This allows the microprocessor to control which conditions cause interrupts and to determine the source of the interrupt. The status registers are described in Chapter 3.0.

NOTE: Receiver interrupts will not function if the receive clock is not active. For

example, if losing the signal to the line interface causes the receive clock recovery circuit to be disabled, the CN8223 will not respond to an LOS interrupt.

2-2 Conexant 100046C

Page 37

CN8223 2.0 Functional Description

ATM Transmitter/Receiver with UTOPIA Interface

2.2 Line Framers

This section describes the operation and control of the internal framers for DS3, E3 (both G.751 and G.832), E4 (G.832), STS-1, and STS-3c/STM-1 formatted serial streams. The transmit and receive serial interfaces can operate at up to 155 MHz. Detailed timing information for the line interface is given in

Chapter 4.0.

The framer receive circuitry recovers the frame location from the serial stream and provides cell octets to the HEC/PLCP cell alignment block. All alarm and error conditions are monitored and reported in status registers and event counters.

The framer transmit circuitry receives cell octets from the HEC/PLCP cell alignment block and adds line framing overhead information. All alarm and error conditions can be generated from control registers.

External interfaces to this block and the interface to the rest of the CN8223 are illustrated in Ta bl e 1- 2. The CN8223 line mode is set for both transmit and receive in the CONFIG_1 register [0x00]. Table 2- 1 lists the valid line modes set by CONFIG_1.

2.2 Line Framers

Table 2-1. Valid CONFIG_1 Line Mode Settings, Bits 7–0

Type of Line Input Signal

DS1 0 0 0 1 0 0 or 1

DS1 (externally gapped 192 bits/frame) 0 1 0 1 0 0

E1 1 0 0 1 0 0 or 1

E1 (externally gapped TS0 and TS16) 1 1 0 1 0 0

DS3, internal framer 2 0 0 or 1 0 0 0 or 1

DS3, external framer 2 0 0 1 0 0 or 1

DS3, external framer (gapped 84/85 bits) 2 1 0 1 0 0

E3, internal G.751 format 3 0 0 or 1 0 0 0

E3, external G.751 format 3 0 0 1 0 0

E3, external G.751 format (gapped first 16 bits)

E3, internal G.832 format 4 x 0 or 1 0 0 1

E4, internal G.832 format 5 x 1 0 0 1

PHY Type

31 0100

Unframed

Input

Disable

B3ZS/

HDB3

External

Framer

Enable

Parallel

Interface

Enable

HEC

Align

STS-1, internal framer 6 x 0 or 1 0 0 1

STS-3c/STM-1, internal framer 7 x 1 0 0 1

Parallel or TAXI interface, 53 octet cells 0 x 0 1 1 1

NOTE(S): x = Don’t Care.

100046C Conexant 2-3

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2.0 Functional Description CN8223

2.2 Line Framers ATM Transmitter/Receiver with UTOPIA Interface

2.2.1 Internally Framed Transmit Line Interface

In internal framer mode, the transmitter provides positive and negative pulse indications and a transmit output clock to an external Line Interface Unit (LIU) (or output clock and NRZ serial data if internal B3ZS/HDB3 encoding is disabled) in response to a transmit input clock.

Table 2 -2 gives the internal framing mode interface connections. The

functional timing for the transmit line interface is similar for all internal framer modes. Figure 2-3 illustrates the interface timing when the internal B3ZS/HDB3 encoder is enabled. The TCLKO phase shown can be inverted with Invert TX Clock Output [bit 7] of the CONFIG_3 register [0x02].

Table 2-2. Internal Framer Transmitter Interface Connections

Signal Name Connect to CN8223 Pin

Transmit Clock Input (TXCKI) TXCKI

Transmit Clock Output (TCLKO) TCLKO

Transmit Positive Data (TXPOS) TXOUT[1]

Transmit Negative Data (TXNEG) TXOUT[2]

Figure 2-3. Internal Framer Transmitter Interface Timing with Line Encoding

TCLKO

TXPOS

TXNEG

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ATM Transmitter/Receiver with UTOPIA Interface

2.2.1.1 High-Speed

PECL Transmit Interface

Figure 2-4. Internal Framer Transmitter Interface Timing Without Line Encoding

For STS-3c, STM-1, or E4, the high-speed PECL interface is used. This mode is used in any case where an external LIU/decoder is used (such as E4 and STS-3c/STM-1 CMI decoding). If the mode is set to E4 or STS-3c/STM-1 in CONFIG_1, then the outputs are taken from the “HS±” versions of the output pins. The TCLKO (and TCLKO_HS±) phase shown can be inverted with the Invert TX Clock Output control bit.

Table 2 -3 lists the interface connections for the internal framing mode without

line encoding. Figure 2-4 illustrates the interface timing when the internal B3ZS/HDB3 encoder is disabled.

Table 2-3. Internal Framing Unencoded Transmitter Connections (STS-3c, STM-1, E4)

Signal Name Connect to CN8223 Pin

Transmit Clock Input (TXCKI) TXCKI_HS±

Transmit Data (TXDATO) TXOUT_HS±

Transmit Clock Output (TCLKO) TCLKO_HS±

2.2 Line Framers

TCLKO

TXDATO

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2.0 Functional Description CN8223

2.2 Line Framers ATM Transmitter/Receiver with UTOPIA Interface

2.2.2 Internally Framed Receive Line Interface

In internal framer mode, the receiver inputs are positive and negative pulse indications, and the receive clock (and NRZ serial data if internal B3ZS/HDB3 decoding is disabled) comes from an external LIU.

Table 2 -4 lists the interface connections for all of the internal framing modes.

The functional timing for the receive line interface is similar for all internal framer modes. Figure 2-5 illustrates the interface timing when the internal B3ZS/HDB3 decoder is enabled. The RXPOS and RXNEG inputs are sampled on the falling edge of the RXCKI clock input. Data inputs can be sampled on the rising edge of the input clock by setting Invert RX Clock Sampling [bit 8] in register CONFIG_3 [0x02].

Table 2-4. Internal Framer Receiver Interface Connections

Signal Name Connect to CN8223 Pin

Receive Clock Input (RXCKI) RXCKI

Receive Positive Data (RXPOS) RXIN[1]

Receive Negative Data (RXNEG) RXIN[2]

Receive Loss of Signal (RXLOS~~) RXIN[4]

Figure 2-5. Internal Framer Receiver Interface Timing

RXCKI

RXPOS

RXNEG

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ATM Transmitter/Receiver with UTOPIA Interface

2.2.2.1 High-Speed

PECL Receive Interface

Figure 2-6. Timing for Internal Framer Receiver, Encoder Disabled

RXCKI

STS-3c, STM-1 and E4 use the high-speed PECL interface. This mode is used in any case where an external LIU/decoder is used (such as E4 and STS-3c/STM-1 CMI decoding). If the mode is set to E4 or STS-3c/STM-1 in CONFIG_1, then the inputs are taken from the “HS sampled on the falling edge of RXCKI. RXDATI can be sampled on the rising edge of the input clock by setting the Invert RX Clock Sampling bit. Tab le 2 -5 lists the connections for internal framer Rx with the encoder disabled; Figure 2-6 illustrates the timing with the coder disabled.

Table 2-5. Connections for Internal Framer Rx, Encoder Disabled (STS-3c, STM-1, E4)

Signal Name Connect to CN8223 Pin

Receive Clock Input (RXCKI) RXCKI or RXCKI_HS±

Receive Data (RXDATI) RXIN[0] or RXIN_HS±

Receive Loss of Signal (RXLOS~) RXIN[4]

2.2 Line Framers

±” versions of the input pins. RXDATI input is

RXDATI

2.2.2.2 Receiver

Framing Operation

8223_018

Five modes are provided for receiver framing operation: DS3, G.751 E3, G.832 E3/E4, STS-1, and STS-3c/STM-1.

In DS3 mode, a parallel-search framing circuit recovers the subframe and M-frame alignments in the DS3 signal. Framing is initiated by an out-of-frame condition as determined by the receiver frame bit-check circuitry. When 3 out of 16 consecutive subframing (F) bits are in error or when 2 out of 3 consecutive M-frames have M bit errors, an out-of-frame condition is declared.

In G.751 E3 mode, a serial search for the 10-bit FAS pattern (1111 0100 00) is conducted. When three consecutive correct patterns are found, the receiver is declared to be in frame. An out-of-frame condition is declared when four consecutive incorrect FAS patterns are detected.

In G.804 E3/E4 and STS-1/STS-3c/STM-1 modes, an octet alignment by the serial-to-parallel conversion circuit is found in conjunction with an octet search for the SONET A1/A2 framing pattern (which is the same pattern as, but not related to, the PLCP A1/A2 bytes). When two consecutive good patterns are found, the receiver is declared to be in frame. An out-of-frame (OOF) condition is declared when four consecutive incorrect A1/A2 patterns are detected.

In STS-3c/STM-1 mode, an octet alignment by the serial-to-parallel conversion circuit is found in conjunction with an octet search for the third A1 and the first A2 octets.

In STS-1 Mode, if STS-1 Stuffing Option [bit 15] in CONFIG_1 [0x00] is set, then columns 30 and 59 in the payload envelope are stuff columns, and these octets will not be interpreted as ATM cell octets. If this bit is not set, then all 86 columns of the SPE will be interpreted as ATM cell octets.

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2.2 Line Framers ATM Transmitter/Receiver with UTOPIA Interface

2.2.3 Externally Framed Transmit Line Interface

In external framer mode, the transmitter inputs are a clock and a synchronization signal that indicate the position of framing bits in the DS1, E1, DS3, or E3 framing signal. The transmit data stream output is a single serial output. The synchronization signal period can be any multiple of the frame period.

Functional timing for the transmit line interface is similar for all external framer modes. These interfaces are compatible with Conexant framers Bt8360 for DS1, Bt8510 for E1, Bt8370 for E1/T1, and Bt8330B for DS3 and E3. Interface connections for these serial, external framing modes are given in Table 2-6.

Table 2-6. Serial External Framer Transmitter Interface Connection

Signal Name Connect to CN8223 Pin

Transmit Clock Input (TXCKI) TXCKI

Transmit Sync Input (TXSYI) TXIN

Transmit Data Output (TXDATO) TXOUT[3]

Figure 2-7 illustrates the transmit timing for the DS1 interface. TXCKI is

1.544 MHz. TXSYI has a rising edge prior to the sampling of the frame bit. This signal does not have to be present at every frame; in particular, it can be a superframe synchronization signal with a period of 3 ms. TXDATO is the output signal; it transitions in response to the rising edge of TXCKI and can be sampled on the following falling edge. The framing bit position content in the output stream is undefined.

Figure 2-7. DS1 Interface Transmit Timing

TXCKI

TXSYI

TXDATO

78S2345678FS234567

Channel 24 Channel 1

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ATM Transmitter/Receiver with UTOPIA Interface

Figure 2-8 illustrates the transmit timing for the E1 interface. TXCKI is

2.048 MHz. TXSYI has a rising edge prior to the sampling of the first bit of time slot 0. This signal can be present every 2 ms. TXDATO is the output signal; it transitions in response to the rising edge of TXCKI, and can be sampled on the following falling edge. The content of time slot 0 and time slot 16 of the output is undefined.

Figure 2-8. E1 Interface Transmit Timing

TXCKI

TXSYI

TXDATO

78S 23 4 5 6781 2 3 45 678

2.2 Line Framers

Time Slot 31

Time Slot 0

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2.2 Line Framers ATM Transmitter/Receiver with UTOPIA Interface

Figure 2-9 illustrates the transmit timing for the DS3 interface. TXCKI has a

frequency of 44.736 MHz. TXSYI (active low) is sampled on falling clock transitions, and TXDATO changes on falling clock edges. TXSYI has a rising edge after the sampling of the overhead bit (once every 85 bits). TXDATO is the output signal; it transitions in response to the falling edge of TXCKI, and can be sampled on the following falling edge. This timing is compatible with the Conexant Bt8330B DS3/E3 framer, using the TXOVH output of that circuit to synchronize the CN8223 input. The content of the frame bit position is undefined.

Figure 2-9. DS3 Interface Transmit Timing

TXCKI

TXSYI

TXDATO

Information Field

Frame Bit Position

Information Field

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ATM Transmitter/Receiver with UTOPIA Interface

Figure 2-10 illustrates the transmit timing for the E3 interface. TXCKI has a

frequency of 34.368 MHz. TXSYI has a rising edge after the sampling of the last bit of the frame alignment signal. TXDATO is the output signal; it transitions in response to the falling edge of TXCKI, and can be sampled on the following falling edge. This timing is compatible with the Conexant Bt8330B DS3/E3 framer using the TXOVH output. The frame alignment signal position is filled with the value 0xCCCC. This value provides the four overhead bits (required by ETSI prETS 300 214) that follow the frame alignment signal defined by ITU G.751.

Figure 2-10. E3 Interface Transmit Timing

TXCKI

TXSYI

2.2 Line Framers

TXDATO

Frame Alignment Signal Position

XXXXXXXXX

2.2.4 Externally Framed Receive Line Interface

The CN8223 external receive line interface has three inputs: clock, data, and frame sync. Frame sync can be a multiple of the frame period. Table 2-7 lists the receiver connections for all external framing modes. The receive line inputs consist of the receive clock (RXCKI), the receive sync input (RXSYI), and the receive data input (RXDATI) when the external framer mode is selected.

Table 2-7. External Framing Mode Receiver Connections

Signal Name Connect to CN8223 Pin

Receive Clock Input (RXCKI) RXCKI

Receive Sync Input (RXSYI) RXIN[3]

Receive Data Input (RXDATI) RXIN[0]

X1100

Information Field

8223_022

Receive Loss of Signal (RXLOS~) RXIN[4]

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2.0 Functional Description CN8223

2.2 Line Framers ATM Transmitter/Receiver with UTOPIA Interface

The input timings are all similar: RXDATI and RXSYI are sampled on the falling edge of the input clock; and the low-to-high transition of the sync signal occurs during the interval of the frame bit for DS1 and DS3, with the first bit of time slot 0 for E1, and the first bit of the frame-alignment signal for E3. For brevity, only the DS1 timing is illustrated (Figure 2-11). The timing on this interface is similar to the timing on the transmit interface. It is compatible with Conexant framers. The data and sync inputs can be sampled on the rising edge of the input clock by setting Invert RX Clock Sampling [bit 8] of CONFIG_3 [0x02].

In all framed, serial line formats, the content of the framing bit positions is ignored. RXSYI does not need to be present every frame; it can be applied at any submultiple of the frame rate (e.g., once every ESF superframe for DS1).

Figure 2-11. Receiver DS1 Line Interface Timing

RXCKI

RXSYI

RXDATI

Channel 24

65432S 765432SF87

Channel 1

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2.3 Overhead Generation

The CN8223 automatically receives and generates line overhead. For additional flexibility, line overhead can be monitored and inserted for STS-3c, STM-1, and G.832 E3/E4 modes.

2.3.1 Internal DS3 Mode

The transmitter circuitry automatically generates all F and M framing bits. The transmitter calculates the parity of each M-frame and inserts this data into bits P1 and P2 of the following M-frame. Bits X1 and X2 contain 1s unless Transmit Alarm Control [bit 6] of CONFIG_2 [0x01] is set. If this bit is set, bits X1 and X2 contain 0s. All C bit positions are generated automatically by the transmitter. Overhead generation of DS3 values is summarized in Tabl e 2- 8.

Table 2-8. DS3 Overhead Values

Overhead Bits CN8223 Operation

2.3 Overhead Generation

X1, X2 Yellow alarm bits set from CONFIG_2, bit 6.

P1, P2 Calculates and inserts frame parity. No error insertion.

M123 Internally generated 010 pattern. No error insertion.

F1234 Internally generated 1001 pattern. No error insertion.

C1 Subframe 1 Application ID channel. Internally generated as all 1s.

C2 Subframe 1 Network requirement bit. Internally generated as all 1s.

C3 Subframe 1 FEAC channel. Internally generated under processor control.

C123 Subframe 2 Unused. Internally generated as all 1s.

C123 Subframe 3 Path parity. Same value inserted as P1, P2 in all 3 bits. No error insertion.

C123 Subframe 4 FEBE indication. Internally generated as all 1s. If receiver detects a path parity, or M123 or F1234 error,

then non-111 code is inserted for one frame.

C123 Subframe 5 Terminal data link. Data or all 1s from internal HDLC formatter when enabled.

C123 Subframes 6, 7 Internally generated as all 1s.

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2.3 Overhead Generation ATM Transmitter/Receiver with UTOPIA Interface

2.3.2 Internal G.832 E3/E4 Modes

All framing overhead is generated automatically and the BIP octet is calculated and inserted in the EM position. The BIP field can be errored using the TXFEAC_ERRPAT register [0x03] and BIP Error Insert [bits 12–10 of CONFIG_2 [0x01]. All undefined overhead octets are inserted externally as described in Section 2.3.5, and individual overhead octets can be disabled (set to all 0s) using Overhead Control [bits 3–0] of CONFIG_2 [0x01]. Internally generated octets are FA1, FA2, EM, and MA. Overhead generation of G.832 E3 and E4 values is summarized in Table 2 -9 .

Table 2-9. G.832 E3 and E4 Overhead Values

Overhead Bits CN8223 Operation

FA1/FA2 Inserts standard values (0xF6, 0x28) or can be inserted externally through port TXOVH[7:0]. If this

bit is disabled, the value is 0x00.

EM Calculates and inserts BIP8. Errors can be inserted using the TXFEAC_ERRPAT register. Allows

single error insertion or all 0 value (continuous error).

TR Always inserted through port TXOVH[7:0].

MA Calculates and inserts line FEBE based on incoming EM errors. Can be set for FEBE = all 1s or all 0s.

Inserts FERF and timing marker from register. Can be disabled to all-0s or inserted from TXOVH[7:0].

NR Always inserted through port TXOVH[7:0].

GC Inserted externally through port TXOVH[7:0] or from internal HDLC formatter, if enabled.

P1 E4 mode only. Always inserted through port TXOVH[7:0].

P2 E4 mode only. Always inserted through port TXOVH[7:0].

2.3.3 Internal G.751 E3 Mode

The FAS pattern is automatically generated by the transmitter circuitry. The transmitter also inserts the A bit as determined from Transmit Alarm Control [bit 6] of CONFIG_2 [0x01]. Overhead generation of G.751 E3 values is summarized in Tab l e 2- 10.

Table 2-10. G.751 E3 Overhead Values

Overhead Bits CN8223 Operation

FAS 10-bit pattern internally generated—1111010000. No error

insertion.

A Alarm bit set from CONFIG_2, bit 6.

N Data or all 1s from internal HDLC formatter when enabled.

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2.3.4 STS-1 and STS-3c/STM-1 Modes

All framing overhead is generated automatically and all BIP overhead is calculated and inserted in the proper positions. BIP fields can be errored using the TXFEAC_ERRPAT register [0x03] and BIP Error Insert [bits 12–10] of CONFIG_2 [0x01]. Groups of overhead octets can be disabled (set to all 0s) using Overhead Control [bits 3–0] of CONFIG_2. Internally generated octets are A1, A2, C1, B1, B3, C2, H1, H2, H3, G1, B2, K2, H4, and M1.

In STS-1 mode, if STS-1 Stuffing Option [bit 15] in CONFIG_1 [0x00] is set, then columns 30 and 59 in the payload envelope are stuffed with all 0s and are not available for ATM cell octet transport (resulting in a total of 84 columns available for transport). If this bit is not set, then all 86 columns of the SPE are available for ATM cell octets.

The C1 octet can be programmed to be obtained from the TXOVH bus by setting Enable External Section Trace [bit 1] of CONFIG_4 [0x29]. The C1 values generated are listed in order of precedence in Tab le 2 -1 1.

Table 2-11. C1 Values

Mode Control Bit C1 Octet Value

Disable C1 Config_2[0] 00

2.3 Overhead Generation

Enable External Config_4[1] From TXOVH Bus

STS-1 Mode Config_1[2:0] 01

STS-3c/STM-1 Mode Config_1[2:0] 01,02,03

The pointer value generated in SONET/SDH modes is controlled by STM-1/STS-3c Pointer [bit 0] in the CONFIG_4 register [0x29]. This bit should be set low for STS-1 operation. When this bit is low, the H1/H2 pointer value is fixed at 0x620A. When this bit is set high (for STM-1 operation), the AU-4 pointer value is fixed at 0x6A0A (SS bits = 10). Overhead generation of STS-1, STS-3c, and STM-1 values is summarized in Table 2 -1 2.

Table 2-12. STS-1, STS-3c, and STM-1 Overhead Values (1 of 2)

Overhead Byte CN8223 Operation

A1, A2 Inserts standard values (0xF6, 0x28) or may be inserted externally through port TXOVH[7:0]. If this

bit is disabled, the value is 0x00.

C1 Internally generated (0x00 if disabled; 0x01 in STS-1 mode; 0x01, 0x02, and 0x03 in STS-3c mode).

Can be externally inserted through port TXOVH[7:0].

B1 Calculates and inserts B1. Errors can be inserted using the TXFEAC_ERRPAT register. Allows single

error insertion or all-zero value (continuous error).

E1 Always inserted through port TXOVH[7:0].

F1 Always inserted through port TXOVH[7:0].

D1–D3 Inserted externally through port TXOVH[7:0] or from internal HDLC formatter, if enabled.

H1, H2, H3 Internally generated. The H1 values are 0x62 in STS-3c mode and 0x6A in STM-1 mode. The H2

value is 0x0A in both STS-3c and STM-1 modes. The H3 value is 0x00. If overhead insertion is disabled, all values are 0x00.

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2.3 Overhead Generation ATM Transmitter/Receiver with UTOPIA Interface

Table 2-12. STS-1, STS-3c, and STM-1 Overhead Values (2 of 2)

Overhead Byte CN8223 Operation

H4 This byte is no longer used by the CN8223. Its value is insignificant. H4 is the number of octets

between the H4 octet position and the next cell starting position in the payload and thus has a value ranging from 0 to 52. Its value will change in each frame because the payload does not hold an integral number of cells. This used to be the mechanism to locate cell boundaries but is no longer used since the HEC alignment technique was developed. Thus, the value in this position does not really matter. The CN8223 transmitter still generates this value but the receiver does not pay attention to it.

B2 Calculates and inserts B2. Errors can be inserted using the TXFEAC_ERRPAT register. Allows single

error insertion or all-zero value (continuous error).

K1, K2 The K1 and K2 (FERF) values are internally generated through register 0x32. They can also be

inserted externally through port TXOVH[7:0].

D4–D12 Always inserted through port TXOVH[7:0].

Z1 Always inserted through port TXOVH[7:0].

M1 Calculates and inserts line FEBE, based on incoming B2 errors. Can be set for FEBE = all 1s or all 0s.

E2 Always inserted through port TXOVH[7:0].

J1 Always inserted through port TXOVH[7:0].

B3 Calculates and inserts B3. Errors can be inserted using the TXFEAC_ERRPAT register. Allows single

error insertion or all-zero value (continuous error).

C2 Three options:

• If disabled, value = 0x00

• Can be internally generated (0x13)

• Can be externally inserted through port TXOVH[7:0]

G1 Calculates and inserts path FEBE (or all 1s or all 0s). Inserts path RDI and qualifier (path yellow). If

disabled, inserts value of 0x00.

F2 Always inserted through port TXOVH[7:0].

Z3, Z4 Always inserted through port TXOVH[7:0].

Z5 Always inserted through port TXOVH[7:0].

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2.3.5 Transmit Framing Overhead Interface

An octet interface is available for external insertion of certain framing overhead in STS-1/STS-3c/STM-1 and G.832 E3/E4 framing modes. The interface consists of an output clock on TOVH_CLK, an output marker on TMRKR, and an 8-bit input bus for overhead octets.

Figure 2-12.

There is a clock pulse on the TOVH_CLK output for each overhead octet that appears in the framing format and that is provided on the bus input. The bus input is sampled on the falling edge of the TOVH_CLK signal. TMRKR is high on a particular octet in each mode to synchronize external circuitry.

Figure 2-12. Transmit Framing Overhead Interface Timing

TOVH_CLK

TMRKR

The timing for this interface is

2.3 Overhead Generation

illustrated

TXOVH[7:0]

All overhead octets can be provided by external insertion if Enable External Overhead [bit 15] in CONFIG_2 [0x01] is set. If this bit is not set, only octets that are not internally generated are obtained from the external interface.

Section 2.3.1, Section 2.3.2, Section 2.3.3, and Section 2.3.4 describe internally

generated octets.

In STS-1 mode, there are four clock pulses on TOVH_CLK for each row in the framing format (a total of 36 clock pulses per frame). The Synchronous Payload Envelope (SPE) starts immediately after the row 1 overhead (the J1 octet follows the C1 octet). TMRKR is high during row 1 of the framing format (octets A1, A2, C1, J1). STS-3c/STM-1 mode has the same format except there are 10 clock pulses for each row for a total of 90 clock pulses per frame.

In STS-1/STS-3c/STM-1 modes, the content of octets D1, D2, and D3 is from the internal HDLC formatter, if enabled. These octets can also be provided via the TXOVH[7:0] input.

In G.832 E3 mode, there is a total of 7 clock pulses per frame and TMRKR is high during the FA1 and FA2 octets. In G.832 E4 mode, there is a total of 16 clock pulses per frame, and TMRKR is again high during the FA1 and FA2 octets. The TXOVH[7:0] inputs should be connected to ground if all 0s octet data is desired for octets that are not internally generated.

A1 A2 C1 J1

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2.3 Overhead Generation ATM Transmitter/Receiver with UTOPIA Interface

2.3.6 Receive Framing Overhead Interface

An octet interface is available for external observation of all framing overhead in STS-1/STS-3c/STM-1 and G.832 E3/E4 framing modes. The interface consists of two output clocks on ROVH_CLK[1,0], two output markers on RMRKR[1,0], and an 8-bit output bus RXOVH[7:0]. Timing for this interface is illustrated in

Figure 2-13. There is a clock pulse on the ROVH_CLK[1] output for each section

and line overhead octet in STS-1 and STS-3c/STM-1 modes and for all overhead octets in G.832 E3 and E4 modes. There is a clock pulse on the ROVH_CLK[0] output for each path overhead octet in STS-1 and STS-3c/STM-1 modes.

The RMRKR[1,0] outputs and the bus output are set up prior to the rising edge of the clocks and can be sampled externally on the rising edge of ROVH_CLK[1,0]. The RMRKR[1] output is high during row 1 overhead in all modes (A1, A2, and C1 in STS-1/STS-3c/STM-1 modes and FA1, FA2 in G.832 E3/E4 modes). The RMRKR[0] output is high during row 1 path overhead (octet J1) in STS-1 and STS-3c/STM-1 modes. There are two marker and clock outputs for STS-1 and STS-3c/STM-1 modes because the SONET frame and payload envelopes can be offset from each other.

Mode Overhead Octets Output per Frame STS-1 STS-3c/STM-1 G.832 E3 G.832 E4

36 90

In STS-1/STS-3c/STM-1 modes, the contents of octets D1, D2, and D3 are provided to the internal HDLC receiver. The GC octets of the E3 and E4 formats are also provided to the HDLC receiver. Terminal data link bits in DS3 mode (C bits of subframe 5) and the N-bit in G.751 E3 mode are also provided to the HDLC receiver.

Figure 2-13. Receive Framing Overhead Interface Timing

ROVH_CLK[1]

RMRKR[1]

ROVH_CLK[0]

RMRKR[0]

RXOVH[7:0]

A1 A2 C1

8223_025

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2.4 Status and Alarms

The CN8223 automatically receives and generates alarms.

2.4.1 Status and Counter Interrupts

The status interrupt pin STAT_INT can be programmed to provide an interrupt on any occurrence in the LINE_STATUS register [0x38]. Each of these signals generates a receive status interrupt if the corresponding interrupt is enabled in the EN_LINE_INT register [0x2D]. To determine if an interrupt is caused by a PHY status event, the LINE_STATUS register is read. This clears the interrupts in that register.

Two types of interrupts are provided: error and alarm. Error signals cause an interrupt on each occurrence of an error condition. Error signals are bits 9–13 in the LINE_STATUS register. Alarm signals provide an interrupt on change of state. All other indications in LINE_STATUS are alarm indications.

Interrupt status bits for the line/PHY counter overflows are located in the OVFL_STATUS register [0x3A]. The enables for these interrupts are in EN_OVFL_INT [0x2F]. All counters are 16 bits. If a counter is set to interrupt, it rolls over to zero when it exceeds its maximum value. If a counter is not set to interrupt, it saturates at its maximum value of 65,535 and ignores further events. To determine if an interrupt has been caused by a counter, the microprocessor reads the OVFL_STATUS register.

If the interrupt for a particular counter is not set, the counter saturates at a value of 65,535 and stays at that value until read. If Enable One-Second Latching of Line Counters [bit 13 in CONFIG_1 [0x00] is set, then at each one-second interval defined by the input ONESECI, the current counter value is latched for the following one-second interval, and the counter is cleared. If the counter is again read in that one-second interval, the current value of the counter is read and then cleared.

The LCV counter [0x40] is always latched (and the counter cleared) by the ONESECI input regardless of the setting of Enable One-Second Latching of Line Counters. When this counter is read, the latched value is presented and then cleared. Subsequent reads prior to the next ONESECI latching event produce a value of zero.

2.4 Status and Alarms

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2.4 Status and Alarms ATM Transmitter/Receiver with UTOPIA Interface

2.4.2 Alarm Signal Generation

Three alarm signals can be generated by the transmitter in DS3 mode. These alarms are generated by setting Transmit Alarm Control [bits 6–4] of the CONFIG_2 register [0x01]. The yellow alarm is contained in the X1 and X2 bits. DS3 AIS has the highest priority, followed by idle code, and finally yellow alarm.

DS3 FEBE alarms are generated automatically in the transmitter when the receiver detects either a frame bit error or a C-parity error in an M-frame. When no alarm condition is present, the FEBE channel contains all-1s. When an alarm is to be sent (as determined by the receiver) the FEBE channel is set to all 0s for one M-frame for each error occurrence.

In G.751 E3 mode, transmission of AIS (unframed all 1s) is enabled by setting Transmit Alarm Control [bit 4] high. Transmission of yellow alarm is enabled by setting Transmit Alarm Control [bit 6] high. This causes the transmitted A-bit to be set to one.

In G.832 E3/E4 modes, transmission of AIS or the MA FERF indication is enabled by setting Transmit Alarm Control [bits 4 or 5], respectively. The MA timing marker bit can be set by setting Transmit Alarm Control [bit 6].

In STS-1 and STS-3c/STM-1 modes, transmission of line Alarm Indication Signal (AIS), Line Far End Receive Failure (FERF), and various path indications can be enabled as described in Section 3.3.

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2.4 Status and Alarms

2.4.3 Alarm Detection

The internal framers contain status indicators to obtain alarm information for link maintenance. Table 2 -1 3 shows the error indications by line mode. This table is repeated as Table 3 -1 7, in Chapter 3.0.

Table 2-13. Status Indications for All Modes (Register 0x38)

Bit

15 Line FEBE Error 0 0 0 0

14 One-Second Count One-Second Count One-Second Count One-Second Count One-Second Count

13 Signal Label

12 Path FERF Error FEBE All 1s MA FERF FEBE All 1s FEBE All 1s

11 Path FEBE Error PLCP FEBE Error MA FEBE PLCP FEBE Error PLCP FEBE Error

10 Summary BIP Error PLCP BIP Error EM BIP Error PLCP BIP Error PLCP BIP Error

9 Line FERF PLCP Frame Error x PLCP Frame Error PLCP Frame Error

8 LOC PLCP Yellow/LOC LOC PLCP Yellow PLCP Yellow

STS-1/STS-3c/

STM-1

Mismatch

Internal DS3 G.832 E3/E4 Internal G.751 E3

Invalid FEBE Payload Type

Mismatch

Invalid FEBE Invalid FEBE

Ext. Framer

(57 octet)

7 STS LOF 2–3 PLCP LOF 2–3 E3/E4 LOF 2–3PLCP LOF 2–3PLCP LOF 2–3

6 STS LOF PLCP LOF E3/E4 LOF PLCP LOF PLCP LOF

5 STS OOF PLCP OOF/LOC E3/E4 OOF PLCP OOF PLCP OOF

4 Path Yellow DS3 X-bit Yellow x E3 A-bit Yellow x

3 Path AIS DS3 Idle Code x x x

2 Line AIS DS3 AIS E3/E4 AIS E3 AIS x

1 STS LOP DS3 OOF x E3 OOF x

0 LOS (Input) LOS (Input) LOS (Input) LOS (Input) LOS (Input)

NOTE(S): “x” means content should be disregarded.

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2.0 Functional Description CN8223

2.5 Parallel Line Interface ATM Transmitter/Receiver with UTOPIA Interface

2.5 Parallel Line Interface

The CN8223 has a parallel line interface consisting of TXOUT[8:0] and RXOUT[8:0]. These octet ports allow interfacing of external framers or other devices that use parallel data. Table 2 -1 , illustrates the architecture of this parallel interface. Also, this interface can be used for the Advanced Micro Devices TAXI interface chipset.

2.5.1 TAXI Interface

The parallel port of the CN8223 can be configured to interface directly with AMD’s TAXI transmit/receive chipset. To enable this mode, set the following values in each of these registers:

CONFIG_1 (0x00): Set the 8 LSBs to 0xE0. CONFIG_3 (0x02): Set Enable HEC Coset (bit 0) and Invert RX Clock

(bit 8) high.

CONFIG_4 (0x29): Set Enable TAXI Interface (bit 3) high.

The transmit interface logic automatically generates the signals needed by the TAXI transmitter to insert JK sync and TT start-of-cell symbols before each transmitted data cell of 53 octets. When no transmit port is active, the transmitter sends continuous JK sync symbols.

The receiver interface logic detects the TT start-of-cell command and synchronizes its cell circuitry to receive and process the 53-octet cell data. The receiver ignores all incoming JK sync signals while awaiting the reception of the TT symbol. The receiver is not clocked on any command or data octet if the violation indication is present on RXIN[8]. None of the indications in the LINE_STATUS register [0x38] are valid in TAXI mode except for One Second Count. Any other indications should be ignored. Violations will be counted in Line Counter 2. All cell status and cell event counters operate as in other modes.

In TAXI mode, the capability to shut down the output of cells to the FIFO interface is lost because of the use of the RCV_HLD pin. In this mode, the control bits in CELL_VAL or external logic using the VLTN signal must be employed for this function.

NOTE: Source and line loopbacks are not functional in TAXI mode due to the

asymmetry between the transmit and receive control lines.

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Timing information for TAXI mode is found in Section 4.3.5. Pin connections for the TAXI chipset and the CN8223 are listed in Table 2-14.

Table 2-14. Pin Connections between TAXI Chipset and CN8223

Signal Name from TAXI Chipset Connect to CN8223 Pin

Receive Clock (CLK) RXCKI

Receive Data (DO 7-0) RXIN[7:0]

Receive Command (CO 1) TXIN

Receive Command Strobe (CSTRB) RCV_HLD

Receive Violation (VLTN) RXIN[8]

Transmit Clock (CLK) TXCKI

Transmit Data (DI 7-0) TXOUT[7:0]

Transmit Command (CI 1) TXOUT[8]

Transmit Command (CI 0,2,3) GND

Transmit Strobe (STRB) TCLKO

2.5 Parallel Line Interface

2.5.2 Transmit Parallel Interface

Interface connections for the Transmit Parallel Interface mode are listed in

Table 2 -1 5. TXOD and TXDELO are mapped to TXIN and TXOUT[8],

respectively. Figure 2-14 illustrates the transmit timing for the parallel interface. TXCKI has a frequency of up to 20 MHz. In parallel mode, the synchronization signal TXOD marks the octet clocks where the CN8223 does not provide a new data octet on the TXDAT output. This could be used for marking all of the overhead (non-ATM payload) octets in a data stream.

Alternatively, TXOD can be held low and a gapped octet clock provided from the external circuitry to the CN8223 on TXCKI. TXDAT is the output signal; it transitions in response to the rising edge of TXCKI, and can be sampled on the following falling edge externally. TXDELO also transitions in response to the rising edge and marks the first octet of each 53-octet cell.

Table 2-15. Transmit Parallel Interface Mode Connections

Transmit Clock Input (TXCKI) TXCKI

Transmit Octet Disable (TXOD) TXIN

Transmit Data Output (TXDAT) TXOUT[7:0]

Transmit Cell Delineation (TXDELO) TXOUT[8]

Signal Name Connect to CN8223 Pin

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2.5 Parallel Line Interface ATM Transmitter/Receiver with UTOPIA Interface

Figure 2-14. Transmit Parallel Interface Timing

TXCKI

TXDAT[7:0]

TXOD

TXDELO

Data Data Data

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2.5.3 Receive Parallel Interface

Interface connections for the Receive Parallel Interface mode are listed in

Table 2 -1 6. Figure 2-15 illustrates the receive timing for the parallel interface. In

parallel mode, data octets are provided on RXDAT[7:0] with an octet clock (up to 20 MHz) on RXCKI. The octet data is sampled on the falling edge of RXCKI. The data inputs can be sampled on the rising edge of the input clock by setting Invert RX Clock Sampling [bit 8] of CONFIG_3 [0x02]. An idle octet indicator can be provided on RXOD as illustrated in Figure 2-15. The CN8223 ignores all octets for which the RXOD input is high. This input can be used to mark framing overhead (non-ATM payload) octets.

Table 2-16. Receive Parallel Interface Mode Connections

Signal Name Connect to CN8223 Pin

Receive Clock Input (RXCKI) RXCKI

Receive Octet Disable (RXOD) RXIN[8]

Receive Data Input (RXDAT) RXIN[7:0]

2.5 Parallel Line Interface

Figure 2-15. Receive Parallel Interface Timing

RXCKI

RXDAT[7:0]

RXOD

Data

(ignored)

Data Data

8223_027

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2.6 ATM Cell Processing ATM Transmitter/Receiver with UTOPIA Interface

2.6 ATM Cell Processing

The ATM cell processing block is located between the line framers and FIFO port blocks of the CN8223 (see Figure 1-3). This functional block interfaces between the octet data and cell data portions of the chip. The CN8223 supports cell delineation via either PLCP or HEC alignment for DS1, E1, DS3, E3, E4, STS-1, and STS-3c/STM-1 rates. At DS3 and E3 rates, all required stuffing functions are supported.

2.6.1 Cell Generation for Transmit

Cell generation refers to the formatting of 53-octet ATM cells from 48- or 52-octet payload data from the FIFO interface for hand-off to the line framer transmitter. The CN8223 provides modes that generate complete cells as well as modes that pass entire 53- or 57-octet cells directly from the FIFO interface. Cell modes and other per-port controls are in the four CELL_GEN_x registers [0x04–0x07].

The generation process operates autonomously with a handshake protocol through the FIFO interface. Cells are forwarded automatically to the line framer for transmission.

When full ATM cell generation is performed, a 5-octet header is generated by the CN8223. The VCI and other fields in the first 4 octets come from microprocessor control registers. The HEC in octet 5 is calculated and inserted by the CN8223. HEC coverage over 4-header octets (ATM) or 3-header octets (SMDS/802.6) is selectable by HEC Coverage [bit 1] of CONFIG_3 [0x02]. The remaining 48 octets are payload and are taken from the FIFO interface. The CN8223 calculates and overwrites the CRC field to complete the 53-octet cell.

A cell-ready indication controls the cell generation process from the external ATM interface circuit to the cell generation block. When the ATM interface indicates that it has the first cell of a message ready, the cell generation block begins formatting a non-idle cell for transmission using the octet data and cell delineation control inputs at the interface. The cell generation circuitry automatically generates idle cells until the external FIFO indicates that another cell is ready for transfer. The header and payload for idle cells are programmable via control registers. When the next cell is ready, the host presents the data and cell delineation control inputs.

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Two rate control registers are provided for control of the port sources to allow programmable rate shaping of cell transmission. The ratio of active to idle cells is programmable with 0.4 % granularity. The cell generation process maintains status counts of non-idle cells transmitted for each of the four sources. Table 2- 17 lists the four cell generation modes provided by the CN8223.

Table 2-17. Cell Generation Modes

Mode Function

48-Octet Mode Provides for full ATM generation. Forty-eight octets are taken from the FIFO interface, the appropriate

header fields are attached, and the payload CRC is overwritten to form the ATM cell.

52-Octet Mode Allows a 53-octet cell, less the HEC octet, to be transferred from the FIFO interface. The HEC is calculated

and inserted by the CN8223. The payload CRC for AAL3/4 can be inserted, or checked and transferred without modification. Both the HEC and the payload CRC can be optionally disabled or errored on a single-event basis. The cell generation process also provides HEC coset generation, ATM payload scrambling. In each of the above modes, any header field can be overwritten with information from control registers.

53-Octet Mode Allows entire 53-octet cells to be transferred from the FIFO interface. This is the mode used when Port 0

is configured for UTOPIA.

57-Octet Mode Allows the input of entire 57-octet PLCP slots from the FIFO interface. Can be used for external PLCP

insertion or test generation purposes.

2.6 ATM Cell Processing

2.6.1.1 CELL_GEN_x Register

Per-port cell generation registers for FIFO Ports 0–3 are in the four CELL_GEN_x registers [0x04–0x07]. Cell Generation Mode [bits 1,0] selects the operating mode for the generation circuit. are provided. In 52-, 53-, or 57-octet modes, the individual header fields obtained from the FIFO interface can be overwritten. This overwriting is accomplished with the values found in the TX_HDR registers for a particular port by setting the appropriate field insertion control bit in the CELL_GEN_x register. In 48-octet mode the header fields always come from the programmed value in the corresponding TX_HDR register.

The overhead fields of active cells are taken from the locations listed in

Table 2 -1 8 or set to the indicated values.

The four modes described in

Tabl e 2-17

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Table 2-18. Overhead Field Locations

Overhead Field Source

Cell Header Header Register TX_HDR or FIFO input

Header Error Control HEC Generation Circuit or FIFO input

Segment Type FIFO Input

Sequence Count FIFO Input

Length Field FIFO Input

Payload CRC Payload CRC Generation Circuit or FIFO Input

Disable HEC [bit 9] and Disable Payload CRC [bit 10] in the CELL_GEN_x registers [0x04–0x07], disable the field generation and allow the existing field to pass. Error HEC [bit 11] and Error Payload CRC [bit 12] force a single error occurrence in the generated field. The Error functions are cleared after the error is generated. This allows the microprocessor to easily generate a specific number of errors. The error pattern programmed in the TXFEAC_ERRPAT register [0x03] is used with the Error HEC control to generate a specific number of HEC errors for checking receiver error correction/detection circuitry.

The Error Payload CRC bit inserts 4-bit errors into the payload CRC field. The Inhibit Single Cell Generation [bit 13] field in CELL_GEN_x, inhibits cell transmission from the port for a single cell interval. A single idle cell (with header contents as defined in the Transmit Idle Header Register [0x0A–0x0B] and payload set to all 0s) is transmitted in place of a data cell from this port at the next cell interval if the priority control tries to obtain a cell from this port. This bit is cleared by the cell generation circuitry after the idle cell has been transmitted or if a cell from another port is selected by the priority control. The microprocessor can poll this bit to determine when the idle cell insertion has been completed.

Idle cells are automatically generated when no transmit port is active. The header for idle cells is obtained from the TX_IDLE_xx registers, and the HEC is automatically calculated. The payload for idle cells is obtained from the IDLE_PAY register [0x2A]. This data octet is inserted in all octet positions of the idle cell payload. The CRC-10 can be inserted if required by setting Disable Payload CRC of CELL_GEN_x to zero.

2.6.1.2 Cell Generation Status and Status

Interrupts for Transmit

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A per-port count of cells transmitted is maintained in the CELL_SENT_CNTx counters [0x4E–0x51] for each port. These counters can be programmed to cause an interrupt in the CELL_STATUS register [0x3B] by setting enable bits in the EN_CELL_INT register 0x30]. The interrupt clears when CELL_STATUS is read. If the counter interrupt is not enabled, the counter stops at its maximum value of 65,535. If the interrupt is enabled, the counter interrupts on “roll over” and continues counting. The counter clears when it is read.

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2.6.2 Cell Validation for Receive

Cell validation refers to the checking of cells coming in from the PHY block for proper format. Modes that deliver 48-, 52- or 53-octet cells, or 57-octet PLCP slots to the FIFO output ports are provided by the CN8223.

Four modes are available for cell output:

• A test mode writes the entire 57-octet PLCP slot to the FIFO interface.

• A 53-octet mode writes the 53-octet ATM cell to the FIFO interface.

• A 52-octet mode writes the ATM cell without the HEC octet to the FIFO

interface.

• A final mode delivers 48-octet cell payloads to the FIFO interface.

When the UTOPIA interface mode is used, only 53-octet output is available.

The protocol verification provided includes HEC validation with ATM or SMDS/802.6 coverage, cell header filter/screen against four maskable 32-bit programmable values, validation of payload length per segment type, and correct payload CRC value. Status reporting on validation steps is via error counters and status register indications. Status bits can be programmed to generate interrupts to the microprocessor. Each validation step can be individually disabled. Cells are routed to one of four output ports if a match to that port’s programmable header value is made.

Each cell is output to the ATM interface after a 6- or 10-octet buffer to allow for header processing. A “cell-valid” output pin is provided to indicate that none of the enabled error checks detected an error. The UTOPIA internal FIFO or external circuitry is notified to discard the cell when the valid indication goes inactive. Idle cells are automatically deleted from the ATM layer output. Parity and control/delineation signals are provided with each octet at the port interface. The microprocessor receives status and error counts as cell validation proceeds.

All event and error counters can be programmed to cause an interrupt on overflow. Reading the interrupt source register allows the microprocessor to identify overflows and update internal counts. All counters can be read by the microprocessor and are cleared when read.

2.6 ATM Cell Processing

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2.6 ATM Cell Processing ATM Transmitter/Receiver with UTOPIA Interface

2.6.2.1 HEC Alignment In 53-octet mode, either the internal framer or the parallel input provides octet

alignment information to the HEC alignment state machine. Each octet position is then searched for correct HEC alignment to determine cell delineation. The HEC alignment framing state machine is given in ITU I.432. Three states are present: hunt, pre-sync, and sync. The hunt state is entered when seven consecutive errored HEC patterns are found at the current alignment location. The pre-sync state is entered when a candidate position contains the correct HEC pattern. The sync state is entered when six consecutive, correct HEC patterns at the candidate location are found.

The HEC state machine can be altered to include state integration by setting the Integrate HEC Framing control bit in CONFIG_5. When this bit is set, the state machine has two additional states: OCD Anomaly and Verification. The OCD Anomaly state is entered when seven consecutive errored HEC patterns are found at the current alignment location. OCD Anomaly status is indicated in bit 10 of CONFIG_5. After an integration time of X ms in the OCD Anomaly state, the LCD defect state is entered. The LCD defect state is indicated in bit 8 of LINE_STATUS [0x38] and on the LOCD output pin. The verification state is entered when six consecutive, correct HEC patterns at the candidate location are found. After x ms in the verification state, the sync state is entered. The value of x is 4 ms for SONET/SDH modes and 2.5 ms for DS3 mode. This integration time is counted from the 8 kHz reference input on the 8KCKI input pin. A rising edge must be present on this input every 125 machine.

µs for proper integration in this state

2.6.2.2 CELL_VAL Control Register

Cell validation refers to the error checking of received cells prior to output to the FIFO interface. It is controlled via the CELL_VAL register [0x14]. Per-port output mode selects 48-, 52-, 53-, or 57-octet modes for each of the four ports. Enable HEC Correction [bit 8] enables the HEC correction mode for single-bit header errors. If this bit is set to zero, then no correction is performed, but error detection is always performed. Error correction must be disabled if HEC Coverage [bit 1] in CONFIG_3 [0x03] is set for SMDS/802.6 mode, or if Enable HEC Coset [bit 0] in CONFIG_3 is not enabled.

Header Only Output [bit 12] in CELL_VAL enables a 5-octet output mode on Port 3. Only the 4 header octets of cells addressed to Port 3 and the status octet in

Table 2 -1 9 are output to the FIFO port. In 53-octet cell formats, if status output is

enabled with Header Only Output, none of the other ports should be programmed for 53-octet output.

Enable Status Octet [bit 13] in CELL_VAL sends a status octet to FIFO Port 3. It should only be used in 53-octet output mode. When this bit is set, the HEC octet position in the FIFO output data is omitted, and a status word as shown in

Table 2 -1 9 is appended to the end of the cell as octet number 53. In 53-octet cell

formats, if status output is enabled with the Enable Status Octet bit, none of the other ports should be programmed for 53-octet output.

The status word contains indications of Port 3 header and payload errors as well as VCI/VPI match information for the other three ports for each cell received. The status word bits are set only if the corresponding failure occurs and the check for that failure is enabled. The User Data Bit is derived from the PT field in the header as shown in Tabl e 2-20 and can be used as an AAL5 EOM marker. These two Port 3 output options are available only if none of the ports are set to 57-octet output mode.

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Table 2-19. Status Octet Definition

Bit Definition

0 HEC Error Corrected for Port 3

1 HEC Error Not-Corrected for Port 3

2 Payload Length Error for Port 3 (AAL3/4)

3 Payload CRC-10 Error for Port 3 (AAL3/4)

4 User Data Bit for Port 3 (AAL5 EOM)

5 Header Match Port 0

6 Header Match Port 1

7 Header Match Port 2

Table 2-20. PT Header Field and User Data Bit

PT Header Field User Data Bit

2.6 ATM Cell Processing

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 0

If Disable Cell Receiver [bit 14] of CELL_VAL and Disable Port Reception— Port X [bits 7–4] of CONFIG_4 [0x29] are not set, then enabled checks are made on each cell received in the following sequence:

1. The HEC is checked for errors under control of the HEC Coverage [bit 1]

of CONFIG_3 [0x03]. Correctable errors are corrected if Enable HEC Correction [bit 8] of CELL_VAL is set. The correction/detection state machine is implemented as defined in the ATM UNI/NNI specifications. Errors counted in either the COR_HEC_ERR counter [0x49] or UNCOR_HEC_ERR counter [0x4A] are also indicated in the corresponding bits in the EVENT_STATUS register [0x39]. HEC error correction/detection is performed independent of any header screening that is enabled. Error correction should be enabled only if HEC Coverage is 0 and Enable HEC Coset [bit 0] of CONFIG_3 is 1.

2. The payload CRC-10 is checked. Errors are counted in the

PAY_CRC_ERR counter [0x48] and indicated in EVENT_STATUS. No CRC checking is performed on cells matching the idle header description.

3. The payload length is checked to be consistent with the segment type.

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2.6 ATM Cell Processing ATM Transmitter/Receiver with UTOPIA Interface

Segment Type Payload Length BOM or COM 44 EOM 4–44 mod 4 SSM 8–44 mod 4

Errors are counted in the PAY_LEN_ERR counter [0x4C] and indicated in EVENT_STATUS. No payload length checking is performed on cells matching the idle header description.

All errors disabled by the global disables in CELL_VAL are counted, and the first enabled error in the above sequence of checks is counted in the appropriate cell error counter. Disabled errors will not cause the cell to be marked as invalid. Header octets are compared to the HDR_VAL registers under control of the HDR_MSK bits. This determines routing to the proper output port. If no match is made to any of the VCI/VPI fields for the four ports or to the idle definition, the cell is counted in the NON_MATCH_CNT counter [0x57]. Payload CRC-10 and length checks can also be disabled on a per port basis by using the control bits in CONFIG_4. These bits simply disable the error from marking the cell as invalid and do not affect the counting of errors in any way. This feature can be used to route AAL 3/4 cells to one port with checks enabled and AAL5 cells to a different port with checks disabled.

HEC Coverage [bit 1] in CONFIG_3 determines the calculation range for the HEC. If this bit is low, the HEC is calculated over header octets 1–4 for ATM cells. If this bit is high, the HEC is calculated over header octets 2–4 for SMDS/802.6 cells.

Validation checks can be individually disabled with the remaining control bits in the CELL_VAL register [0x14]. Disable HEC Check [bit 9] disables the check of the header error control octet. Disable Payload Length Check [bit 10] disables the check for consistency between the segment type field and the length field. Disable Payload CRC Check [bit 11] disables the check of the payload CRC. The above disables are global disables for all ports and override the per-port control in CONFIG_4, which also contains per port disables for payload length and payload CRC checks.

2.6.2.3 Interrupts and

Status Counters for Cell

Validation

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Cell error events are indicated with bits 0–6 of the EVENT_STATUS register [0x39] and can cause an interrupt if enabled with the corresponding bit in the EN_EVENT_INT register [0x2E]. Status bits are latched at the event occurrence and are cleared when EVENT_STATUS is read. The error events are also counted, and interrupts on error counter overflows can be enabled in EN_OVFL_INT [0x2F]. Counter overflow status is provided in OVFL_STATUS [0x3A], and the status bits are cleared when the status register is read. These counters are not latched, and each counter is cleared individually when it is read.

CELL_RCV_CNTx [0x52–0x55] provides a count of all cells that are accepted for processing and delivery to Port x. This count is based on a header match with the header value and mask bits that are set in the associated registers for Port x. This count does not include cells discarded due to an error in the HEC. IDLE_CELL_CNT [0x56] is a count of valid cells received that match the programmed idle value and mask. NON_MATCH_CNT [0x57] is a count of active cells that did not match any of the programmed VCI/VPI values (port or idle).

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Counter overflow interrupts can be individually enabled. If a counter is set to interrupt, it rolls over to zero, sets the interrupt, and continues counting errors after it reaches its maximum value. If a counter is not set to interrupt, it saturates and holds when it reaches its maximum value (0xfff). The interrupt enable bits for the counters are found in the EN_CELL_INT register [0x30], with the corresponding interrupt status in the CELL_STATUS register [0x38]. If one of the cell counter overflow interrupts occurs, the CELL_STATUS register can be read to determine which counter or counters overflowed. These interrupts are cleared when CELL_STATUS is read.

Some interrupts in the CELL_STATUS register are related to the transmission/reception of individual cells. These interrupts may be enabled in EN_CELL_INT with corresponding status bits in CELL_STATUS. Cell Rcvd—Port x indicates the validation process has received a complete ATM cell destined for Port x. Cell Sent—Port x indicates a cell has been transmitted from source x. These interrupts are cleared when CELL_STATUS is read.

2.6.3 PLCP Cell Generation for Transmit

In 57-octet PLCP formats, the PLCP overhead generation consists of the framing octets A1 and A2, the Path Overhead Identifier (POI) octets, and the path overhead octets. All of these are generated by the PHY transmit circuitry, but can be selectively disabled if desired.

The A1 and A2 octets are generated according to TR-TSV-000773. The POI octets are determined by the particular PLCP that is selected, but in each case they consist of a slot count and a parity bit. The DS3 PLCP has 12 slots per frame, the DS1 and E1 PLCP have 10, and the E3 PLCP has 9. In each case, the POI octets provide a backwards count of the PLCP slots in the frame, along with a parity bit. Generation of the A1, A2, and POI octets can be disabled via the Overhead Control [bits 3–0] of CONFIG_2 [0x01]. All path overhead growth octets Zn and the path user channel F1 are forced to zero.

The B1 octet is populated with a BIP-8 code that is calculated over each PLCP frame. The BIP Error Insert [bits 12–10] of CONFIG_2 control insertion of BIP-8 errors in the generated PLCP. If errors are to be inserted, a non-zero value written to the TXFEAC_ERRPAT register inverts the corresponding bits of the B1 octet from that calculated by the BIP-8 circuit in the following PLCP frame. Insert control bits are cleared after each frame when the errors are inserted. The register can be read to determine if this has occurred, so that the microprocessor can insert BIP-8 errors as desired in each PLCP frame.

2.6 ATM Cell Processing

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This capability can be used to verify far-end FEBE operation. BIP generation can be disabled via the Overhead Control bits. The fields of the G1 octet are under control of the All 0s FEBE [bit 14], All 1s FEBE [bit 13], and Transmit Alarm Control [bits 9–4] of CONFIG_2. The FEBE controls operate as shown in

Table 2 -2 1.

Table 2-21. FEBE Controls

All 1s FEBE All 0s FEBE FEBE Field Value

0 0 BIP-8 Errors Received

0 1 0000

1 0 1111

1 1 0000

The yellow alarm bit in the G1 octet is set to the value contained in Transmit Alarm Control [bit 7].

The C1 octet is under control of PHY Type [bits 2–0] of CONFIG_1 [0x00], Force Cycle Stuffing [bit 6] of CONFIG_3 [0x02], and Overhead Control [bits 3–0] of CONFIG_2 [0x01] as shown in Ta ble 2 -22.

Table 2-22. C1 Octet

Disable C1 Generation

1xx 00

0DS1, E1x 00

0 DS3, E3 0 Per Selected 8 kHz Reference

0 DS3, E3 1 Per Default Cycle

The trailer content (except in E1 mode where there is no trailer) has each nibble set to 1100 unless Overhead Control [bit 0] is set. In this case, each nibble has the value 0000.

In 53-octet formats, no PLCP overhead is associated with each ATM cell. The only overhead present is that contained in the line framing format, as discussed in

Section 2.2.

PHY Type

Force Cycle

Stuffing

C1 Octet Value

(Via CONFIG_1, Bit 11)

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2.6.4 PLCP Cell Validation for Receive

In 57-octet PLCP formats, the PHY receiver implements framing state machines for cell alignment as described in TR-TSV-000773. In 53-octet formats, the PHY receiver implements the HEC alignment state machine as described in ITU I.432.

In serial framed 57-octet mode, the PHY receiver processes a serial stream to find PLCP framing. Octet synchronization is provided externally in DS1 and E1 modes. Internal or external E3 octet synchronization and DS3 nibble synchronization are provided to the PHY framer. Physical layer framing patterns are automatically removed before recovery of the octet data. If unframed mode is enabled, the receiver will search each bit position to determine octet alignment.

The 57-octet PLCP framing state machine contains three states: in-frame, out-of-frame, and loss-of-frame. Valid framing is found when two consecutive valid path overhead octets in sequence are observed after the A1, A2 framing octets. The out-of-frame state is entered only from the in-frame state, when there are errors in both the A1 and A2 octets or when there are two consecutive Pn errors. This event is an OOF event, and is counted. The LOF state is entered after eight consecutive PLCP frames in the out-of-frame state.

Stuffing and destuffing are provided according to the PHY type setting in 57-octet formats. Cycle stuffing is used at the transmit PLCP for DS3 and E3 whenever the receive PLCP is in the LOF state or the RCV_HLD input is high, and this function is enabled with Receiver Hold Enable [bit 10] of CONFIG_1 [0x00]. Cycle stuffing can also be forced by setting Force Cycle Stuffing [bit 6] of CONFIG_3 [0x02] high.

2.6 ATM Cell Processing

NOTE: When the framing mode is dynamically modified between direct mapping

and PLCP framing, the CN8223 will go into an OOF state. Dynamic switching should only be used if necessary.

2.6.4.1 PLCP Status Errors in either the A1 or A2 PLCP framing octets cause an indication in the

LINE_STATUS register PLCP Frame Error bit and are counted. PLCP OOF events are indicated by the PLCP OOF bit and counted. PLCP LOF events (OOF for eight consecutive PLCP frames) are indicated by the PLCP LOF bit. If an LOF condition persists for more than 2–3 seconds, the PLCP LOF 2–3 status bit is set. This is determined by LOF being set for three consecutive rising edges of the ONESECI input. Loss of cell delineation in 53-octet modes is indicated by the LOC bit and counted. PLCP OOF and LOC indications also appear on the LOCD output pin.

The PLCP Yellow Alarm status bit is set high after 10 consecutive frames with a PLCP yellow alarm value of one and cleared after 10 consecutive frames of a value of zero.

Errors detected in the receiver BIP-8 code checking circuit cause BIP-8 Error to be set and counted. FEBE Error is set if any valid non-zero FEBE value (values of 1 through 8) is received. This condition is also counted in the REM_BIP counter. Invalid FEBE is set if any invalid FEBE value (9 through F) is received; a value of F also causes FEBE All 1s to be set. This value is used to indicate that the FEBE calculation is not supported at the far end of the circuit.

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2.6 ATM Cell Processing ATM Transmitter/Receiver with UTOPIA Interface

Each rising edge at the ONESECI input causes an indication in the One-Second Count bit. This indication can be used as a timing interrupt to coordinate status collection. If Enable One-second Latching of Line Status is set, the ONESECI input also causes status indications in LINE_STATUS to be latched. If an alarm condition is present during a one-second interval, it is available to be read on the successive interval. Otherwise, the status is latched and held until it is read. If this bit is set and the status word is read twice within a one-second interval, the second read gives the current state of the status word and clears the status register. Enable One-second Latching of Line Counters provides the same functionality for the counters.

Each of the LINE_STATUS bits is latched until read and then cleared if the condition is no longer present. If a status condition clears before the register is read, the status bit is still held. Current status can be obtained by reading the register twice in succession.

2.6.5 PLCP Transmit/Receive Synchronization

For 57-octet formats, the PLCP block must transmit segments at the same rate as they are received. For DS1 and E1, long-term synchronization of the bit clock rates establish this. For DS3 and E3 rates, the payload data rate is independent of the line rate, and a separate timing/synchronization mechanism is required.

The DS3 and E3 PLCPs both have a 125 µs frame period. The reference clock for this frame is taken from the received signal, or alternatively from an external reference supplied to the 8 kHz clock input 8KCKI. In either case, the transmit circuit generates one PLCP frame per reference frame.

In 53-octet formats, all frame structures are based on a 125 consequently, no stuffing is required to synchronize the transmit and receive segments.

Clock and control inputs consist of the following:

µs period;

• An external 8 kHz reference for the PLCP at E3 and DS3

• A one-second input to synchronize status collection timing in

multiple-port applications

• A “hold receiver” input that can externally disable cell validation when an external framer loses frame or signal

• Three test inputs

• A reset input

A one-second clock output is provided to allow synchronization of status collection for multiple CN8223s or for CN8223s and framers. When a single CN8223 is used, ONESECO should be connected to ONESECI. This timing output is derived from the external 8 kHz reference clock input on 8KCKI.

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2.7 FIFO Port/UTOPIA Interface

The CN8223 has four bidirectional FIFO ports used to interface to the ATM layer outside the chip. These four ports share FDAT_IN and FDAT_OUT 8-bit ports. Each port has its own set of six control signals used for flow control and timing. (Refer to Figure 1-4, for a diagram of the FIFO port/UTOPIA interface.)

Port 0 can be configured as a level 1 compliant UTOPIA port for connection to other UTOPIA components. When UTOPIA mode is enabled, Ports 1, 2, and 3 are unused. The UTOPIA interface is detailed in Section 2.7.5.

2.7.1 FIFO Interface Inputs and Outputs

The four-port FIFO interface allows the connection of the CN8223 directly to dual-port RAMs, FIFO RAMs, and other similar circuits. The FIFO interface pins and their functions used for connection are listed in Tabl e 2- 23 . Transmit FIFO port timing for the 53-octet mode is shown in Figure 2-16. Detailed descriptions of the transmit FIFO pin functions are given in Ta ble 2 -2 4. Receive FIFO port timing for the 53-octet mode is shown in Figure 2-17. Detailed descriptions of the receive FIFO pin functions are given in Tabl e 2- 25 .

2.7 FIFO Port/UTOPIA Interface

Table 2-23. FIFO Interface Pin Connections (1 of 2)

CN8223 Function

FDAT_IN[8:0] Transmit Data with Parity

FCTRL_IN[0] Port 0 Transmit Data FIFO Empty

FCTRL_IN[1] Port 1 Transmit Data FIFO Empty

FCTRL_IN[2] Port 2 Transmit Data FIFO Empty

FCTRL_IN[3] Port 3 Transmit Data FIFO Empty

FCTRL_IN[4] Port 0 Receive Data FIFO Full

FCTRL_IN[5] Port 1 Receive Data FIFO Full

FCTRL_IN[6] Port 2 Receive Data FIFO Full

FCTRL_IN[7] Port 3 Receive Data FIFO Full

FDAT_OUT[8:0] Receive Data with Parity

FCTRL_OUT[0] Port 0 Receive Data Write Strobe

FCTRL_OUT[1] Port 1 Receive Data Write Strobe

FCTRL_OUT[2] Port 2 Receive Data Write Strobe

FCTRL_OUT[3] Port 3 Receive Data Write Strobe

FCTRL_OUT[4] Port 0 Receive Cell Invalid Indication

FCTRL_OUT[5] Port 1 Receive Cell Invalid Indication

FCTRL_OUT[6] Port 2 Receive Cell Invalid Indication

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2.7 FIFO Port/UTOPIA Interface ATM Transmitter/Receiver with UTOPIA Interface

Table 2-23. FIFO Interface Pin Connections (2 of 2)

CN8223 Function

FCTRL_OUT[7] Port 3 Receive Cell Invalid Indication

FCTRL_OUT[8] Ports 0, 1, 2 Receive Cell Sync Marker

FCTRL_OUT[9] Port 3 Receive Cell Sync Marker

FCTRL_OUT[10] Receive FIFO Write Error or Receive Start of Cell

FCTRL_OUT[11] Transmit Cell Sync Marker

FCTRL_OUT[12]

FCTRL_OUT[13]

FCTRL_OUT[14]

FCTRL_OUT[15]

FCTRL_OUT[16] Transmit PLCP Frame Sync Marker or Transmit Start of Cell

NOTE(S):

(1)

FIFO read strobes are forced inactive (high) during hardware or software resets.

(1)

Port 0 Transmit Data Read Strobe

Port 1 Transmit Data Read Strobe

Port 2 Transmit Data Read Strobe

Port 3 Transmit Data Read Strobe

Figure 2-16. Transmit FIFO Port Interface Timing, 53-Octet Mode

Port x Transmit

Data Read Strobe

Transmit Cell

Sync Marker

Transmit Start-

of-Cell Marker

Transmit Frame

Sync Marker

Port x Transmit

Data FIFO Empty

Transmit Data

Octet

•••

5654

8223_028

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Table 2-24. FIFO Transmit Pin Functional Descriptions

CN8223 FIFO Pin Function Functional Description

Transmit Data FIFO Empty In the transmit direction, the Transmit Data FIFO Empty input inhibits the Transmit Data Read

Strobe for a particular port. The empty flag from the FIFO, when inactive, indicates that the FIFO contains at least one entire cell of the appropriate length for the selected mode. Data read strobes to a particular port are inhibited if the empty flag for that port is low. There are four of these signals, asserted low, one per port.

Transmit PLCP Frame Sync If using FIFO mode and PLCP mapping, when 57-octet input is selected on the transmitter, the

Transmit PLCP Frame Sync Marker (FCTRL_OUT[16]) is high during the first slot of the PLCP frame to indicate the start of the frame.

Transmit Start of Cell Marker In 53-octet mode, FCTRL_OUT[16] indicates the Transmit Start of Cell, informing the FIFO that

the next strobe will read the first octet of the cell to be transmitted.

Transmit Cell Sync Marker The Transmit Cell Sync Marker is an additional output to delineate cell boundaries to the

transmit data FIFO. This marker is low during the read strobe requesting the last octet of a cell, and high during all other read strobes regardless of the programmed length of the cell to be transferred from the FIFO.

Figure 2-17. Receive FIFO Port Interface Timing, 53-Octet Mode

2.7 FIFO Port/UTOPIA Interface

Port X Receive

Data Write Strobe

Receive Cell Sync Marker

Receive Start-

of-Cell Marker

Receive Cell

Invalid Indication

Receive Data Octet

•••

56551234

8223_029

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2.7 FIFO Port/UTOPIA Interface ATM Transmitter/Receiver with UTOPIA Interface

Table 2-25. FIFO Receive Pin Descriptions

CN8223 FIFO Input Functional Description

Receive Data Write Strobe The receive data FIFO interface strobes data octets from FDAT_OUT[8:0] into an external

FIFO device on each rising edge of Receive Data Write Strobe. This strobe is a gated clock with 48-, 52-, 53-, or 57- strobes for the corresponding number of cell octets, depending on mode. There are four Receive Data Write Strobes, one per port.

Receive Data FIFO Full This flag is active low. If Receive Data FIFO Full is asserted by the external FIFO and the

CN8223 attempts a write to that port data, loss occurs. If this happens, Receive FIFO Write Error pin (FCTRL_OUT[10]) is asserted low. There are four Receive Data FIFO full signals, one per port.

Receive Cell Sync Marker The sync marker will be low during the last octet of data transfer and high during all other

octets of the data transfer for each cell regardless of the number of octets selected for output.

Receive Cell Invalid Indication This per-port signal indicates that a HEC or other check has failed. The invalid indication will

be low during the first octet of data transfer. If any enabled check fails, the invalid indication will be high during the last five octets of the cell. If no failures occur, the indication will stay de-asserted through the end of the cell. The FIFO or a microprocessor must mark this cell as bad to prevent further processing.

Optional Start of Cell Mode If Start-of-Cell/Write Error Output [bit 15] in the CELL_VAL register [0x14] is set, then

FCTRL_OUT[10] becomes an active-high start-of-cell output marker for the receiver, and FCTRL_OUT[16] becomes an active-high start-of-cell output marker for the transmitter. These indicators are valid only in 53-octet input/output mode. In this mode, the Receive FIFO Write Error function is not available.

2.7.2 Transmit Port Priority Mechanism

Each of the four transmit data read ports has a priority level that is programmable to four levels. The control bits for setting the port priority level are in the CELL_GEN_x control registers. Priority level 0 is the highest priority, priority level 3 is the lowest (see Tabl e 2-26).

Table 2-26. Priority Levels

CELL_GEN 3 CELL_GEN 2 Priority Level

00 0

01 1

10 2

11 3

If more than one port is assigned the same priority level, then arbitration occurs in port order with bandwidth allocated cyclically to Port 0, Port 1, Port 2, and Port 3.

The priority state machine looks at the port empty flag inputs for all ports at priority level 0 and reads cells from these ports cyclically until all port flags indicate empty. If no cells are available at priority 0, the state machine then looks at the port empty flags for all ports at priority level 1 and reads cells from these ports cyclically as long as no priority 0 port has a cell ready.

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If a higher priority port indicates that it has a cell ready during servicing of a lower priority port, service switches to the higher priority port after completion of the cell currently being formatted and transmitted. Servicing of ports and priority levels continues in this manner until the lowest priority ports are serviced and empty.

Port priority programming is not intended to be dynamic and should be used only as a configuration setup. Changes in port priority cannot take place until ports are inactive (via FIFO empty flag or transmit rate shaping).

Unused ports should be programmed to the lowest priority level, and their empty flag inputs should be connected to ground.

2.7.3 Transmit Rate Shaping Control

Each of the four transmit data ports has a rate shaping control to allow the allocation of programmable bandwidth to cells originating from this port. The TX_RATE_01 [0x09] and TX_RATE_23 [0x08] registers control this function.

The transmit circuitry contains a mod-256 master counter to control rate shaping. This counter is incremented for every ATM cell that is transmitted, and it rolls over to 0 when count 255 is reached.

The programmed rate value for a port in the TX_RATE_xx registers determines the count range for which transmission from that port is allowed. For instance, if Port 0 is programmed with a rate value of 63, transmission of cells queued at Port 0 will be allowed for 64 (one more than the programmed value) of the 256 counts of the master counter.

The transmission is spread over all counts of the counter so that transmission is not bursty. This gives Port 0 a bandwidth allocation of 25 % of the total outgoing bandwidth even if all of the other ports are inactive.

This allocation scheme is valid for rate values from 1 to 255 resulting in allocation ranges from 0.8 % to 100 %. Programming a port’s rate value to zero disables transmissions from that port and causes the transmit circuitry to ignore FIFO flag indications from that port.

The programmed rate value is an upper bound on the transmission from a particular port, and the exact ratio may not be achieved if multiple ports are active at the same time.

2.7 FIFO Port/UTOPIA Interface

2.7.4 Receive Port Addressing

Received cells are routed to each of the four FIFO ports depending on the values in the Header Value and Header Mask registers. These registers allow a range of ATM cells to be routed to one of the four FIFO ports. Also, the same ATM cell can be routed to multiple receive FIFO ports if desired.

The HDR_VALx_12 and HDR_VALx_34 register contents are used to match incoming ATM cell headers. There are four sets of these registers (x = 0, 1, 2, 3), one set for each of the four receive FIFO ports. If HDR_VALx_12 and HDR_VALx_34 are a bitwise match to the incoming cell, then this cell is routed to the x receive FIFO port.

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2.7.4.1 Header Screening

The HDR_MSKx_12 and HDR_MSKx_34 registers further qualify the bitwise values in the Header Value registers. There are four sets of these registers (x = 0, 1, 2, 3), one set for each of the four receive FIFO ports. A bit set to 1 in a Header Mask register sets the same bit position in the Header Value register to a Don’t Care condition for accepting cell headers.

An example of Header Value and Mask register screening for cells received by

FIFO Port 0 follows:

HDR_VAL0_12 = 0000 H

HDR_VAL0_34 = F000 H

HDR_MSK0_12 = 0000 H

HDR_MSK0_34 = 0000 H

This header screening setup for FIFO Port 0 receives cells with octets 1 2 3 4 equal to 00 00 F0 00. Since the Header Mask bits for Port 0 are all 0, there is no effect on the header value screening.

In the following example the Header Mask value allows multiple cells to be accepted by FIFO Port 0:

HDR_VAL0_12 = 0000 H

HDR_VAL0_34 = F000 H

HDR_MSK0_12 = 0000 H

HDR_MSK0_34 = 0003 H

2.7.4.2 Output Screening

This header screening setup for FIFO Port 0 accepts four different received cells with octets 1 2 3 4 equal to 00 00 F0 00, 00 00 F0 01, 00 00 F0 02, or 00 00 F0 03. The 2 bits set in HDR_MSK0_12 set Don’t Care conditions for the same 2 bit positions in HDR_VAL0_12. This allows four different ATM cell headers to be accepted by FIFO Port 0.

These control registers enable the CN8223 to be programmed to accept only certain slot types, or all slots whether busy or not, and also to screen slots for a particular VCI/VPI pattern. To disable header screening completely, write the mask register to all 1s. Headers are screened after any error correction is performed by the HEC circuitry.

The receiver circuitry contains buffer storage so that the header octets can be examined to determine which, if any, port is to be activated for output. This allows output of the PLCP and header octets in 57- and 53-octet modes, respectively.

Header octets are compared to the programmed values in the HDR_VAL registers under control of the HDR_MSK registers. If a match is made, the data write strobe for that port is activated, and the cells are written to the port. By using the mask bits to mark Don’t Care locations, cells with different header values can be sent to a single port. This allows entire VCI/VPI “pages” to be sent to the same location. Also, several ports can be programmed to receive cells with the same header values or overlapping pages of header values resulting in a programmable broadcast capability.

If Accept/Reject [bits 15–12] in CONFIG_3 [0x02], is set for a particular port, then all cells with headers matching the programmed header value and mask criteria are rejected by the port, and all other cells are accepted for output. This feature can be used to screen certain VCI/VPI values from being output to a particular port.

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If Delete Idle Cells [bit 2] of CONFIG_4 [0x29] is set, then received cells matching the idle header and mask criteria are automatically screened from appearing on the output of all ports.

This idle cell screening is in addition to any reject values that are programmed for the individual ports. Only addressed ports have active strobes.

2.7.5 UTOPIA Interface

The CN8223 incorporates an interface that is compliant with both the ATM For um UTOPIA Level 1 (Version 2.01) Specification and the Saturn Compliant Interface for ATM PHY Devices Specification.

When the UTOPIA interface is enabled, the CN8223 becomes a single port device with all input and output of cell data taking place on Port 0. Configurations for ports 1, 2, and 3 (such as header values and masks or rate controls) are ignored when in UTOPIA mode. The header values, masks, rate controls, and other per-port configuration control bits for Port 0 govern the operation of the UTOPIA port cell stream.

The UTOPIA interface contains transmit and receive buffer FIFOs with a depth of four cells and is programmable for reduced latency requirements per ATM Forum document 94/0317. UTOPIA interface pins are listed in Table 2-27.

The UTOPIA interface is controlled by 0x2B—UTOPIA_1 (Utopia Port

Control Register 1) and 0x2C—UTOPIA_2 (Utopia Port Control Register 2). The

timing for the UTOPIA interface is functionally compatible with the timing shown in the Version 2.01 ATM Forum Specification. Detailed timing information can be found in Chapter 4.0.

Table 2-27. UTOPIA Interface Pins

UTOPIA Signal CN8223 Pin

2.7 FIFO Port/UTOPIA Interface

Signal Direction Relative to

CN8223

TxData (7:0) FDAT_IN[7:0] In

TxPrty 0 FDAT_IN[8] In

TxSOC FCTRL_IN[0] In

TxEnb~ FCTRL_IN[1] In

TxClk FCTRL_IN[2] In

TxFull~/TxClav FCTRL_OUT[2] Out

RxData (7:0) FDAT_OUT[7:0] Out

RxPrty 0 FDAT_OUT[8] Out

RxSOC FCTRL_OUT[0] Out

RxEnb~ FCTRL_IN[3] In

RxClk FCTRL_IN[4] In

RxEmpty~/RxClav FCTRL_OUT[1] Out

— FCTRL_IN[5:7] Reserved, Connect to Ground

— FCTRL_OUT[16:4] Undefined Output

RcvFifoOverflow FCTRL_OUT[3] Out

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2.8 FEAC Channel and HDLC Data Link Programming ATM Transmitter/Receiver with UTOPIA Interface

2.8 FEAC Channel and HDLC Data Link Programming

This section discusses the use and programming requirements for the FEAC channel and HDLC data link. The FEAC channel is used in DS3 mode; the HDLC data link is used by DS3, E3, and STS-1/3 framers.

2.8.1 FEAC Channel Transmitter

The FEAC Channel transmitter is under control of the PHY Type [bits 2–0], External Framer [bit 5] of CONFIG_1 [0x00], Transmit Alarm Control [bits 9–4 of CONFIG_2 [0x01], Enable FEAC Transmission [bit 9], and Transmit FEAC Data [bits 15–10] of TXFEAC_ERRPAT [0x03]. An interrupt for use with FEAC channel operations is available on the DL_INT output pin, and status bits for determining the interrupt source are located in the RXFEAC_VER register [0x3C].

The PHY type must be set to internal DS3 for FEAC channel transmission to take place. In DS3 mode, the last C bit in subframe 1 of the M-frame is used for transmission. Setting the Transmit Alarm Control [bits 9–4] for transmission of AIS disables transmission of the FEAC channel. Transmission of yellow alarm or idle code has no effect on FEAC channel transmission.

The TXFEAC_ERRPAT register controls the byte to be transmitted on the FEAC channel. All messages for transmission on the FEAC channel must be in the form “0xxxmmm011111111”. The right-most bit of this sequence is the first bit transmitted on the channel. To initiate transmission of a message byte in the FEAC channel, write the desired byte in the form “mmmxxx” into bits 15–10 of the TXFEAC_ERRPAT register. A 1 must be written to Enable FEAC Transmission [bit 9]. Transmission of the flag (11111111) and the 0s on either side of the “xxxmmm” pattern is automatic. Ten repetitions of the message are sent before an interrupt is issued on the DL_INT pin. The interrupt also appears in the RXFEAC_VER register to request a new byte from the processor. To clear the interrupt, you must write the TXFEAC_ERRPAT register. Each time a new byte is written, 10 transmissions of that byte (and flag) will automatically occur. Interrupts from the transmit FEAC channel will occur at a rate of approximately one interrupt per 17 ms.

If you write a 0 to Enable FEAC Transmission [bit 9], then continuous transmission of idle flags is enabled and no interrupts are issued until a byte of the proper format is written to the TXFEAC_ERRPAT register. Interrupts from the FEAC channel transmitter appear on Transmit FEAC Interrupt [bit 8] in the RXFEAC_VER register [0x3C].

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2.8.2 FEAC Channel Receiver

The FEAC channel receiver is under control only of the received data stream. The receiver interrupt is under control of Enable Receive FEAC Interrupt [bit 8] in TXFEAC_ERRPAT. This interrupt must be enabled by setting this bit for receiver interrupts to appear on the DL_INT output and for proper interaction with the processor. The last C bit in subframe 1 in C bit parity mode is provided to the receiver circuitry at all times.

Receiver status is monitored via Receive FEAC Interrupt [bit 9] in RXFEAC_VER. When a receive FEAC channel interrupt is generated on DL_INT, the Receive FEAC Interrupt bit will be set in 0x3C. If this bit is observed upon reading the RXFEAC_VER, then at least 10 repetitions of the same byte have been received by the data link and placed in bits 15–10 of RXFEAC_VER. The receive interrupt serves as notice that the message bits in RXFEAC_VER are valid. Reading RXFEAC_VER clears the receive interrupt.

An idle message is all 1s, and all other messages are of the form “0xxxmmm011111111” with reception of the rightmost bit first from the channel. The receiver logic recognizes the eight 1s message flag followed by a message byte and interrupts the controller upon reception of 10 repetitions of a valid message byte. The “mmmxxx” message byte that was received is stored in RXFEAC_VER bits 15–10 at 0x3C. Continuous incoming messages on the FEAC channel produce an interrupt rate of approximately one interrupt per 17 ms for this interrupt source. No interrupts are generated if the FEAC channel is receiving continuous idle flags or if the interrupt is not enabled in TXFEAC_ERRPAT.

2.8.3 HDLC Data Link Transmitter

The HDLC data link capability is present in the following formats:

2.8 FEAC Channel and HDLC Data Link Programming

• DS3 Terminal Data Link C bits

• G.751 E3 N bit

• G.832 E3 and E4 GC octet

• STS-1/STS-3c/STM-1 D1, D2, D3 octet data link

The HDLC formatter has an 8-octet buffer (organized as four 16-bit words) for both the receiver and transmitter, located at addresses 0x58 through 0x5B and 0x5C through 0x5F, respectively. Addresses are word-wide locations that hold 2 bytes each. Therefore, each buffer has an address range of 4, two for each buffer half. Each buffer holds 4 octets.

The HDLC data link transmitter is under the control of the Enable HDLC Data Link [bit 5] in the CONFIG_5 [0x31] and bits 6–0 in DL_CTRL_STAT [0x60]. An interrupt for use with data link operations is available on the DL_INT output pin, and status bits for determining the interrupt source are located in DL_CTRL_STAT.

If the framer is in a mode that allows data link transmission as described above, the DL_CTRL_STAT register is the main control register used for transmit data link operations. Disable Data Link Transmission [bit 6] of DL_CTRL_STAT must be set low to enable operation of the data link. If this bit is set high, an all 1s signal is transmitted in the data link bit positions in the outgoing serial stream. With the data link enabled, the Send Message [bit 0], Send FCS [bit 1], and Abort Message [bit 2] bits of DL_CTRL_STAT control operation. TxBytes[2:0] [bits 5–3] of DL_CTRL_STAT form a pointer to the TX_DL_BUFFER used by the data link transmitter.

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2.8 FEAC Channel and HDLC Data Link Programming ATM Transmitter/Receiver with UTOPIA Interface

The transmitter implements an HDLC data link per ITU standard Q.921. The functions provided by the data link transmitter circuitry are transparency zero stuffing, Frame Check Sequence (FCS) generation, idle flag generation, and abort flag generation. There are no restrictions on the total length of the message. Q.921 requires that all messages be an integral number of 8-bit bytes. The transmitter can only transmit 8-bit bytes. The byte transmission times for the transmitter are approximately those shown in Table 2- 2 8.

Table 2-28. Byte Transmission Times for Transmitter

Mode Byte Transmission Times

DS3 C bit Parity

G.751 E3

G.832 E3, E4

STS-1

STS-3c/STM-1

An 8-byte buffer (organized as four 16-bit words) is provided for the transmit data link channel to minimize processor interruptions. This buffer is located at addresses 0x5C through 0x5F. Byte 0 is the least significant byte of 0x5C, byte 1 is the most significant byte of 0x5C, byte 2 is the least significant byte of 0x5D, etc. Filling of this buffer is accomplished by the processor in the same manner as writing to control registers. This buffer can be read as well as written to verify contents. The buffer is divided into two halves to reduce the real-time requirements on the processor. The processor loads four bytes (2 words) at a time, while the data link transmitter reads from the other half of the buffer. This gives the processor at least 160 bytes of message for transmission before the next interrupt is issued. Interrupts are issued each time the transmitter circuitry reaches a 4-byte buffer boundary.

The transmitter should be initialized with the DL_CTRL_STAT register bits 6–0 written to zero. This enables the transmitter to send idle flags on the data link. No interrupts are generated when the data link is sending idle flags, thus no processor intervention is required until a message is to be sent.

µs (at the fastest byte rate) to assemble the next four

284 µs

357 µs

125

µs

125 µs

µs

2.8.3.1 Sending a Message

2-46 Conexant 100046C

Beginning with an idle channel, the processor writes the first four bytes of message data to the TX_DL_BUFFER. The first two bytes of data to be transmitted should be written to 0x5C. The message is written to the buffer in ascending order starting at 0x5C and ending at 0x5F. The least significant bit (LSB) in each byte is transmitted first. This buffer can be written well before the message is to be sent, if desired. After the first block of data is present in the buffer memory, the processor writes to the DL_CTRL_STAT register to begin transmission:

• Send Message = 1

• TxBytes[2:0] = 3

• Send FCS = 0

• Abort Message = 0

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ATM Transmitter/Receiver with UTOPIA Interface

The 3-bit field TxBytes[2:0] is functionally split into two parts. The most significant bit (MSB) indicates to the transmitter circuitry which half of the buffer to read from next. The two LSBs indicate the stop location, i.e., where the last message byte is located. When the new controls are latched by the transmitter circuitry, the processor is interrupted for the next set of controls. Now, the processor has up to 4-byte intervals (byte transmission time periods) to write a new set of controls to the control register. Because of a race condition, the ISR that is processing the transmit interrupt must delay 1.5 byte times before writing a new control register value. The processor can now write the next block of data to the next half of the message buffer.

When the end of a message is reached, or in the event of a short message, there may not be exactly 4 bytes remaining. In this case, the processor writes the remaining data to the message buffer as usual. The processor now must write the highest location used to the TxBytes[2:0] field in the data link control register. Send FCS is set to 1. This causes the FCS to be sent after this last block of data.

When this set of controls is latched, the processor is interrupted. At this time a new message can be sent, or Send Message can be set to 0 to send idle flags. If a new message is to be sent immediately, the next half of the transmit buffer can be written, and the data link control register configured accordingly. This results in only one idle flag being transmitted between messages. If there is no new message ready, the processor must write Send Message to 0. If this is not done within 4 byte intervals, undefined data is transmitted.

2.8 FEAC Channel and HDLC Data Link Programming

2.8.3.2 Aborting a Message

2.8.3.3 Transmitter Interrupts

To abort a message in progress, the controller writes Abort Message to 1 in the data link control register. The transmitter finishes sending the message byte in progress, then transmits an abort flag (11111110). After writing the abort signal to the control register, a second write may follow the next interrupt to cause the transmitter to go to the idle condition or to transmit another message. In the latter case, the abort flag is followed by one idle flag, and the new message begins. If the second write is not performed, the formatter continues to transmit abort flags until instructed otherwise.

The transmitter generates an interrupt when it has latched the present set of controls and is ready for a new set. There are no interrupts during the transmission of idle flags. Therefore, to start a message from an idle condition, the processor writes the first half of the buffer and the proper control bits. When the circuit latches these controls internally, an interrupt is immediately issued for the next set of control bits. The processor then has up to 4 byte intervals to respond to the interrupt. The interrupt appears on the DL_INT pin. The DL_CTRL_STAT register indicates the source of the interrupt but not the cause. The controller software must know from the message context what response is required. The interrupt is an active low level, not a pulse. The transmit interrupt is cleared upon the writing of the DL_CTRL_STAT register. A write operation must be performed to clear the current interrupt and prevent missing later interrupts.

If the interrupt is a mid-message interrupt, a new data link control word must be written with TxBytes[2:0] equal to the ending location of the next message block. The MSB of TxBytes[2:0] informs the transmit circuitry which half of the buffer to read next.

Interrupts from the HDLC data link transmitter will appear on Transmitter Interrupt [bit 14] in DL_CTRL_STAT [0x60]. Interrupts must be enabled to appear on DL_INT by setting Enable HDLC Data Link = 1 in CONFIG_5.

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2.8 FEAC Channel and HDLC Data Link Programming ATM Transmitter/Receiver with UTOPIA Interface

2.8.3.4 Transmitter Control Example

This example shows the sequence necessary to transmit a 10-byte hex message starting in the low half of the transmit buffer. With the transmitter in the idle state, the processor executes the following sequence:

2.8.4 HDLC Data Link Receiver

The HDLC data link receiver is under the control of the received data stream only. The receiver interrupt is under the control of Enable Receive Data Link Interrupt [bit 7] in DL_CTRL_STAT [0x60]. You must enable this interrupt by setting this bit for receiver interrupts to appear on the DL_INT output and for proper interaction with the processor. The HDLC data link capability is present in the following formats:

write bytes 1 and 2 to address 0x5C

write bytes 3 and 4 to address 0x5D

write 19 to address 0x60 (bytes = 3, send message = 1)

at TX Interrupt:

write bytes 5 and 6 to address 0x5E

write bytes 7 and 8 to address 0x5F

write 39 to address 0x60 (bytes = 7, send message = 1)

at TX Interrupt:

write bytes 9 and 10 to address 0x5C

write 0B to address 0x60 (bytes = 1, send message = 1,

send FCS = 1)at TX Interrupt:

write 00 to address 0x60 (send message = 0, send FCS = 0

• DS3 Terminal Data Link C bits

• G.751 E3 N bit

• G.832 E3 and E4 GC octet

• STS-1/STS-3c/STM-1 D1, D2, D3 octet data link

The data link bits are provided to the receiver circuitry at all times. Therefore, when the LINE_STATUS register [0x38] indicates that alarms are being received that render the data link information useless, you can disable the receive data link interrupt to prevent excessive or spurious interrupts to the processor. Receiver status is monitored via Receiver Interrupt [bit 15] in DL_CTRL_STAT and via the receiver status bits in that register (bits 13-8). When a receive data link interrupt is generated on DL_INT, the Receiver Interrupt bit is set. If this bit is observed upon reading the DL_CTRL_STAT register, then the status obtained from bits 13–8 indicates the receiver status that caused the interrupt.

The DL_CTRL_STAT register contains three status bits and a three-bit buffer pointer. The status bits are Abort Flag Received [bit 8], Bad FCS [bit 9], and Idle Code Received [bit 10]. The 3-bit buffer pointer RxBytes[2:0] [bits 13–11] is used to point to locations in the 8-byte (organized as four 16-bit words) RX_DL_BUFFER. This buffer is located at addresses 0x58 through 0x5B. The buffer pointer indicates the last location written by the data link receiver. Byte 0 of the buffer is the least significant byte of 0x58, byte 1 is the most significant byte of 0x58, byte 2 is the least significant byte of 0x59, etc.

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ATM Transmitter/Receiver with UTOPIA Interface

2.8.4.1 Receiver Operation

The receiver implements an HDLC data link per ITU standard Q.921. The functions provided by the data link receiver circuitry are transparency-zero removal, FCS checking, idle flag reception, and abort flag reception. There are no restrictions on the total length of the message. Q.921 requires that all messages be an integral number of 8-bit bytes. If the receiver receives a message that is not an integral number of bytes, the receiver status indicates a message received with bad FCS. The per-byte reception times are equivalent to those given for the transmitter for any particular mode.

The receiver powers up in an indeterminate state. It is initialized by the receipt of an idle flag (0x7E) on the link, which sets Idle Code Received = 1 in the data link status register (bits 13-8 of 0x60). When the idle flag is removed from the link and a message starts coming in, the receiver removes stuffed 0s and writes the resulting data to the receive data link buffer beginning with the least significant byte of 0x58 and counting up to the most significant byte of 0x5B.

When the first four bytes have been written, the processor is interrupted to read the data out of the buffer. The processor has 4 byte intervals to read the data before it is overwritten with new data. The interrupt is cleared when the processor reads DL_CTRL_STAT. The status register indicates a message in progress at this time:

• Idle Code Received = 0

• RxBytes[2:0] = 3

2.8 FEAC Channel and HDLC Data Link Programming

If the upper half of the buffer had just been filled, the status register indicates RxBytes[2:0] = 7, and locations 4 through 7 must be read during the next 4 byte intervals to retrieve the message.

When the last block of data has been received, the processor is again interrupted. This time, the data link status register indicates the end of message:

• Idle Code Received = 1

• RxBytes[2:0] = n

• Bad FCS = 0 or 1

The RxBytes[2:0] = n portion of the register indicates the highest-numbered location that was written in the receive buffer. Locations 0 to n or 4 to m (where n = 0 to 3 and m = 4 to 7) must be read to retrieve the data depending on what has already been read at the previous interrupt. The two highest-numbered locations contain the FCS that was received at the end of the message. A new incoming message always starts in the opposite buffer half from where the previous message ended to prevent overwriting of previously received bytes and allow the processor time to retrieve those bytes. For example, if a message ended in buffer 0x5A or 0x5B, the next message received would be stored starting in 0x58. If a message ended in buffer 0x58 or 0x59, the next message received would be stored starting in 0x5A.

If the received message is a multiple of 8 bytes, then when the processor is interrupted to read the last block of data, the FCS has yet to be received. In this event, the processor is again interrupted when the FCS has been checked, and an idle flag received. The data link status register shows RxBytes[2:0] = 1 (or 5), FCS good or bad, and Idle Code Received = 1; and the FCS that was received will be in locations 0 and 1 (or 4 and 5). Again, the data must be read out during the next 4 byte intervals, or it may be overwritten by a new incoming message.

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2.0 Functional Description CN8223

2.8 FEAC Channel and HDLC Data Link Programming ATM Transmitter/Receiver with UTOPIA Interface

Alternatively, the FCS data may be ignored, and the good or bad indication used directly. It is important that software strategies allow for the fact that the LAPD receiver cannot recognize the FCS as such until the closing flag is recognized. It can happen that the processor is interrupted to read 4 message bytes, and the next byte received is the closing flag.

When the processor exits the interrupt routine, another interrupt will be pending for the end of message. The status for this interrupt indicates the idle condition, the FCS status, and the byte count will be the same as the previous interrupt (RxBytes[2:0] = 3 or 7) because no extra bytes were received. In this event, the last two bytes read from memory on the previous interrupt were not message bytes after all, but were actually the FCS bytes. If the FCS spans a 4-byte boundary, the final interrupt indicates that one additional byte was received (RxBytes[2:0] = 0 or 4), the idle condition, and the FCS status.

2.8.4.2 Receiver Interrupts

The data link receiver generates an interrupt in response to three events:

1. The current half of the message buffer is full

2. The end-of-message flag was detected

3. An abort flag was detected

DL_CTRL_STAT indicates the cause of the interrupt. The interrupt is cleared

upon the reading of this register.

If the interrupt is due to the current half of the receive buffer being full, Idle Code Received is cleared, and RxBytes[2:0] indicates which half of the buffer must be read.

If the interrupt is due to the end-of-message flag being detected, Idle Code Received is set, Bad FCS indicates the result of the FCS error check, and RxBytes[2:0] indicates the last location written. The processor is not interrupted again until four bytes of a new message have been received.

If the interrupt is due to an abort flag being received, Abort Flag Received is set, and there is nothing to be done by software other than discard any previously received message bytes. The processor will not be interrupted again until four bytes of a new message have been received.

Interrupts from the HDLC data link receiver appear on Receiver Interrupt [bit 15] in DL_CTRL_STAT. Interrupts must be enabled to appear on DL_INT by setting Enable Receive Data Link Interrupt [bit 7] in DL_CTRL_STAT.

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CN8223 2.0 Functional Description

ATM Transmitter/Receiver with UTOPIA Interface

2.8.5 Receiver Response Example

The following example shows the sequence necessary to receive an 8-byte hex message that was stored starting in the low half of the receive buffer. In this example, the final interrupt indicates that two more bytes are present in the buffer; however, these bytes are FCS bytes, not message bytes.

When an interrupt is received, the processor reads DL_CTRL_STAT [0x60] to determine the source of the interrupt. If the source is determined to be the receive HDLC data link, the processor responds in the following manner (the status shown below ignores bits 15 and 14 in DL_CTRL_STAT):

at RX Interrupt:

read address 0x60 to get status (status = 18xx:

read address 0x58 to get 1st and 2nd data bytes

read address 0x59 to get 3rd and 4th data bytes at RX

read address 0x60 to get status (status = 38xx:

read address 0x5A to get 5th and 6th data bytes

read address 0x5B to get 7th and 8th data bytes at RX

read address 0x60 to get status(status = 0Cxx or 0Exx

read address 0x58 if desired (FCS bytes 1 and 2)

2.8 FEAC Channel and HDLC Data Link Programming

bytes = 3, idle = 0)

Interrupt:

bytes = 7, idle = 0)

Interrupt:

bytes = 1, idle = 1, bad fcs = 0 or 1)

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2.8 FEAC Channel and HDLC Data Link Programming ATM Transmitter/Receiver with UTOPIA Interface

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3.0 Registers

3.1 Registers Overview

Table 3 -1 displays an overview of the CN8223 registers. All registers are 16-bit, and the addresses are on 16-bit

boundaries. There are seven address pins, A[7:1]. A[0] is always 0; therefore, it does not require a pin.

Table 3-1. ATM Transmitter/Receiver Status Registers, Counters, and Data Link Control

CN8223 Control and Status Registers

Address Name Allowed Operations

0x00–0x31, 0x60 Control Registers Read and Write

0x38–0x3B Status Registers Read Only

0x3C Part Number/Version/FEAC Rx Read Only

0x40–0x48 Line Framer/PHY Error Counters Read Only

0x49–0x4D Cell Error Counters Read Only

0x4E–0x57 Cell Transmitted/Received Counters Read Only

0x58–0x5B Receive HDLC Data Link Buffers Read Only

0x5C–0x5F Transmit HDLC Data Link Buffers Read and Write

100046C Conexant 3-1

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3.0 Registers CN8223

3.2 Control Register Overview ATM Transmitter/Receiver with UTOPIA Interface

3.2 Control Register Overview

Table 3 -2 lists the 52 control registers of the CN8223. Control registers are realized as latches within the

CN8223 and are programmed by a write operation from the microprocessor. No initialization is provided for operational purposes. All registers must be initialized as required for each application by the microprocessor. A reset signal on the RESET pin (pin 118) resets counters and framer state machines. RESET does not affect control register contents.

Control bits that do not have a defined function are reserved and must be written to 0. All control registers can be read to verify contents, except those control bits whose functions cause single events and are, therefore, not latched.

Control registers in this section have been ordered by function: 7 control configurations, 19 control transmitter functions, 22 control receiver functions, and 4 enable interrupts.

Table 3-2. ATM Transmitter/Receiver Microprocessor Control Registers (1 of 2)

Address Name Function

0x00 CONFIG_1 Configuration Control Register 1

0x01 CONFIG_2 Configuration Control Register 2

0x02 CONFIG_3 Configuration Control Register 3

0x03 TXFEAC_ERRPAT Transmit FEAC/BIP-8 Error Pattern

0x04 CELL_GEN_0 Cell Generation Control - Port 0

0x05 CELL_GEN_1 Cell Generation Control - Port 1

0x06 CELL_GEN_2 Cell Generation Control - Port 2

0x07 CELL_GEN_3 Cell Generation Control - Port 3

0x08 TX_RATE_23 Transmit Rate Control Value - Ports 2, 3

0x09 TX_RATE_01 Transmit Rate Control Value - Ports 0, 1

0x0A TX_IDLE_12 Transmit Idle Header Value - Octets 1, 2

0x0B TX_IDLE_34 Transmit Idle Header Value - Octets 3, 4

0x0C TX_HDR0_12 Transmit Port 0 Header Value - Octets 1, 2

0x0D TX_HDR0_34 Transmit Port 0 Header Value - Octets 3, 4

0x0E TX_HDR1_12 Transmit Port 1 Header Value - Octets 1, 2

0x0F TX_HDR1_34 Transmit Port 1 Header Value - Octets 3, 4

0x10 TX_HDR2_12 Transmit Port 2 Header Value - Octets 1, 2

0x11 TX_HDR2_34 Transmit Port 2 Header Value - Octets 3, 4

0x12 TX_HDR3_12 Transmit Port 3 Header Value - Octets 1, 2

0x13 TX_HDR3_34 Transmit Port 3 Header Value - Octets 3, 4

0x14 CELL_VAL Cell Validation Control

0x15 HDR_VAL0_12 Receive Port 0 Header Value - Octets 1, 2

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ATM Transmitter/Receiver with UTOPIA Interface

Table 3-2. ATM Transmitter/Receiver Microprocessor Control Registers (2 of 2)

Address Name Function

0x16 HDR_VAL0_34 Receive Port 0 Header Value - Octets 3, 4

0x17 HDR_VAL1_12 Receive Port 1 Header Value - Octets 1, 2

0x18 HDR_VAL1_34 Receive Port 1 Header Value - Octets 3, 4

0x19 HDR_VAL2_12 Receive Port 2 Header Value - Octets 1, 2

0x1A HDR_VAL2_34 Receive Port 2 Header Value - Octets 3, 4

0x1B HDR_VAL3_12 Receive Port 3 Header Value - Octets 1, 2

0x1C HDR_VAL3_34 Receive Port 3 Header Value - Octets 3, 4

0x1D HDR_MSK0_12 Receive Port 0 Header Mask - Octets 1, 2

0x1E HDR_MSK0_34 Receive Port 0 Header Mask - Octets 3, 4

0x1F HDR_MSK1_12 Receive Port 1 Header Mask - Octets 1, 2

0x20 HDR_MSK1_34 Receive Port 1 Header Mask - Octets 3, 4

0x21 HDR_MSK2_12 Receive Port 2 Header Mask - Octets 1, 2

0x22 HDR_MSK2_34 Receive Port 2 Header Mask - Octets 3, 4

3.2 Control Register Overview

0x23 HDR_MSK3_12 Receive Port 3 Header Mask - Octets 1, 2

0x24 HDR_MSK3_34 Receive Port 3 Header Mask - Octets 3, 4

0x25 RX_IDLE_12 Receive Idle Header Value - Octets 1, 2

0x26 RX_IDLE_34 Receive Idle Header Value - Octets 3, 4

0x27 IDLE_MSK_12 Receive Idle Header Mask - Octets 1, 2

0x28 IDLE_MSK_34 Receive Idle Header Mask - Octets 3, 4

0x29 CONFIG_4 Configuration Control Register 4

0x2A IDLE_PAY Transmit Idle Cell Payload Value

0x2B UTOPIA_1 Utopia Port Control Register 1

0x2C UTOPIA_2 Utopia Port Control Register 2

0x2D EN_LINE_INT Line/PHY Status Interrupt Enable Register

0x2E EN_EVENT_INT Status Event Interrupt Enable Register

0x2F EN_OVFL_INT Counter Overflow Interrupt Enable Register

0x30 EN_CELL_INT Cell Counter Interrupt Enable Register

0x31 CONFIG_5 Configuration Control Register 5

0x32 TX_K1K2 Transmit K1, K2 Value for SONET APS

0x33 RX_K1K2 Receive K1, K2 Value for SONET APS

0x60 DL_CTRL_STAT HDLC Data Link Control and Status Register

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3.0 Registers CN8223

3.3 Configuration Control Registers ATM Transmitter/Receiver with UTOPIA Interface

3.3 Configuration Control Registers

0x00—CONFIG_1 (Configuration Control Register 1)

The CONFIG_1 register is located at address 0x00. This register sets chip parameters for both transmit and receive operations. The line interface type is set for both transmit and receive by bits 7–0. Valid combinations of bits 7–0 for the line interface type in this register are given in Tabl e 3- 3.

Bit

15 1 STS-1 Stuffing

14 1 Source Loopback Causes the receiver input to be taken from the transmitter output in all modes; the

13 1 Enable One-Second

12 1 Enable One-Second

Field

Size

Name Description

Enables an alternate ATM mapping for STS-1 mode. If this bit is set, then 84

Option

Latching of Line Counters

Latching of Line Status

columns of the SPE are available for ATM cell octets. If this bit is not set, then all 86 columns of the SPE are available for ATM cell octets.

transmitter output is unaffected. This function allows the generation of self-diagnostic routines at system startup to ensure the health of the line/physical framing process. If an external framer mode is selected, the external framer needs to continue providing an input to TXSYI when source loopback is enabled. Source loopback does not work in TAXI mode.

Causes status indications in the line/PHY counters (other than LCV) to be latched at one-second intervals. This interval is determined by successive rising clock edges to ONESECI. If an alarm condition is present during a one-second interval, it is available to be read on the successive interval. Otherwise, the status is latched and held until it is read. If this bit is set and the status word is read twice within a one-second interval, the second read gives the current state of the status word and clears it.

Causes status indications in the LINE_STATUS register to be latched at one-second intervals. The one-second interval is determined by successive rising clock edges to ONESECI. If an alarm condition is present during a one-second interval, it is available to be read on the successive interval. Otherwise, the status is latched and held until it is read. If this bit is set and the status word is read twice within a one-second interval, the second read gives the current state of the status word and clears it.

11 1 External 8 kHz

Timing

10 1 Receiver Hold

Enable

91Enable Cell

Scrambler

8 1 Disable LOCD Allows cell validation and error counting to continue when cell delineation is lost (via

3-4 Conexant 100046C

Forces the transmit PLCP to be synchronized to an external 8 kHz timing reference rather than to the received PLCP reference. This control bit is meaningful only in 57-octet DS3 and E3 formats.

Allows the RCV_HLD input to disable cell processing. Internal cell receiver functions will operate, but no segments will be accepted by the cell validation state machine or output on the FIFO ports.

Enables the x payload.

either PLCP or HEC).

+ 1 scrambler (required for 53-octet direct mapping) for cell

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ATM Transmitter/Receiver with UTOPIA Interface

Bit

71Enable HEC

6 1 Enable Parallel

5 1 External Framer Set if line framing is performed with an external framer. When this bit is low, the

4 1 Disable B3ZS/HDB3 Bypasses the internal encoder/decoder so that NRZ data can be presented directly to

3 1 Unframed Input Specifies whether the serial stream from an external circuit contains overhead or

2–0 3 PHY Type Sets the type of line framing and physical processing to be used. PHY modes are

Field

Size

Name Description

Enables cell delineation via the HEC alignment method. This method is for use in any

Alignment

Interface

mode where cells are directly mapped into the physical layer. When this bit is set, 53-octet cells are expected. When this bit is low, 57-octet cells (with PLCP framing overhead) are expected.

Selects the parallel interface for input/output. When this bit is low, serial data is expected; when high, parallel data is expected.

internal framer for the selected mode will be used.

the internal framing functions. For E1 and DS1 in external framer mode, set to 0.

only payload. The normal mode is framed mode. Physical layer overhead bits are located by a synchronization input and are ignored by the PHY framer. In unframed mode, all line framing bit positions are assumed to be nonexistent.

always symmetric; the transmit and receive modes are identical. The PLCPs for DS1 and DS3 are described in TR-TSV-000773; E1 and E3 PLCPs are described in ETSI draft standards prETS 300 213 and prETS 300 214; E3, DS3, and E4 direct-mapped modes are described in ITU G.832; and STS-1 and STS-3c formats are described in TR-NWT-000253.

3.3 Configuration Control Registers

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3.3 Configuration Control Registers ATM Transmitter/Receiver with UTOPIA Interface

Table 3-3. Valid Combinations of CONFIG_1, Bits 0–7

Type of Line Input Signal

DS1 00 0100 or 1

DS1 (externally gapped 192 bits/frame) 0 1 0 1 0 0

E1 10 01 00 or 1

E1 (externally gapped TS0 and TS16) 1 1 0 1 0 0

DS3, Internal Framer 2 0 0 or 1 0 0 0 or 1

DS3, External Framer 2 0 0 1 0 0 or 1

DS3, External Framer (gapped 84/85 bits) 2 1 0 1 0 0

E3, Internal G.751 Format 3 0 0 or 1 0 0 0

E3, External G.751 Format 3 0 0 1 0 0

E3, External G.751 Format (gapped 1st 16 bits)

E3, Internal G.832 Format 4 x 0 or 1 0 0 1

E4, Internal G.832 Format 5 x 1 0 0 1

STS-1, Internal Framer 6 x 0 or 1 0 0 1

STS-3c/STM-1, Internal Framer 7 x 1 0 0 1

PHY

Type

31 0100

Unframed

Input

Disable

B3ZS/

HDB3

External

Framer

Enable

Parallel

Interface

Enable

HEC

Align

Parallel or TAXI Interface, 53 Octet Cells 0 x 0 1 1 1

Notes: 1. “x” = Don’t Care

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3.3 Configuration Control Registers

0x01—CONFIG_2 (Configuration Control Register 2)

The CONFIG_2 register is located at address 0x01 and controls transmit formatting and alarm generation.

Table 3 -4 defines Alarm Controls for the Line Framing/PHY Formats. Tabl e 3- 5 defines the control bits for

STS-1/STS-3c/STM-1. Tabl e 3- 6 defines the overhead bits for Line Framing/PHY Formats.

Bit

15 1 Enable External

14 1 All-Zeros FEBE Inserts an all-0s value in the FEBE field. The all-0s value provides an indication at

13 1 All-1s FEBE Inserts an all-1s value in the FEBE field of the transmit frame. The all-1s value

12–10 3 BIP Error Insert Selects the BIP field that will be errored with the TXFEAC_ERRPAT register

Field

Size

Name Description

Enables all overhead octets to be inserted externally in STS-1/STS-3c/STM-1 and

Overhead

G.832 E3/E4 modes. If this bit is not set, internal generation of overhead octets is enabled as described in Section 2.3.

the far end that no BIP-8 errors are being detected. BIP-8 status and error counts are not affected. This control bit is active in all modes whether the FEBE field is single- or multi-bit.

notifies the far end that the FEBE function is inhibited. BIP-8 status and error counts are not affected. This control bit is active in all modes whether the FEBE field is single- or multi-bit.

according to the following:

Bit 12 Bit 11 Bit 10 BIP Field to be Errored

0 0 0 No errors inserted

0 0 1 B1 field (all modes)

0 1 0 B2 field, bits 23:16 (STS-3c/STM-1 mode only)

0 1 1 B2 field, bits 15:8 (STS-3c/STM-1 mode only)

1 0 0 B2 field, bits 7:0 (STS-1/STS-3c/STM-1 modes)

1 0 1 B3 field (STS-1/STS-3c/STM-1 modes)

1 1 0 No errors inserted

1 1 1 B2 field, all 3 octets (STS-3c/STM-1 mode)

These bits are cleared by the transmitter after the error is inserted in the overhead field, and can be read as 0 to verify that error insertion has taken place.

9–4 6 Transmit Alarm

Control

3–0 4 Overhead Control Selectively disables overhead generation. Standard overhead is generated internally

Controls the generation of alarms for 57-octet PLCPs and internal framers. No alarms are transmitted if all bits in this control field are set to 0. Setting any of these bits to a 1 causes an alarm to be transmitted according to Tab le 3- 4 and Ta ble 3-5. For example, in STS-3c mode, setting bit 4 to a 1 will cause the Line AIS alarm to be transmitted.

if all bits in this control field are set to 0. Overhead sources for all PHY modes are given in Table 2-8. When a particular overhead field is set to be disabled, it will be filled with 0s. Overhead generation is disabled dependent on mode, according to the data in Tab le 3- 6.

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3.0 Registers CN8223

3.3 Configuration Control Registers ATM Transmitter/Receiver with UTOPIA Interface

Table 3-4. Alarm Transmission

Line Framing/PHY Format Alarm Control 7 Alarm Control 6 Alarm Control 5 Alarm Control 4

53-Octet DS1, E1 Modes Not Used Not Used Not Used Not Used

57-Octet External (PHY types 0–3) G1 Yellow (PLCP) Not Used Not Used Not Used

57-octet Internal DS3 Mode G1 Yellow (PLCP) X-Bit Yellow Idle Code AIS

57-octet Internal G.751 E3 Mode G1 Yellow (PLCP) A-Bit Yellow Not Used AIS

E3/E4 G.832 (PHY types 4–5) Not Used MA Timing Marker MA FERF AIS

53-octet Internal DS3 mode Not Used X-Bit Yellow Idle code AIS

Table 3-5. Alarm Transmission—STS–1/STS–3c/STM–1

STS-1/STS-3c/STM-1 (PHY Types 6-7) Alarm Control Bit

Line AIS Alarm Control 4

Line FERF Alarm Control 5

Path Yellow Alarm Control 6

Path FERF Alarm Control 7

Path AIS Alarm Control 8

SPE Unequipped Alarm Control 9

Table 3-6. Overhead Generation Disable

Line Framing/PHY Format Overhead Bit 3 Overhead Bit 2 Overhead Bit 1 Overhead Bit 0

57-Octet Modes (PHY types 0–3) A1, A2, Pn B1 C1 Trailer Bits

E3/E4 G.832 (PHY types 4–5) A1, A2 EM MA Not Used

STS-1/STS-3c/STM-1 (PHY types 6–7) A1, A2 B1, B2, B3 H1, H2, H3, H4 C1, C2

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CN8223 3.0 Registers

ATM Transmitter/Receiver with UTOPIA Interface

3.3 Configuration Control Registers

0x02—CONFIG_3 (Configuration Control Register 3)

The CONFIG_ 3 register is located at address 0x02 and controls miscellaneous functions.

Bit

15–12 4 Accept/Reject

11 1 Count Block Errors Changes the count function of Error Counters 5–9 [0x44–0x48]. When this bit is

10 1 Reserved Set to 0.

9 1 Line Loopback Enables a loopback of the incoming receive data and clock to the transmit data and

Field

Size

Name Description

Allows each receive port to be programmed to either accept or reject cells with

Header–Port 3–0

headers as specified in the RXHDR registers. When this bit is low, cells with headers matching the header value (as qualified by the mask value) for the port will be accepted and written out to the port. When this bit is high, cells with matching headers (as qualified by the mask value) will be rejected, and all other cells will be accepted and written out to the port.

low, the counters count the actual number of errored bits in the BIP or FEBE octets. When this bit is high, the counters increment once for each errored BIP or FEBE block per G.826.

clock outputs. The receive data is still processed by the receiver circuitry. Invert TX Clock Output (bit 7) is functional in this mode to allow inversion of the looped clock at TCLKO (or TCLKO_HS±). Line Loopback is not functional for TAXI or external framer modes. Upon a hardware RESET (pin 118), this bit will be cleared (set to 0).

8 1 Invert RX Clock

Sampling

7 1 Invert TX Clock

Output

6 1 For DS3 and G.751

E3 PLCP modes: Force Nibble Stuffing

6 1 For STS-3c and

STM-1 modes: Tx Overhead Control

Selects the edge of the receive clock input where the incoming receive data is sampled. When this bit is low, the incoming data on RXIN (or RXIN_HS±) is sampled by the falling edge of RXCKI (or RXCKI_HS±). When this bit is high, the incoming data is sampled on the rising edge. This bit must be set for operation in TAXI mode.

Selects the active edge of the transmit clock output when connecting directly to an external LIU. When this bit is low, the falling edge of TCLKO (or TCLKO_HS±) will be centered on the relevant data outputs. When this bit is high, the rising edge of TCLKO (or TCLKO_HS±) will be centered on the data outputs.

If this bit is low, 13/14 nibble stuffing is performed in DS3 and G.751 E3 PLCP modes. Stuffing is performed to synchronize the transmit PLCP with either the external 8 kHz frame reference or the receive PLCP framer, depending on the setting of External 8 kHz Timing in the CONFIG_1 register.

If this bit is high, the transmitter PLCP framing is allowed to free-run to an internally generated 8 k frame rate when no clock is available from the 8 kHz input or the receive PLCP framer. This bit is ignored in modes that do not perform nibble stuffing.

In STS-3c and STM-1 modes, this bit determines whether Transmit Overhead bytes G1, K2#1, and Z2#3 are input from the Transmit Overhead bus or are internally generated.

When this bit is set to 0 the following are internally generated:

• G1-Path FEBE/RDI—Path FEBE is automatically generated in response to Path BIP errors.

• Path RDI (yellow alarm) is inserted according to CONFIG_5, bits 2 and 3.

• K2#1—Line FERF is transmitted by setting CONFIG_2 bit 5 to a 1.

• Z2#3—Line FEBE alarm is transmitted automatically in response to Line

BIP errors.

When this bit is set to 1, these bytes are obtained from the external TXOVH bus.

5 1 Parity Odd/Even Set to 1: odd parity FIFO port generation and checking.

Set to 0: even parity FIFO port generation and checking.

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3.0 Registers CN8223

3.3 Configuration Control Registers ATM Transmitter/Receiver with UTOPIA Interface

Bit

4 1 Check Input Parity Enables parity checking at the FIFO port inputs. This bit must be enabled for the

3 1 Disable Write

21Enable DS1 PRS

1 1 HEC Coverage Determines the calculation range for the HEC. If this bit is low, the HEC is calculated

01Enable HEC Coset

Field

Size

Name Description

input parity error status bits or interrupts to be active.

Inhibits the receive port FIFO write strobes when a cell is determined to be invalid Strobes on Invalid Cells

Generator

for use with generic FIFOs.

Causes the physical layer data content to be replaced by a quasi-random signal

stream. This stream is used for certain transmission tests in DS1 systems.

over header octets 1–4 for ATM cells. If this bit is high, the HEC is calculated over

header octets 2–4 for SMDS/802.6 cells.

Enables the x

to transmission and prior to error detection/correction if HEC is internally

generated. For TAXI mode, enable HEC Coset must be active.

+ x4 + x2 + 1 polynomial to be XOR’ed with the calculated HEC prior

0x29—CONFIG_4 (Configuration Control Register 4)

The CONFIG_ 4 register is located at address 0x29 and controls miscellaneous functions.

Bit

Field

Size

Name Description

15-12 4 Disable CRC

Check-Ports 3–0

11-8 4 Disable Length

Check-Ports 3–0

7-4 4 Disable Port

Reception-Ports 3–0

31Enable TAXI

Interface

2 1 Delete Idle Cells Allows the screening of cells matching the receive idle header and mask criteria

1 1 Enable External

Section Trace

0 1 STM-1/STS-3c

Pointer

Disables the payload CRC check on a per-port basis. This disable controls only the output of cells to the FIFO interface and does not control the counting of payload CRC errors. (Counts are performed collectively, not per port.)

Disables the payload length check on a per-port basis. This disable controls only the output of cells to the FIFO interface and does not control the counting of payload length errors. (Counts are performed collectively, not per port.)

Disables the output of any received cells on a per-port basis. This disable control is internally synchronized to cell boundaries so that no partial cells are output on a port.

Enables an interface specific to 100 Mbps 4B/5B data transceivers on the parallel interface port. This interface is detailed in Section 2.5.1.

from appearing on the outputs of any of the receive ports. When this bit is low, idle cells are not automatically screened from port output. When this bit is high, idle cells are screened from output on the receive FIFO port.

Allows the section trace octet (C1) to be inserted externally. When this bit is low, the C1 octet is generated internally. When this bit is high, the C1 octet is inserted from the TXOVH input bus.

Enables the SS bits to be generated in the AU-4 pointer for STM-1 compatibility. When this bit is low, an STS-3c H1/H2 pointer is generated by the transmitter (no SS

bits present) and the C2 AU-4 pointer is generated with the SS bits set to 10.

(1)

octet

has the value 0x13. When this bit is high, an STM-1

NOTE(S):

(1)

The C2 octet is the STS Path Signal Label. It is allocated to indicate the content of the STS SPE, including the status of the mapped payloads.

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CN8223 3.0 Registers

ATM Transmitter/Receiver with UTOPIA Interface

3.3 Configuration Control Registers

0x31—CONFIG_5 (Configuration Control Register 5)

The CONFIG_5 register is located at address 0x31 and controls miscellaneous functions. Bits 3–0 are control bits which can be written and read. Bits 10, 9, and 8 are read-only status bits.

Bit

15–11 5 Reserved Set to 0.

10 1 Receive G1 Bit 5 Indicates the value of the RDI qualifier bit being received in the G1 octet of the

9 1 Receive G1 Bit 6 Indicates the value of the RDI qualifier bit being received in the G1 octet of the

8 1 Receive G1 Bit 7 Indicates the value of the RDI qualifier bit being received in the G1 octet of the

Field

Size

Name Description

STS-3c/STM-1 frame. This bit would be used in conjunction with bit 4 in the LINE_STATUS register [0x38] to determine the type of RDI (Path Yellow) being received.

7 1 Bt8222: Reserved

for Bt8222B and higher including the CN8223: Reset

6 1 Set G1 X Bits All-1s Sets the X bits in the G1 octet of the PLCP overhead to all 1s when this bit is high.

5 1 Enable HDLC Data

Link

4 1 Reserved Set to 0.

3 1 Transmit G1 Bit 5 Controls the transmission of the qualified RDI signals in the path status octet (G1) in

2 1 Transmit G1 Bit 6 Controls the transmission of the qualified RDI signals in the path status octet (G1) in

1 1 Enable External

Signal Label

0 1 Transmit Clock

Select

Set to 0. In Bt8222 revision B and higher, this bit is a software reset. Writing this bit to 1 has the same affect as high logic level on pin 118, RESET.

When this bit is low, the X bits will be all 0s.

Enables the internal HDLC data link receiver and transmitter. Programming for the HDLC data link is described in Section 2.8.

SONET/SDH modes. The value written to this bit will be placed in the corresponding bit of the G1 octet.

Selects the source for the C2 octet in the path overhead for SONET/SDH formats. When this bit is low, the C2 octet is internally generated. When this bit is high, the C2 octet is obtained from the TXOVH inputs.

Selects the clock source for the transmitter circuitry. When this bit is low, the transmit clock is from the TXCKI or TXCKI_HS± inputs. When this bit is high, the transmit clock is from the RXCKI or RXCKI_HS± inputs to enable loop timing.

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3.0 Registers CN8223

3.3 Configuration Control Registers ATM Transmitter/Receiver with UTOPIA Interface

0x2B—UTOPIA_1 (Utopia Port Control Register 1)

The UTOPIA_1 register is located at address 0x2B and controls operation of the UTOPIA interface. Operation of the UTOPIA interface is detailed in Section 2.7.5.

Bit

15–7 9 Reserved Set to 0.

6 1 Reset TX FIFO Resets the address generators and flags associated with the transmit FIFO when

5 1 Reset RX FIFO Resets the address generators and flags associated with the receive FIFO when this

4 1 Reserved Set to 0.

3, 2 2 Flag Threshold Selects the cell look-ahead level for asserting the TxFull~/TxClav flag to the ATM

Field

Size

Name Description

this bit is set high. This bit should be set high when Enable UTOPIA Interface (bit 0) is first set high, then written low after ATM and PHY layer initialization is complete. While the CN8223 is being initialized, its bit should be held low. Before setting this bit high, the ATM layer UTOPIA interface control lines must be in an inactive state. If they are not, the CN8223 UTOPIA FIFO pointers could become corrupted. To conserve power, write this bit high if the UTOPIA interface is not used.

bit is set high. This bit should be set high when the Enable UTOPIA Interface control bit is first set high and can then be written low after ATM and PHY layer initialization is complete. While the CN8223 is being initialized, this bit should be held low. Before setting this bit high, the ATM layer UTOPIA interface control lines must be in an inactive state. If they are not, the CN8223 UTOPIA FIFO pointers could become corrupted. To conserve power, this bit should be written high if the UTOPIA interface is not used.

layer. The control bits and flag look-ahead are as follows:

Octet/Cell

Handshake Flag Threshold TxFull~/TxClav Look-Ahead

0 x Full after 4 more octets

1 00 (Two-cell look-ahead) Full after current cell + 2 cells

1 01 (Single cell look- ahead) Full after current cell + cell

1 10 or 11 (Normal mode) Full after current cell

1 1 Octet/Cell

Handshake

0 1 Enable UTOPIA

Interface

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Selects the full flag handshake protocol for the FIFO buffers. If this bit is low, then octet-level handshaking is selected and the flags supplied are TxFull~ and RxEmpty~. If this bit is high, then cell-level handshaking is selected, and the flags supplied are TxClav and RxClav. In octet-handshake mode, the RxClav flag goes active after one full cell is in the receive UTOPIA FIFO. Also in this mode, when the 256-byte transmit UTOPIA FIFO has 252 bytes filled, TxClav goes active, indicating that only four bytes of space remain.

Selects the interface type on the FIFO I/O pins. If this bit is low, the interface is the standard four-port FIFO interface. If this bit is high, then the interface is a single-port UTOPIA-compliant interface controlled by the Port 0 Control Registers.

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CN8223 3.0 Registers

ATM Transmitter/Receiver with UTOPIA Interface

Use the following steps to initialize the CN8223 for proper UTOPIA port operation:

1. Put RS8234 in the global reset: write 0x40000000 to CONFIG0.

2. Write RS8234’s CONFIG0 to appropriate values, but do not overwrite the

GLOBAL_RESET bit.

3. Put CN8223 in the reset mode: write 0x0080 to CONFIG_5.

4. Initialize CN8223, including UTOPIA interface if needed.

5. Release CN8223 reset: write 0x0000 to CONFIG_5.

6. Release RS8234 reset: set GLOBAL_RESET bit to 0.

7. Enable RS8234’s Reassembly coprocessor.

8. Enable CN8223’s Receiver: write 0x0C02 to CELL_VAL register.

9. Enable RS8234’s Segmentation coprocessor.

0x2C—UTOPIA_2 (Utopia Port Control Register 2)

The UTOPIA_2 register is located at address 0x2C and controls operation of the UTOPIA interface.

Bit

15–6 10 Reserved Set to 0.

Field

Size

Name Description

3.3 Configuration Control Registers

5–0 6 Reserved Set to 35 hex.

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3.4 Transmit Control Registers ATM Transmitter/Receiver with UTOPIA Interface

3.4 Transmit Control Registers

0x03—TXFEAC_ERRPAT (Transmit FEAC/Error Pattern Register)

The TXFEAC_ERRPAT register is located at address 0x03. The eight MSBs control the FEAC channel used for DS3. Programming of the FEAC channel is discussed in Section 2.8.

The eight LSBs of this register insert BIP-8 errors in the transmitted PLCP, G.832, or SONET overhead or HEC errors in the cell header for end-to-end testing. The error pattern is XOR’ed with the selected field that is to be errored.

Bit

15–10 6 Transmit FEAC Data Six bits of serial data.

9 1 Enable FEAC

8 1 Enable Receive

7–0 8 Error Insertion

Field

Size

Name Description

Enables FEAC transmission; message is transmitted 10 times. Interrupt on DL_INT

Transmission

FEAC Interrupt

Pattern

when done.

Turns on the interrupt for the FEAC receive.

BIP-8 errors for PLCP, G.832, or SONET.

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