Page 1
DISCRETE SEMICONDUCTORS
DATA SH EET
BSP120
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Page 2
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a
miniature SOT223 envelope and
designed for use as a line current
interrupter in telephone sets and for
application in relay, high-speed and
line-transformer drivers.
FEATURES
• Direct interface to C-MOS, TTL,
etc.
• High-speed switching
• No secondary breakdown
QUICK REFERENCE DATA
Drain-source voltage V
Drain-current (DC) I
Drain-source ON-resistance
ID= 250 mA; VGS= 10 V R
Gate threshold voltage V
PINNING - SOT223
1 = gate
2 = drain
3 = source
4 = drain
Marking code
BSP120
DS
D
DS(on)
GS(th)
BSP120
max. 200 V
max. 250 mA
typ.
max.
max. 2.8 V
712Ω
Ω
PIN CONFIGURATION
handbook, halfpage
Top view
Fig.1 Simplified outline and symbol.
4
123
MAM054
d
g
s
April 1995 2
Page 3
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSP120
D-MOS transistor
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage V
Gate-source voltage (open drain) ±V
Drain current (DC) I
Drain current (peak) I
Total power dissipation up to T
=25°C (note 1) P
amb
Storage temperature range T
Junction temperature T
DS
GSO
D
DM
tot
stg
j
THERMAL RESISTANCE
From junction to ambient (note 1) R
th j-a
Note
1. Device mounted on an epoxy printed-circuit board 40 mm × 40 mm × 1.5 mm; mounting pad for the drain lead
min. 6 cm
2
.
max. 200 V
max. 20 V
max. 250 mA
max. 800 mA
max. 1.5 W
−65 to + 150 °C
max. 150 °C
= 83.3 K/W
CHARACTERISTICS
=25°C unless otherwise specified
T
j
Drain-source breakdown voltage
I
=10µA; VGS=0 V
D
Drain-source leakage current
VDS=160 V; VGS=0 I
Gate-source leakage current
V
= 20 V; VDS=0 I
GS
Drain-source ON-resistance (see Fig.4)
ID= 250 mA; VGS= 10 V R
Gate threshold voltage
= 1 mA; VGS=V
I
D
DS
Transfer admittance
= 250 mA; VDS= 15 V Yfs
I
D
Input capacitance at f = 1 MHz;
= 10 V; VGS=0 C
V
DS
(BR)DSS
DSS
GSS
DS(on)
V
GS(th)
iss
min. 200 V
max. 1.0 µA
max. 100 nA
typ.
max.
min.
max.
min.
typ.
typ.
max.
712Ω
Ω
0.8
2.8VV
125
250mSmS
4565pF
pF
Output capacitance at f = 1 MHz;
= 10 V; VGS=0 C
V
DS
April 1995 3
oss
typ.
max.
2030pF
pF
Page 4
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
Feedback capacitance at f = 1 MHz;
= 10 V; VGS= 0 C
V
DS
Switching times (see Figs 2 and 3)
I
= 250 mA; VDD= 50 V;
D
VGS= 0 to 10 V t
handbook, halfpage
10 V
0 V
50 Ω
VDD = 50 V
I
D
MBB691
rss
on
t
off
handbook, halfpage
INPUT
OUTPUT
typ.
max.
typ.
max.
typ.
max.
10 %
t
on
90 %
510pF
36ns
1520ns
90 %
BSP120
pF
ns
ns
t
off
10 %
MBB692
3
10
handbook, halfpage
I
D
(mA)
2
10
10
Fig.2 Switching time test circuit.
VGS = 10 V
5 V
4 V
81012
R
DSon
Fig.4 Tj=25°C; typical values.
MDA738
(Ω)
Fig.3 Input and output waveforms.
8
VGS (V)
MDA739
handbook, halfpage
144 6
1
I
D
(A)
0.8
0.6
0.4
0.2
0
010
246
Fig.5 Tj=25°C; VDS= 10 V; typical values.
April 1995 4
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Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
8
VDS (V)
MDA740
5 V
4 V
3 V
handbook, halfpage
1
I
D
(A)
0.8
0.6
0.4
0.2
0
010
VGS = 10 V
246
handbook,
P
(W)
2
tot
1.6
1.2
0.8
0.4
0
0 50 100 200
150
T
amb
BSP120
MBB693
(°C)
handbook, halfpage
3
k
2.5
2
1.5
1
0.5
−50 0 50
Fig.8
Fig.6 Tj=25°C; typical values.
100
Tj (°C)
DSon
at T
j
at 25 °C
;=
R
-----------------------------------------
k
R
DSon
at 250 mA/10 V; typical values.
MDA742
150
1.2
handbook, halfpage
k
1.1
1
0.9
0.8
0.7
−50 0 50
Fig.9
Fig.7 Power derating curve.
100
GS th()
at 25 °C
at T
j
;=
V
---------------------------------------------
k
V
GS th()
V
at 1 mA; typical values.
GS(th)
MDA743
Tj (°C)
150
April 1995 5
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Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
C
iss
C
oss
C
rss
VDS (V)
MDA744
120
handbook, halfpage
C
(pF)
80
40
0
010 30
20
BSP120
Fig.10 Tj=25°C; VGS= 0; f = 1 MHz; typical values.
April 1995 6
Page 7
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSP120
D-MOS transistor
PACKAGE OUTLINE
Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223
D
c
y
b
1
4
E
H
E
AB
X
v M
A
132
e
1
e
DIMENSIONS (mm are the original dimensions)
UNIT A1b
mm
A
1.8
1.5
OUTLINE
VERSION
SOT223
0.10
0.01
cD
b
p
1
0.80
3.1
2.9
0.32
0.22
0.60
IEC JEDEC EIAJ
b
6.7
6.3
p
w M
B
0 2 4 mm
scale
e1HELpQywv
e
E
3.7
3.3
REFERENCES
4.6
2.3
7.3
6.7
A
1.1
0.7
Q
A
1
L
p
detail X
0.95
0.85
0.1 0.10.2
EUROPEAN
PROJECTION
ISSUE DATE
96-11-11
97-02-28
April 1995 7
Page 8
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSP120
D-MOS transistor
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
April 1995 8
Page 9
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
NOTES
BSP120
April 1995 9
Page 10
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
NOTES
BSP120
April 1995 10
Page 11
Philips Semiconductors Product specification
N-channel enhancement mode vertical
D-MOS transistor
NOTES
BSP120
April 1995 11
Page 12
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Printed in The Netherlands 137107/1200/01/pp12 Date of release: April 1995 Document order number: 9397 750 02471
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