Datasheet BSP110 Datasheet (Philips)

Page 1
DISCRETE SEMICONDUCTORS
DATA SH EET
BSP110
N-channel enhancement mode vertical D-MOS transistor
Product specification File under Discrete Semiconductors, SC13b
April 1995
Page 2
Philips Semiconductors Product specification
N-channel enhancement mode vertical D-MOS transistor
DESCRIPTION
N-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and designed for use in telephone ringer circuits and for application in relay, high-speed and line transformer drivers.
FEATURES
Direct interface to C-MOS, TTL, etc.
High-speed switching
No secondary breakdown
PINNING - SOT223
1 = gate 2 = drain 3 = source 4 = drain
QUICK REFERENCE DATA
Drain-source voltage V Drain source voltage
(non-repetitive peak; tp≤ 2 ms) V Gate-source voltage (open drain) ± V Drain current (DC) I Total power dissipation up to T Drain-source ON-resistance
ID= 200 mA; VGS=10V R
Transfer admittance
= 200 mA; VDS=15V Yfs
I
D
=25°CP
amb
DS
DS(SM)
GSO
D
tot
DS(on)
BSP110
max. 80 V
max. 100 V max. 20 V max. 325 mA max. 1.5 W
typ. max.
min. typ.
4.57Ω
75
150mSmS
MARKING CODE
BSP110
PIN CONFIGURATION
handbook, halfpage
Top view
4
123
MAM054
d
g
s
Fig.1 Simplfied outline and symbol.
Page 3
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSP110
D-MOS transistor
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage V
DS
Drain-source voltage
(non-repetitive peak; t Gate-source voltage (open drain) ± V Drain current (DC) I Drain current (peak) I Total power dissipation up to T Storage temperature range T Junction temperature T
2 ms) V
p
=25°C (note 1) P
amb
DS(SM)
GSO D DM
tot stg j
THERMAL RESISTANCE
From junction to ambient (note 1) R
th j-a
Note
1. Device mounted on an epoxy printed-circuit board 40 mm × 40 mm × 1.5 mm; mounting pad for the drain lead min.
2
6 cm
.
max. 80 V
max. 100 V max. 20 V max. 325 mA max. 650 mA max. 1.5 W
65 to + 150 °C
max. 150 °C
= 83.3 K/W
CHARACTERISTICS
=25°C unless otherwise specified
T
j
Drain-source breakdown voltage
=10µA; VGS=0 V
I
D
Drain-source leakage current
V
= 60 V; VGS=0 I
DS
Gate-source leakage current
V
= 20 V; VDS=0 I
GS
Gate threshold voltage
ID= 1 mA; VDS=V
GS
Drain-source ON-resistance (see Fig.4)
= 150 mA; VGS=5V R
I
D
ID= 200 mA; VGS=10V R
Transfer admittance
ID= 200 mA; VDS=5V | Yfs|
Input capacitance at f = 1 MHz;
= 10 V; VGS=0 C
V
DS
(BR) DSS
DSS
GSS
I
GS(th)
DS(on)
DS(on)
iss
min. 80 V
max. 1.0 µA
max. 100 nA
min. max.
typ. max.
typ. max.
min. typ.
typ. max.
0.8
2.8VV
710Ω
4.57Ω
75
150mSmS
1530pF
pF
Page 4
Philips Semiconductors Product specification
N-channel enhancement mode vertical D-MOS transistor
Output capacitance at f = 1 MHz;
= 10 V; VGS=0 C
V
DS
Feedback capacitance at f = 1 MHz;
= 10 V; VGS=0 C
V
DS
Switching times (see Figs 2 and 3)
I
= 200 mA; VDD=50V;
D
VGS= 0 to 10 V t
BSP110
oss
rss
on
t
off
typ. max.
typ. max.
typ. max.
typ. max.
1320pF
pF
36pF
pF
25ns
ns
510ns
ns
handbook, halfpage
10 V
0 V
VDD = 50 V
I
D
50
MBB691
Fig.2 Switching time test circuit.
handbook, halfpage
INPUT
OUTPUT
Fig.3 Input and output waveforms.
10 %
t
on
90 %
90 %
10 %
t
off
MBB692
Page 5
Philips Semiconductors Product specification
N-channel enhancement mode vertical D-MOS transistor
8 V
R
DSon
MDA731
6 V
5 V
100 2
()
3
10
handbook, halfpage
I
D
(mA)
2
10
10
VGS = 10 V
468
handbook, halfpage
1
I
D
(A)
0.8
0.6
0.4
0.2
0
010
VDS = 10 V
246
BSP110
MDA732
5 V
8
VGS (V)
handbook, halfpage
1
I
D
(A)
0.8
0.6
0.4
0.2
0
010
Fig.4 Tj=25°C; typical values.
VGS = 10 V
8 V
7 V
6 V
5 V
4 V
3 V
246
8
VDS (V)
MDA733
handbook,
P (W)
Fig.5 Tj=25°C; typical values.
2
tot
1.6
1.2
0.8
0.4
0
0 50 100 200
150
T
amb
MBB693
(°C)
Fig.6 Tj=25°C; typical values.
Fig.7 Power derating curve.
Page 6
Philips Semiconductors Product specification
N-channel enhancement mode vertical D-MOS transistor
100
MDA735
Tj (°C)
150
handbook, halfpage
3
k
2.5
2
1.5
1
0.5
50 0 50
Fig.8
k
typical values at 150 mA/5 V.
at T
R
DSon
--------------------------------------- -
R
DSon
j
at 25 °C
;=
1.2
handbook, halfpage
k
1.1
1
0.9
0.8
0.7
50 0 50
Fig.9
k
V
at T
V
GS(th)
----------------------------------------
V
GS(th)
at 1 mA; typical values.
GS(th)
j
at 25 °C
BSP110
MDA736
Tj (°C)
150
100
;=
50
handbook, halfpage
C
(pF)
40
30
20
10
0
010 30
Fig.10 Tj= 25 °C; VGS= 0; f = 1 MHz;
typical values.
MDA737
C
iss
C
oss
C
rss
20
V
(V)
DS
Page 7
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSP110
D-MOS transistor
PACKAGE OUTLINE
Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223
D
c
y
b
1
4
E
H
E
AB
X
v M
A
132
e
1
e
DIMENSIONS (mm are the original dimensions)
UNIT A1b
mm
A
1.8
1.5
OUTLINE VERSION
SOT223
0.10
0.01
cD
b
p
1
0.80
3.1
2.9
0.32
0.22
0.60
IEC JEDEC EIAJ
b
6.7
6.3
p
w M
B
0 2 4 mm
scale
e1HELpQywv
e
E
3.7
3.3
REFERENCES
4.6
2.3
7.3
6.7
A
1.1
0.7
Q
A
1
L
p
detail X
0.95
0.85
0.1 0.10.2
EUROPEAN
PROJECTION
ISSUE DATE
96-11-11 97-02-28
Page 8
Philips Semiconductors Product specification
N-channel enhancement mode vertical
BSP110
D-MOS transistor
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
Page 9
Philips Semiconductors Product specification
N-channel enhancement mode vertical D-MOS transistor
NOTES
BSP110
Page 10
Philips Semiconductors Product specification
N-channel enhancement mode vertical D-MOS transistor
NOTES
BSP110
April 1995 10
Page 11
Philips Semiconductors Product specification
N-channel enhancement mode vertical D-MOS transistor
NOTES
BSP110
April 1995 11
Page 12
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Printed in The Netherlands 137107/00/01/pp12 Date of release: April 1995 Document order number: 9397 750 02469
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