Datasheet BS62UV1024TI, BS62UV1024TC, BS62UV1024STI, BS62UV1024STC, BS62UV1024SI Datasheet (BSI)

BSI

Ultra Low Power/Voltage CMOS SRAM 128K X 8 bit

BS62UV1024

 FEATURES

• Ultra low operation voltage : 1.8V ~ 3.6V

• Ultra low power consumption : Vcc = 2.0V C-grade : 10mA (Max.) operating current

I- grade : 15mA (Max.) operating current

0.01uA (Typ.) CMOS standby current

Vcc = 3.0V C-grade : 20mA (Max.) operating current

I- grade : 25mA (Max.) operating current

0.02uA (Typ.) CMOS standby current

• High speed access time :

-15 150ns (Max.) at Vcc = 2.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

 DESCRIPTION

The BS62UV1024 is a high performance, ultra low power CMOS Static Random Access Memory organized as 131,072 words by 8 bits and operates from a wide range of 1.8V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of

0.01uA and maximum access time of 150ns in 2V operation. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62UV1024 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62UV1024 is available in the JEDEC standard 32 pin 450mil Plastic SOP, 8mmx13.4mm STSOP 300mil Plastic SOJ and 8mmx20mm TSOP.

• Easy expansion with CE2, CE1, and OE options

 PRODUCT FAMILY

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

SPEED

(ns)

Vcc=

2.0V

BS62UV1024SC SOP BS62UV1024TC TSOP BS62UV1024JC SOJ BS62UV1024STC STSOP-32

O

C to +70OC1.8V ~ 3.6V+0 150 1.0uA 0.3uA 20mA 10mA

BS62UV1024PC PDIP BS62UV1024DC BS62UV1024SI SOP BS62UV1024TI TSOP BS62UV1024JI SOJ-32 BS62UV1024STI STSOP

O

-40

C to +85OC 1.8V ~ 3.6V 150 25mA 15mA

BS62UV1024PI PDIPBS62UV1024DI

 PIN CONFIGURATIONS

•

NC

1

A16

2

A14

3

A12

4

A7

5

A6

6

BS62UV1024SC BS62UV1024SI

A5

7

BS62UV1024PC

A4

8

BS62UV1024PI

A3

9

BS62UV1024JC

A2

10

BS62UV1024JI

A1

11

A0

12

DQ0

13

DQ1

14

DQ2

15

GND

16

•

1

A11

2

A9

3

A8

4

A13

5

WE

6

CE2

A15

VCC

A16 A14 A12

7 8 9

NC

10 11 12 13

A7

14

A6

15

A5

16

A4

BS62UV1024TC BS62UV1024STC BS62UV1024TI BS62UV1024STI

VCC

32

A15

31

CE2

30

WE

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23

CE1

22

DQ7

21

DQ6

20

DQ5

19

DQ4

18

DQ3

17

32

OE

31

A10

30

CE1

29

DQ7

28

DQ6

27

DQ5

26

DQ4

25

DQ3

24

GND

23

DQ2

22

DQ1

21

DQ0

20

A0

19

A1

18

A2

17

A3

 BLOCK DIAGRAM

A6

A7 A12 A14 A16 A15 A13

A8

A9 A11

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CE2 CE1

WE

OE Vdd

Gnd

POWER DISSIPATION

STANDBY

(ICCSB1, Max)

Vcc=

3.0V

Vcc=

2.0V

1.5uA 1uA

Address

Input

Buffer

8

Control

Operating

(ICC, Max)

Vcc=

3.0V

20

Row

Decoder

Data Input Buffer

Data

Output

Buffer

1024

8

Vcc=

2.0V

Memory Array

Column Decoder

Address Input Buffer

A4

A5

1024 x 1024

Column I/O

Write Driver

Sense Amp

A3 A2 A1 A0 A10

PKG TYPE

-32

DICE

-32

32

DICE

1024

128

14

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS62UV1024

1

Revision 2.2 April 2001

BSI

 PIN DESCRIPTIONS

Name Function

BS62UV1024

A0-A16 Address Input

CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input

WE Write Enable Input

OE Output Enable Input

DQ0-DQ7 Data Input/Output

These 17 address inputs select one of the 131,072 x 8-bit words in the RAM

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when

data read from or write to the device. If either chip enable is not active, the device is

deselected and is in a standby power mode. The DQ pins will be in the high

impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

These 8 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Gnd

Power Supply

Ground

 TRUTH TABLE

MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT

Not selected

(Power Down)

Output Disabled H L H H High Z I

Read H L H L D

Write L L H X D

XHXX

XXL X

High Z I

OUT

IN

CCSB

I

, I

CCSB1

CC

 ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PARAMETER RATING UNITS

TERM

V

BIAS

T

STG

T

P

OUT

I

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

R0201-BS62UV1024

Terminal Voltage with Respect to GND

Temperature Under Bias -40 to +125

Storage Temperature -60 to +150

Power Dissipation 1.0 W

DC Output Current mA20

-0.5 to

Vcc+0.5

 OPERATING RANGE

RANGE

V

O

C

O

C

Commercial 0

Industrial -40

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

Input

IN

C

1. This parameter is guaranteed and not tested.

DQ

Capacitance Input/Output Capacitance

2

AMBIENT

TEMPERATURE

O

C to +70

O

(1)

O

C1.8V ~ 3.6V

C to +85

O

C1.8V ~ 3.6V

(TA = 25oC, f = 1.0 MHz)

VIN=0V 6 pF

I/O

V

=0V 8 pF

Vcc

Revision 2.2 April 2001

BSI

BS62UV1024

 DC ELECTRICAL CHARACTERISTICS ( TA = 0

PARAMETER

NAME

IL

V

IH

V

IL

I

IOL Output Leakage Current

VOL Output Low Voltage Vcc = Max, IOL = 1mA

VOH Output High Voltage Vcc = Min, IOH = -0.5mA

CC

I

CCSB

I

Standby Current-TTL

CCSB1

I

Standby Current-CMOS

PARAMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage Guaranteed Input High

(2)

Voltage

Input Leakage Current Vcc = Max, V

Vcc = Max, CE1= V OE = V

Operating Power Supply Current

CE1 = V

DQ

I

= 0mA, F = Fmax

CE1 = V

DQ

I

= 0mA, F = Fmax

CE1ЊVcc-0.2V, CE2Љ0.2V,

IN

Њ

V

o

C to + 70oC )

IN

= 0V to Vcc -- -- 1 uA

IH

I/O

, V

= 0V to Vcc

IL

, or CE2 = VIH,

IH

, or CE2 = VIL,

Vcc-0.2V or V

IH

, CE2= V

(3)

IN

Љ

0.2V

IL,

or

Vcc=2.0V

Vcc=3.0V

Vcc=2.0V

Vcc=3.0V

Vcc=2.0V

Vcc=3.0V

Vcc=2.0V

Vcc=3.0V

Vcc=2.0V

Vcc=3.0V

Vcc=2.0V

Vcc=3.0V

Vcc=2.0V

Vcc=3.0V

(1)

MAX.

-0.5 --

1.4

2.0

-- Vcc+0.2 V

-- -- 1 uA

-- -- 0.4 V

1.6

2.4

-- -- V

-- -- 10

-- -- 20

-- -- 0.5

-- -- 1

-- 0.01 0.3

-- 0.02 1

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

 DATA RETENTION CHARACTERISTICS ( TA = 0

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.

V

.

RC

o

C to + 70oC )

(1)

MAX. UNITS

DR

Vcc for Data Retention

CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V, V

IN Њ Vcc - 0.2V or VIN Љ 0.2V

1.5 -- -- V

0.6

0.8

UNITS

V

mA

uA

I

CCDR

t

CDR

t

R

1. Vcc = 1.5V, TA= + 25OC

2. t

= Read Cycle Time

RC

 LOW V

DATA RETENTION WAVEFORM (1) ( CE1 Controlled )

CC

Vcc

CE1

 LOW V

DATA RETENTION WAVEFORM (2) ( CE2 Controlled )

CC

Vcc

CE2

R0201-BS62UV1024

Data Retention Current

Chip Deselect to Data Retention Time

Operation Recovery Time

CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V, V

IN Њ Vcc - 0.2V or VIN Љ 0.2V

See Retention Waveform

Data Retention Mode

Vcc

t CDR

CE1 Vcc - 0.2V

Data Retention Mode

Vcc

VDR Њ 1.5V

t CDR

VIL

CE2 Љ 0.2V

3

≥

VDR 1.5V

≥

-- 0.02 0.3 uA

0---- ns

(2)

T

RC

Vcc

-- -- ns

t R

VIHVIH

Vcc

t R

VIL

Revision 2.2 April 2001

BSI

BS62UV1024

 AC TEST CONDITIONS

Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level

Vcc/0V 5ns

0.5Vcc

 AC TEST LOADS AND WAVEFORMS

2V

OUTPUT

INCLUDING JIG AND SCOPE

Vcc

GND

1333

100PF

FIGURE 1A

OUTPUT

10%

Ω

OUTPUT

Ω

2000

THEVENIN EQUIVALENT

ALL INPUT PULSES

90%

→

←

Ω800

→

2V

INCLUDING JIG AND SCOPE

10%

←

1333

5PF

FIGURE 1B

1.2V

5ns

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Ω

2000

o

C to + 70oC, Vcc=2.0V )

MUST BE STEADY

MAY CHANGE FROM H TO L

MAY CHANGE FROM L TO H

,

DON T CAR ANY CHANG PERMITTED

DOES NOT APPLY

MUST BE STEADY

WILL BE CHANGE FROM H TO L

WILL BE CHANGE FROM L TO H

E: CHANGE :

E STATE

UNKNOWN

CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

E1LQV

t

E2HOV

t

GLQV

t

E1LQX

t

E2HOX

t

GLQX

t

E1HQZ

t

E2HQZ

t

GHQZ

t

AXOX

PARAMETER

NAME

t

RC

t

AA

t

ACS1

t

ACS2

t

OE

t

CLZ1

t

CLZ2

t

OLZ

t

CHZ1

t

CHZ2

t

OHZ

t

OH

DESCRIPTION

Read Cycle Time

Address Access Time

Chip Select Access Time (CE1)

Chip Select Access Time (CE2)

Output Enable to Output Valid

Chip Select to Output Low Z (CE1)

Chip Select to Output Low Z (CE2)

Output Enable to Output in Low Z

Chip Deselect to Output in High Z (CE1)

Chip Deselect to Output in High Z (CE2)

Output Disable to Output in High Z

Output Disable to Output Address Change

BS62UV1024-15

MIN. TYP. MAX.

UNIT

150 -- -- ns

-- -- 150 ns

-- -- 100 ns

10 -- -- ns

0--40 ns

040

0--35 ns

10 -- -- ns

R0201-BS62UV1024

4

Revision 2.2 April 2001

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t AA

t OH

OUT

BS62UV1024

t RC

t OH

READ CYCLE2

CE1

CE2

D

OUT

READ CYCLE3

ADDRESS

OE

CE1

(1,3,4)

(1,4)

t CLZ

(5)

t ACS1

t ACS2

t CLZ1

(5)

t AA

t ACS1

t OLZ

t OE

t RC

(5)

t CHZ1, t CHZ2

t OH

(5)

t OHZ

(1,5)

t CHZ1

CE2

D

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = V

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = V

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.

R0201-BS62UV1024

IL .

The parameter is guaranteed but not 100% tested.

OUT

t ACS2

(5)

(2,5)

t CHZ2

t CLZ2

IL and CE2= VIH.

±

5

Revision 2.2 April 2001

BSI

BS62UV1024

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

E2LAX

t

WLOZ

t

DVWH

t

WHDX

t

GHOZ

t

WHQX

PARAMETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR1

t

WR2

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

DESCRIPTION

Write Cycle Time

Chip Select to End of Write

Address Set up Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time (CE1 , WE)

Write Recovery Time (CE2)

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

o

C to + 70oC, Vcc=2.0V )

BS62UV1024-15

MIN. TYP. MAX.

150 -- -- ns

0---- ns

150 -- -- ns

80 -- -- ns

0---- ns

-- -- 40 ns

50 -- -- ns

0---- ns

0--40 ns

5---- ns

UNIT

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

ADDRESS

OE

CE1

CE2

WE

(1)

(5)

t AS

(4,10)

t OHZ

D

OUT

t AW

t WC

t CW

t WP

(11)

(3)

t WR1

t WR2

(3)

(2)

t DH

t DW

D

IN

R0201-BS62UV1024

6

Revision 2.2 April 2001

BSI

BS62UV1024

WRITE CYCLE2

ADDRESS

CE1

CE2

WE

D

OUT

D

IN

(1,6)

t AS

(5)

(4,10)

t WHZ

t AW

t WC

t CW

t WP

(11)

t WR2

(3)

(2)

t DH

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. T

WR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write

cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7.

DOUT is the same phase of write data of this write cycle.

OUT is the read data of next address.

8. D

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

parameter is guaranteed but not 100% tested.

CW is measured from the later of CE1 going low or CE2 going high to the end of write.

11. T

IL ).

±

L = 5pF as shown in Figure 1B. The

R0201-BS62UV1024

7

Revision 2.2 April 2001

BSI

 ORDERING INFORMATION

BS62UV1024 X X ˀˀ Y Y

BS62UV1024

SPEED

15: 150ns

GRADE

C: +0oC ~ +70oC

o

C ~ +85oC

I: -40

PACKAGE

S: SOP T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) J : SOJ P: PDIP D : DICE

 PACKAGE DIMENSIONS

WITH PLATING

c c1

BASE METAL

b

b1

SECTION A-A

R0201-BS62UV1024

SOP -32

8

Revision 2.2 April 2001

BSI

 PACKAGE DIMENSIONS (continued)

BS62UV1024

STSOP - 32

R0201-BS62UV1024

TSOP - 32

9

Revision 2.2 April 2001

BSI

 PACKAGE DIMENSIONS (continued)

BS62UV1024

SOJ - 32

R0201-BS62UV1024

PDIP - 32

10

Revision 2.2 April 2001

BSI

BS62UV1024

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

R0201-BS62UV1024

11

Revision 2.2 April 2001