Page 1
BSI
Very Low Power/Voltage CMOS SRAM
1M X 8 bit
BS62LV8003
FEATURES
• Wide Vcc operation voltage : 2.4V ~ 3.6V
• Very low power consumption :
Vcc = 3V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max) at Vcc = 3V
-10 100ns (Max) at Vcc = 3V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
GENERAL DESCRIPTION
The BS62LV8003 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 words by 8 bits
and operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.5uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable(CE2) and active LOW output
enable (OE) and three-state output drivers.
The BS62LV8003 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV8003 is available in 44 pin TSOP2 and 48-pin BGA type.
• Easy expansion with CE1, CE2 and OE options
PRODUCT FAMILY
SPEED
PRODUCT
FAMILY
BS62LV8003EC TSOP2-44
BS62LV8003BC
BS62LV8003EI TSOP2-44
BS62LV8003BI
OPERATING
TEMPERATURE
Vcc
RANGE
( ns )
Vcc=3V Vcc=3V Vcc=3V
O
C to +70OC 2.4V ~ 3.6V 70 / 100 3uA 20mA
+0
O
-40
C to +85OC 2.4V ~ 3.6V 70 / 100 6uA 25mA
POWER DISSIPATION
STANDBY
( I , Max )
CCSB1
Operating
( I , Max )
CC
PKG TYPE
BGA-48-0810
BGA-48-0810
PIN CONFIGURATIONS
1
A4
2
A3
3
A2
4
A1
5
A0
6
CE1
7
NC
8
NC
9
DQ0
10
DQ1
VCC
GND
DQ2
DQ3
NC
NC
WE
A19
A18
A17
A16
A15
A
B
C
D
E
F
BS62LV8003EC
11
BS62LV8003EI
12
13
14
15
16
17
18
19
20
21
22
123456
OEA3A0
NC
NC
NC
NC
D0
VSS A17
VCC
D3
A5
D1
VCC
D2
NC
A14
A1 A2
A4
A6
A7
A16
A15
44
A5
43
A6
42
A7
41
OE
40
CE2
39
A8
38
NC
37
NC
36
DQ7
35
DQ6
34
GND
33
VCC
32
DQ5
31
DQ4
30
NC
29
NC
28
A9
27
A10
26
A11
25
A12
24
A13
23
A14
CE2
NC
CE1
D4
NC
VCC
D5
VSS
D6
NC
D7
FUNCTIONAL BLOCK DIAGRAM
A13
A17
A15
A18
A16
A14
A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
Vdd
Gnd
A7
A6
A5
A4
WE
OE
Address
Input
Buffer
8
8
Control
22
Row
Decoder
Data
Input
Buffer
Data
Output
Buffer
2048
8
8
Memory Array
2048 X 4096
4096
Column I/O
Write Driver
Sense Amp
512
Column Decoder
18
Address Input Buffer
A11A9 A8 A3 A2 A1 A0A10 A19
G
A18
H
A13
A12
A9A8
WE
NC
A19
A11A10
NC
NC
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV8003
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Revision 2.4
April 2002
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BSI
PIN DESCRIPTIONS
Name Function
BS62LV8003
A0-A19 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
These 20 address inputs select one of the 1,048,576 x 8-bit words in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc
Gnd
Power Supply
Ground
TRUTH TABLE
MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT
Not selected
(Power Down)
Output Disabled H L H H High Z I
Read H L H L D
Write L L H X D
XHXX
XXL X
High Z I
OUT
IN
CCSB
I
I
, I
CC
CC
CC
CCSB1
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL PARAMETER RATING UNITS
TERM
V
BIAS
T
STG
T
T
P
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS62LV8003
Terminal Voltage with
Respect to GND
Temperature Under Bias -40 to +125
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current mA20
-0.5 to
Vcc+0.5
O
O
OPERATING RANGE
RANGE
V
C
C
Commercial 0
Industrial -40
CAPACITANCE
SYMBOL PARAMETER CONDITIONS MAX. UNIT
C
C
1. This parameter is guaranteed and not tested.
IN
DQ
Input
Capacitance
Input/Output
Capacitance
2
AMBIENT
TEMPERATURE
O
O
(1)
(TA = 25oC, f = 1.0 MHz)
O
C to +70
C to +85
C2.4V ~ 3.6V
O
C2.4V ~ 3.6V
VIN=0V 10 pF
I/O
V
=0V 12 pF
Vcc
Revision 2.4
April 2002
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BSI
BS62LV8003
DC ELECTRICAL CHARACTERISTICS ( TA = 0
PARAMETER
NAME
IL
V
IH
V
IL
I
OL
I
OL
V
OH
V
CC
I
CCSB
I
CCSB1
I
PARAMETER TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current = 0V to VccVcc = Max, V
Output Leakage Current
Output Low Voltage = 2mAVcc = Max, I
Output High Voltage = -1mAVcc = Min, I
Operating Power Supply
Current
Standby Current-TTL CE1 = VIH, CE2= V
Standby Current-CMOS
Vcc = Max, CE1 = V
OE = V , V = 0V to
CE1= V
F = Fmax
CE1
Њ
IN
V
Њ
o
C to + 70oC )
IN
IH
IH I/O
OL
OH
IL
, CE2= V
(3)
or CE2 = V
Vcc
IH,IDQ
IL, IDQ
= 0mA,
= 0mA
Vcc-0.2V, CE2Љ0.2V
Vcc - 0.2V or V
IN
Љ
0.2V
IL
Vcc=3V
Vcc=3V
or
Vcc=3V
Vcc=3V
Vcc=3V
Vcc=3V
Vcc=3V
(1)
MAX.
-0.5 -- 0.8 V
2.0 -- Vcc+0.2 V
-- -- 1 uA
-- -- 1 uA
-- -- 0.4 V
2.4 -- -- V
-- -- 20 mA
-- -- 1 mA
-- 0.5 3 uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70
SYMBOL PAR A M ETER TEST CONDITIONS MIN. TYP.
V
.
RC
DR
Vcc for Data Retention
CE1ЊVcc - 0.2V or CE2 Љʳ 0.2V or
IN Њ
Vcc - 0.2V or V
V
o
C )
IN Љ
0.2V
(1)
MAX. UNITS
1.5 -- -- V
UNITS
I
CCDR
t
CDR
t
R
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
1. Vcc = 1.5V, TA= + 25OC
= Read Cycle Time
2. t
RC
LOW V
DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
CC
Vcc
CE1
LOW V
DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
CC
Vcc
CE2
CE1 Њ Vcc - 0.2V or CE2 Љʳ 0.2V
IN Њ Vcc - 0.2V or VIN Љ 0.2V
V
See Retention Waveform
Data Retention Mode
≥
Vcc
VDR 1.5V
t CDR
≥
CE1 Vcc - 0.2V
Data Retention Mode
Vcc
VDR Њ 1.5V
t CDR
VIL
CE2 Љ 0.2V
-- 0.4 2 uA
0 -- -- ns
(2)
T
RC
Vcc
-- -- ns
t R
VIHVIH
Vcc
t R
VIL
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Revision 2.4
April 2002
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BSI
BS62LV8003
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0
5ns
0.5Vcc
AC TEST LOADS AND WAVEFORMS
Ω
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
OUTPUT
Vcc
GND
1269
100PF
Ω
1404
FIGURE 1A
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
→
←
OUTPUT
Ω667
90%
90%
FIGURE 2
3.3V
INCLUDING
JIG AND
SCOPE
→
←
10%
1.73V
5ns
Ω
1269
5PF
1404
FIGURE 1B
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CAR
Ω
ANY CHANG
PERMITTED
DOES NOT
APPLY
E: CHANGE :
E STATE
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = 0
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
E2LQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time (CE1)
Chip Select Access Time (CE2)
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Output Disable to Output Address Change
o
C to + 70oC , Vcc = 3V )
BS62LV8003-70
MIN. TYP. MAX.
70 -- -- 100 -- -- ns
-- -- 70 -- -- 100 ns
-- -- 70 -- -- 100 ns
-- -- 70 -- -- 100 ns
-- -- 35 -- -- 50 ns
10 -- -- 15 -- -- ns
10 -- -- 15 -- -- ns
0 -- 35 0 -- 40 ns
0 -- 30 0 -- 35 ns
10 -- -- 15 -- -- ns
BS62LV8003-10
MIN. TYP. MAX.
UNIT
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Revision 2.4
April 2002
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BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
(1,2,4)
t AA
t OH
OUT
BS62LV8003
t RC
t OH
READ CYCLE2
CE2
CE1
D
OUT
READ CYCLE3
ADDRESS
OE
CE2
CE1
(1,3,4)
(1,4)
t CLZ
(5)
t ACS2
t ACS1
t CLZ
(5)
t AA
t ACS2
t OLZ
t ACS1
t OE
t RC
t OHZ
t CHZ
(1,5)
t CHZ
t OH
(5)
(5)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = V
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
R0201-BS62LV8003
IL .
The parameter is guaranteed but not 100% tested.
D
OUT
IL and CE2 = VIH.
±
5
Revision 2.4
April 2002
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BSI
BS62LV8003
AC ELECTRICAL CHARACTERISTICS ( TA = 0
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
WLOZ
t
DVWH
t
WHDX
t
GHOZ
t
WHQX
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Set up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
o
C to + 70oC , Vcc = 3.0V )
BS62LV8003-70
MIN. TYP. MAX.
70 -- -- 100 -- -- ns
70 -- -- 100 -- -- ns
0 -- -- 0 -- -- ns
70 -- -- 100 -- -- ns
35 -- -- 50 -- -- ns
(CE2,CE1 , WE)
0
-- -- 0 -- -- ns
0--300--40 ns
30 -- -- 40 -- -- ns
0 -- -- 0 -- -- ns
0--300--40 ns
5----10---- ns
t WC
BS62LV8003-10
MIN. TYP. MAX.
UNIT
ADDRESS
OE
CE2
CE1
WE
D
OUT
D
IN
t AS
(4,10)
t OHZ
(3)
t WR
(5)
(11)
(5)
t AW
t CW
t WP
(3)
(2)
t DH
t DW
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Revision 2.4
April 2002
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BSI
BS62LV8003
WRITE CYCLE2
ADDRESS
CE2
CE1
WE
D
OUT
D
IN
(1,6)
t AS
(5)
(4,10)
t WHZ
t AW
t WC
t CW
t WP
(11)
t WR
(3)
(2)
t DH
(7) (8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
WR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
3. T
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
7. D
OUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
The parameter is guaranteed but not 100% tested.
CW is measured from the later of CE2 going high or CE1 going low to the end of write.
11. T
IL ).
±
L = 5pF as shown in Figure 1B.
R0201-BS62LV8003
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Revision 2.4
April 2002
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BSI
ORDERING INFORMATION
BS62LV8003 X X ˀˀ Y Y
BS62LV8003
SPEED
70: 70ns
10: 100ns
GRADE
C: +0oC ~ +70oC
o
C ~ +85oC
I: -40
PACKAGE
E: TSOP2-44
B: BGA-48-0810
PACKAGE DIMENSIONS
R0201-BS62LV8003
TSOP2-44
8
Revision 2.4
April 2002
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BSI
PACKAGE DIMENSIONS (continued)
0.05
0.25
BS62LV8003
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
e
VIEW A
SIDE VIEW
D0.1
D1
48 mini-BGA (8 x 10mm)
N ED
48 10.0 8.0
0.1
E1
E
E1D1 e
3.755.25 0.75
SOLDER BALL 0.350.05
R0201-BS62LV8003
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Revision 2.4
April 2002
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BSI
BS62LV8003
REVISION HISTORY
Revision Description Date Note
2.2 2001 Data Sheet release Apr. 15, 2001
2.3 Modify Standby Current (Typ.
and Max.)
2.4 Modify some AC parameters April,11,2002
Jun. 29, 2001
R0201-BS62LV8003
10
Revision 2.4
April 2002
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