Page 1
BSI
Very Low Power/Voltage CMOS SRAM
512K X 8 bit
BS62LV4006
FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 29mA (@55ns) operating current
I -grade: 30mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
0.45uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 68mA (@55ns) operating current
I -grade: 70mA (@55ns) operating current
C-grade: 58mA (@70ns) operating current
I -grade: 60mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Fully static operation
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV4006TC
BS62LV4006STC
BS62LV4006SC
BS62LV4006EC
BS62LV4006PC
BS62LV4006TI
BS62LV4006STI
BS62LV4006SI
BS62LV4006EI
BS62LV4006PI
OPERATING
TEMPERATURE
RANGE
+0O C to +70O C 2.4V ~ 5.5V 55 / 70 5uA 30uA 24mA 58mA
-
40O C to +85O C 2.4V ~ 5.5V 55 / 70 10uA 60uA 25mA 60mA
Vcc
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• Three state outputs and TTL compatible
DESCRIPTION
The BS62LV4006 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.45uA at 3.0V/25
Easy memory expansion is provided by an active LOW chip enable
(CE) , and active LOW output enable (OE) and three-state output
drivers.
The BS62LV4006 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4006 is available in the JEDEC standard 32L SOP, TSOP
, PDIP, TSOP II and STSOP package.
SPEED
( ns )
55ns :3.0~5.5V
70ns :2.7~5.5V
Vcc = 3.0V
o
C and maximum access time of 55ns at 3.0V/85oC.
POWER DISSIPATION
STANDBY
CCSB1
( I
, Max )
Vcc =5.0V
Operating
( ICC, Max )
Vcc = 3.0V
70ns
Vcc =5.0V
70ns
TSOP-32
STSOP-32
SOP-32
TSOP2-32
PDIP
TSOP-32
STSOP-32
SOP-32
TSOP2-32
PDIP-32
PKG
TYPE
-
32
PIN CONFIGURATIONS
•
A18
A11
A13
A17
A15
VCC
A18
A16
A14
A12
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
BS62LV4006SC
8
BS62LV4006SI
A3
9
BS62LV4006EC
A2
10
BS62LV4006EI
A1
11
BS62LV4006PC
A0
12
DQ0
DQ1
DQ2
GND
•
1
2
A9
3
A8
4
5
WE
6
7
8
9
10
11
12
13
A7
14
A6
15
A5
16
A4
BS62LV4006PI
13
14
15
16
BS62LV4006TC
BS62LV4006STC
BS62LV4006TI
BS62LV4006STI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32
OE
31
A10
30
CE
29
DQ7
28
DQ6
27
DQ5
26
DQ4
25
DQ3
24
GND
23
DQ2
22
DQ1
21
DQ0
20
A0
19
A1
18
A2
17
A3
BLOCK DIAGRAM
A13
A17
A15
A18
A16
A14
A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A7
A6
A5
A4
CE
WE
OE
Vdd
GND
Address
Input
Buffer
22
8
8
Control
Decoder
Data
Input
Buffer
Data
Output
Buffer
Row
2048
8
8
A11 A9 A8 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS62LV4006
1
Memory Array
2048 X 2048
2048
Column I/O
Write Driver
Sense Amp
256
Column Decoder
16
Address Input Buffer
Revision 1.1
Jan. 2004
Page 2
BSI
PIN DESCRIPTIONS
Name Function
BS62LV4006
A0-A18 Address Input
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
These 19 address inputs select one of the 524,288 x 8-bit words in the RAM
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc
GND
Power Supply
Ground
TRUTH TABLE
MODE WE CE OE I/O OPERATION Vcc CURRENT
Not selected X H X High Z I
Output Disabled H L H High Z I
Read H L L D
Write L L X D
OUT
IN
CCSB
, I
CCSB1
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL PAR AME T ER RATING UNITS
TERM
V
BIAS
T
STG
T
PT
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS62LV4006
Terminal Voltage with
Respect to GND
Temperature Under Bias -40 to +85
Storage Temperature
Power Dissipation
DC Output Current 20 mA
-0.5 to
Vcc+0.5
-60 to +150
1.0 W
OPERATING RANGE
RANGE
V
O
C
O
C
Commercial 0
Industrial -40
CAPACITANCE
SYMBOL PARAMETER CONDITIONS MAX. UNIT
C
C
1. This parameter is guaranteed and not 100% tested.
IN
DQ
Input
Capacitance
Input/Output
Capacitance
AMBIENT
TEMPERATURE
O
O
(1)
(TA = 25oC, f = 1.0 MHz)
C to +70
C to +85
VIN=0V
V
O
C 2.4V ~ 5.5V
O
C 2.4V ~ 5.5V
I/O
=0V 8 pF
Vcc
6 pF
2
Revision 1.1
Jan. 2004
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BSI
BS62LV4006
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85
PARAMETER
NAME
IL
V
IH
V
IL
I
LO
I
OL
V
OH
V
(5)
CC
I
CCSB
I
(4)
CCSB1
I
PARAMETER TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(3)
Voltage
Guaranteed Input High
(3)
Voltage
Input Leakage Current Vcc = Max, V
Output Leakage Current
Output Low Voltage -- -- V
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
Standby Current-CMOS
Vcc = Max, CE = V
I/O
V
= 0V to Vcc
Vcc = Max, I
Vcc = Min, I
CE = V
F=Fmax
CE = V
CE ≧Vcc-0.2V,
IN
V
≧
IN
= 0V to Vcc -- -- 1 uA
OL
= 2.0mA
OH
= -1.0mA
IL
, IDQ= 0mA,
(2)
IH
, IDQ= 0mA -- --
Vcc - 0.2V or V
o
C )
IH
, or OE = VIH,
70ns
70ns
IN
0.2V
≦
Vcc = 3.0 V
Vcc = 5.0 V
Vcc = 3.0 V
Vcc = 5.0 V
Vcc = 3.0 V
Vcc = 5.0 V
Vcc = 3.0 V
Vcc = 5.0 V
Vcc = 3.0 V
Vcc = 5.0 V
Vcc = 3.0 V
Vcc = 5.0 V
Vcc = 3.0 V
Vcc = 5.0 V
(1)
MAX.
-0.5 --
2.0
2.2
-- Vcc+0.3 V
-- -- 1 uA
2.4
2.4
-- -- V
-- --
--
0.45
2.0
1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. I
ccSB1_MAX. is 5uA/30uA at Vcc=3.0V/5.0V and TA=70
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85
SYMBOL PAR AME T ER TEST CONDITIONS MIN. TYP.
V
DR
Vcc for Data Retention
o
C. 5. Icc_MAX. is 30mA(@3.0V)/70mA(@5.0V) under 55ns operation.
o
C )
(1)
MAX. UNITS
CE ≧ Vcc - 0.2V
IN ≧ Vcc - 0.2V or VIN ≦ 0.2V
V
1.5 -- -- V
0.8
0.8
0.4
0.4
25
60
0.5
1.0
10
60
UNITS
V
mA
mA
uA
I
CCDR
t
CDR
t
R
1. Vcc = 1.5V, TA= + 25OC
= Read Cycle Time
2. t
RC
3. I
ccDR_MAX. is 0.8uA at TA=70
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
O
C.
CE ≧ Vcc - 0.2V
IN
V
≧ Vcc - 0.2V or VIN ≦ 0.2V
See Retention Waveform
LOW VCCDATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
Vcc
CE
R0201-BS62LV4006
Vcc
t CDR
CE Vcc - 0.2V
3
≥
VDR 1.5V
≥
-- 0.3 1.3 uA
0 -- -- ns
(2)
T
RC
Vcc
-- -- ns
t R
VIHVIH
Revision 1.1
Jan. 2004
Page 4
BSI
BS62LV4006
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
Vcc / 0V
1V/ns
0.5Vcc
CL = 30pF+1TTL
= 100pF+1TTL
C
L
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
DESCRIPTION UNIT
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Data Hold from Address Change
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
o
C )
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
MIN. TYP. MAX.
55 -- -- 70 -- -- ns
-- -- 55 -- -- 70 ns
-- -- 55 -- -- 70 ns
-- -- 30 -- -- 35 ns
10 -- -- 10 -- -- ns
10 -- -- 10 -- -- ns
-- -- 30 -- -- 35 ns
-- -- 25 -- -- 30 ns
10 -- -- 10 -- -- ns
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
R0201-BS62LV4006
(1,2,4)
OUT
t OH
t AA
t RC
t OH
4
Revision 1.1
Jan. 2004
Page 5
BSI
BS62LV4006
READ CYCLE2
CE
D
OUT
READ CYCLE3
ADDRESS
OE
CE
D
OUT
(1,3,4)
(1,4)
t CLZ
t ACS
(5)
t CHZ
(5)
t RC
t AA
t OE
t OH
t OLZ
t OHZ
t CHZ
(5)
(1,5)
t CLZ
t ACS
(5)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
3. Address valid prior to or coincident with CE transition low.
4. OE = V
5. The parameter is guaranteed but not 100% tested.
R0201-BS62LV4006
IL .
IL.
5
Revision 1.1
Jan. 2004
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BSI
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
WLOZ
t
DVWH
t
WHDX
t
GHOZ
t
WHQX
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION UNIT
Write Cycle Time
Chip Select to End of Write
Address Set up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time (CE , WE)
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End ot Write to Output Active
BS62LV4006
o
C )
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
55 -- -- 70 -- -- ns
55 -- -- 70 -- -- ns
0 -- -- 0 -- -- ns
55 -- -- 70 -- -- ns
30 -- -- 35 -- -- ns
0 -- -- 0 -- -- ns
-- -- 25 -- -- 30 ns
25 -- -- 30 -- -- ns
0 -- -- 0 -- -- ns
-- -- 25 -- -- 30 ns
5 -- -- 5 -- -- ns
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
MIN. TYP. MAX.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
ADDRESS
OE
CE
WE
(1)
(5)
t AS
(4,10)
t OHZ
D
OUT
D
IN
t AW
t WC
t CW
t WP
(11)
(3)
t WR
(2)
t DH
t DW
R0201-BS62LV4006
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Revision 1.1
Jan. 2004
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BSI
BS62LV4006
WRITE CYCLE2
ADDRESS
CE
WE
D
OUT
D
IN
(1,6)
t AS
(5)
t AW
(4,10)
t WHZ
t WC
t CW
t WP
(11)
(2)
t OW
(7) (8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. T
WR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
7. D
OUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. T
CW is measured from the later of CE going low to the end of write.
R0201-BS62LV4006
IL ).
7
Revision 1.1
Jan. 2004
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BSI
BS62LV4006
ORDERING INFORMATION
BS62LV4006 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
o
I: -40
C ~ +85oC
PACKAGE
S: SOP
E: TSOP 2
ST: Small TSOP
T: TSOP
P: PDIP
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
SOP -32
WITH PLATING
c c1
BASE METAL
b
b1
SECTION A-A
R0201-BS62LV4006
8
Revision 1.1
Jan. 2004
Page 9
BSI
BS62LV4006
TSOP2 - 32
TSOP - 32
R0201-BS62LV4006
9
Revision 1.1
Jan. 2004
Page 10
BSI
PACKAGE DIMENSIONS (continued)
BS62LV4006
STSOP - 32
PDIP - 32
R0201-BS62LV4006
10
Revision 1.1
Jan. 2004
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