Datasheet BS62LV8005BC, BS62LV4005TI, BS62LV8005EI, BS62LV8005EC, BS62LV8005BI Datasheet (BSI)

BSI

Low Power/Voltage CMOS SRAM 512K X 8 bit

BS62LV4005

 FEATURES

• Vcc operation voltage : 4.5V ~ 5.5V

• Low power consumption Vcc = 5.0V C-grade: 45mA (Max.) operating current

I -grade: 50mA (Max.) operating current

1.5uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc = 5.0V

-55 55ns (Max.) at Vcc = 5.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

 PRODUCT FAMILY

PRODUCT

FAMILY

BS62LV4005SC BS62LV4005EC BS62LV4005TC BS62LV4005STC BS62LV4005PC BS62LV4005SI BS62LV4005EI BS62LV4005TI BS62LV4005STI BS62LV4005PI

OPERATING

TEMPERATURE

O

C to +70OC 55 / 70

+0

O

C to +85

4.5V ~ 5.5V 45mA

O

C4.5V ~-40

 PIN CONFIGURATIONS

 GENERAL DESCRIPTION

The BS62LV4005 is a high performance, low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with maximum access time of 55/ 70ns in 5V operation. Easy memory expansion is provided by active LOW chip enable (CE), active LOW output enable (OE) and three-state output drivers. The BS62LV4005 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV4005 is available in the JEDEC standard 32 pin SOP , TSOP, TSOP II and STSOP .

POWER DISSIPATION

STANDBY

(ICCSB1 , Max )

Vcc

RANGE

SPEED

(ns)

Vcc = 5.0V Vcc = 5.0V Vcc=5.0V

15uA

5.5V 55 / 70 25uA 50mA

 FUNCTIONAL BLOCK DIAGRAM

Operating

(ICC, Max )

PKG TYPE

SOP-32 TSOP2-32 TSOP-32 STSOP-32 PDIP-32 SOP-32 TSOP2-32 TSOP-32 STSOP-32 PDIP-32

•

A18

1

A16

2

A14

3

A12

4

A7

5

A6

6

A5

7

A4

BS62LV4005SC

8

BS62LV4005SI

A3

9

BS62LV4005EC

A2

10

BS62LV4005EI

A1

11

BS62LV4005PC

A0

12

•

BS62LV4005PI

13 14 15 16

BS62LV4005TC BS62LV4005STC BS62LV4005TI BS62LV4005STI

DQ0 DQ1 DQ2

GND

1

A11

2

A9

3

A8

4

A13

5

WE

6

A17

7

A15

8

VC

C

9

A18

10

A16

11

A14

12

A12

13

A7

14

A6

15

A5

16

A4

VCC

32

A15

31

A17

30

WE

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23

CE

22

DQ7

21

DQ6

20

DQ5

19

DQ4

18

DQ3

17

32

OE

31

A10

30

CE

29

DQ7

28

DQ6

27

DQ5

26

DQ4

25

DQ3

24

GND

23

DQ2

22

DQ1

21

DQ0

20

A0

19

A1

18

A2

17

A3

A13 A17 A15 A18 A16 A14 A12

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Vdd

Gnd

A7 A6 A5 A4

WE

Address

Input

Buffer

CE

OE

8

Control

22

Row

Decoder

Data Input Buffer

Data

Output

Buffer

2048

8

A11 A9 A8 A3 A2 A1 A0 A10

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS62LV4005

1

Memory Array

2048 X 2048

2048

Column I/O

Write Driver

Sense Amp

256

Column Decoder

16

Address Input Buffer

Revision 2.4 April 2002

BSI

 PIN DESCRIPTIONS

Name Function

BS62LV4005

A0-A18 Address Input

CE Chip Enable Input

WE Write Enable Input

OE Output Enable Input

DQ0-DQ7 Data Input/Output

These 19 address inputs select one of the 524,288 x 8-bit words in the RAM

CE is active LOW. Chip enable must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

These 8 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Gnd

Power Supply

Ground

 TRUTH TABLE

MODE WE CE OE I/O OPERATION Vcc CURRENT

Not selected

Output Disabled H L H High Z I

Read H L L D

Write L L X D

X H X High Z I

OUT

IN

CCSB

, I

CSB1

C

CC

I

CC

I

CC

 ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PARAMETER RATING UNITS

TERM

V

BIAS

T

STG

T

P

OUT

I

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

R0201-BS62LV4005

Terminal Voltage with Respect to GND

Temperature Under Bias -40 to +125

Storage Temperature -60 to +150

Power Dissipation 1.0 W

DC Output Current mA20

-0.5 to 6.0 V

 OPERATING RANGE

RANGE

O

C

O

C

Commercial 0OC to +70OC 4.5~5.5V

Industrial -40OCto +85OC 4.5~5.5V

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

Input

IN

C

1. This parameter is guaranteed and not tested.

DQ

Capacitance Input/Output Capacitance

2

AMBIENT

TEMPERATURE

(1)

(TA = 25oC, f = 1.0 MHz)

VIN=0V 6 pF

I/O

V

=0V 8 pF

Vcc

Revision 2.4 April 2002

BSI

BS62LV4005

 DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

PAR AMETER

NAME

IL

V

IH

V

IL

I

IOL Output Leakage Current

VOL Output Low Voltage Vcc = Max, IOL = 2mA

VOH Output High Voltage Vcc = Min, IOH = -1mA

CC

I

CCSB

I

Standby Current-TTL CE = VIH, IDQ = 0mA

CCSB1

I

Standby Current-CMOS

PAR AMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage Guaranteed Input High

(2)

Voltage

Input Leakage Current Vcc = Max, V

Vcc = Max, CE = V

I/O

V

= 0V to Vcc

Operating Power Supply Current

CE = V

CE Њ Vcc-0.2V,

IN

Њ

V

IN

IL

, IDQ = 0mA, F = Fmax

Vcc - 0.2V or V

o

C )

(1)

MAX.

Vcc=5.0V

-0.5 -- 0.8 V

2.2 -- Vcc+0.3 V

= 0V to Vcc -- -- 1 uA

IH

, or OE = VIH,

(3)

IN

Љ

0.2V

Vcc=5.0V

-- -- 1 uA

-- -- 0.4 V

2.4 -- -- V

-- -- 45 mA

-- -- 2 mA

-- 1.5 15 uA

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

 DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70

SYMBOL PAR AMET ER TEST CONDITIONS MIN. TYP.

V

.

RC

o

C )

(1)

MAX. UNITS

DR

Vcc for Data Retention

CE Њ Vcc - 0.2V

Њ

IN

V

Vcc - 0.2V or V

Љ

IN

0.2V

1.5 -- -- V

UNITS

I

CCDR

t

CDR

Data Retention Current

Chip Deselect to Data Retention Time

t

R

Operation Recovery Time

CE Њ Vcc - 0.2V

Њ

IN

V

Vcc - 0.2V or V

See Retention Waveform

1. Vcc = 1.5V, TA= + 25OC = Read Cycle Time

2. t

RC

 LOW VCCDATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

Vcc

CE

R0201-BS62LV4005

Vcc

t CDR

CE Vcc - 0.2V

3

IN

≥

VDR 2.0V

≥

Љ

0.2V

-- 0.1 1.5 uA

0 -- -- ns

(2)

T

RC

Vcc

-- -- ns

t R

VIHVIH

Revision 2.4 April 2002

BSI

BS62LV4005

 AC TEST CONDITIONS

Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level

Vcc/0 5ns

0.5Vcc

 AC TEST LOADS AND WAVEFORMS

Ω

1.73V

1928

5PF

1020

FIGURE 1B

Ω

5.0V

OUTPUT

INCLUDING JIG AND SCOPE

OUTPUT

Vcc

GND

1928

Ω

100PF

Ω

1020

FIGURE 1A

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

→

90%

←

FIGURE 2

5.0V

OUTPUT

INCLUDING JIG AND SCOPE

Ω667

90%

→

10%

← 5ns

 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

MUST BE STEADY

MAY CHANGE FROM H TO L

MAY CHANGE FROM L TO H

,

o

C , Vcc = 5.0V )

DON T CAR ANY CHANG PERMITTED

DOES NOT APPLY

E: CHANGE :

E STATE

MUST BE STEADY

WILL BE CHANGE FROM H TO L

WILL BE CHANGE FROM L TO H

UNKNOWN

CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXOX

PARAMETER

NAME

t

RC

t

AA

t

ACS

t

OE

t

CLZ

t

OLZ

t

CHZ

t

OHZ

t

OH

DESCRIPTION

Read Cycle Time

Address Access Time

Chip Select Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Output Disable to Output in High Z

Output Disable to Output Address Change

BS62LV4005-55

MIN. TYP. MAX.

BS62LV4005

MIN. TYP. MAX.

-

70

UNIT

55 -- -- 70 -- -- ns

-- -- 55 -- -- 70 ns

-- -- 30 -- -- 35 ns

10 -- -- 10 -- -- ns 10 -- -- 10 -- -- ns

0 -- 30 0 -- 35 ns

0 -- 25 0 -- 30 ns

10 -- -- 10 -- -- ns

R0201-BS62LV4005

4

Revision 2.4 April 2002

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t OH

OUT

t AA

BS62LV4005

t RC

t OH

READ CYCLE2

CE

D

OUT

READ CYCLE3

ADDRESS

OE

CE

D

OUT

(1,3,4)

(1,4)

t CLZ

t ACS

(5)

t CHZ

(5)

t RC

t AA

t OH

t OE

t OLZ

t ACS

(5)

t OHZ

t CHZ

(5)

(1,5)

t CLZ

NOTES:

1. WE is high for read Cycle.

2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.

4. OE = V

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.

R0201-BS62LV4005

IL .

IL.

±

5

Revision 2.4 April 2002

BSI

BS62LV4005

 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

WLOZ

t

DVWH

t

WHDX

t

GHOZ

t

WHQX

PARAMETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR

t

WHZ

t

W

D

t

DH

t

OHZ

t

OW

DESCRIPTION

Write Cycle Time

Chip Select to End of Write

Address Set up Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End ot Write to Output Active

(CE , WE)

o

C , Vcc = 5.0V )

BS62LV4005-55

MIN. TYP. MAX.

55 -- 70 -- ns--

55 -- 70 -- -- ns

0 -- -- 0 -- -- ns

55 -- -- 70 -- ns--

30 -- -- 35 -- ns--

0 -- -- 0 -- -- ns

0--250--30 ns

25 -- -- 30 -- ns--

0 -- -- 0 -- -- ns

0--250--30 ns

5 -- -- 5 -- -- ns

BS62LV4005-70

MIN. TYP. MAX.

UNIT

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

ADDRESS

OE

CE

WE

(1)

(5)

t AS

(4,10)

t OHZ

D

OUT

D

IN

t AW

t WC

t CW

t WP

(11)

(3)

t WR

(2)

t DH

t DW

R0201-BS62LV4005

6

Revision 2.4 April 2002

BSI

BS62LV4005

WRITE CYCLE2

ADDRESS

CE

WE

D

OUT

D

IN

(1,6)

t AS

(5)

(4,10)

t WHZ

t AW

t WC

t CW

t WP

(11)

(2)

t DH

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. T

WR is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

OUT is the same phase of write data of this write cycle.

7. D

OUT is the read data of next address.

8. D

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

The parameter is guaranteed but not 100% tested.

11. T

CW is measured from the later of CE going low to the end of write.

IL ).

±

L = 5pF as shown in Figure 1B.

R0201-BS62LV4005

7

Revision 2.4 April 2002

BSI

 ORDERING INFORMATION

BS62LV4005 X X ˀˀ Y Y

BS62LV4005

SPEED

70: 70ns 55: 55ns

GRADE

o

C: +0

C ~ +70oC

o

I: -40

C ~ +85oC

PACKAGE

S: SOP E: TSOP 2 T: TSOP ST: Small TSOP P: PDIP

 PACKAGE DIMENSIONS

WITH PLATING

c c1

BASE METAL

b

b1

SECTION A-A

R0201-BS62LV4005

SOP -32

8

Revision 2.4 April 2002

BSI

 PACKAGE DIMENSIONS (continued)

BS62LV4005

TSOP2 - 32

TSOP - 32

R0201-BS62LV4005

9

Revision 2.4 April 2002

BSI

 PACKAGE DIMENSIONS (continued)

BS62LV4005

STSOP - 32

PDIP - 32

R0201-BS62LV4005

10

Revision 2.4 April 2002

BSI

BS62LV4005

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

2.3 Modify Standby Current (Typ. and Max.)

2.4 Modify some AC parameters. April,10,2002

Jun. 29, 2001

R0201-BS62LV4005

11

Revision 2.4 April 2002