Datasheet BS62LV256SIP55, BS62LV256SIP70 Specification

R0201

-BS62LV256

Revision

2.6

11 12 13 14

A14

A12A7A6A5A4A3A2A1A0

DQ0

DQ1

DQ2

GND

28272625242322212019181716

15

BS62LV256PC

BS62LV256SI

512X512

Write Driver

Sense Amp

Address Input Buffer

A10

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

A5A6A7A12

A14

A13A8A9

A11

86 64

512

9

BS62LV

256TC

BS62LV

256TI

32K X 8 bit

Very Low Power CMOS SRAM

Pb-Free and Green package materials are compliant to RoHS

BS62LV256

n FEATURES

Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V Ÿ Very low power consumption :

VCC = 3.0V Operation current : 25mA (Max.) at 70ns 1mA (Max.) at 1MHz Standby current : 0.01uA(Typ.) at 25OC VCC = 5.0V Operation current : 40mA (Max.) at 55ns 2mA (Max.) at 1MHz Standby current : 0.4uA (Typ.) at 25OC

Ÿ High speed access time :

-55 55ns(Max.) at VCC : 4.5~5.5V

-70 70ns(Max.) at VCC : 3.0~5.5V

Ÿ Automatic power down when chip is deselected Ÿ Easy expansion with CE and OE options Ÿ Three state outputs and TTL compatible Ÿ Fully static operation Ÿ Data retention supply voltage as low as 1.5V

n DESCRIPTION

The BS62LV256 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 by 8 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.01uA and maximum access time of 70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and three-state output drivers. The BS62LV256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV256 is available in DICE form, JEDEC standard 28 pin 330mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm TSOP (normal type).

n POWER CONSUMPTION

POWER DISSIPATION

PRODUCT

FAMILY

BS62LV256DC DICE BS62LV256PC PDIP-28 BS62LV256SC SOP-28 BS62LV256TC BS62LV256PI PDIP-28 BS62LV256SI SOP-28 BS62LV256TI

OPERATING

TEMPERATURE

Commercial

+0OC to +70OC

Industrial

-40OC to +85OC

STANDBY

(I

, Max)

CCSB1

VCC=5.0V VCC=3.0V

1MHz 10MHz f

VCC=5.0V VCC=3.0V

Operating

(ICC, Max)

1MHz 10MHz

Max.

f

4.0uA 0.4uA 1.5mA 18mA 35mA 0.8mA 12mA 20mA

5.0uA 0.7uA 2mA 20mA 40mA 1mA 15mA 25mA

Max.

PKG TYPE

TSOP-28

n PIN CONFIGURATIONS

1 2 3 4 5 6 7

BS62LV256PI BS62LV256SC

8 9 10

A11

A13 WE

VCC

A14 A12

1

OE

2 3

A9

4

A8

5 6 7 8 9 10

A7

11

A6

12

A5

13

A4

14

A3

VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3

28 27 26 25 24 23 22 21 20 19 18 17 16 15

A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2

n BLOCK DIAGRAM

Address

Input

Buffer

8

WE

GND

CE

OE

V

CC

Control

Decoder

Data Input

Buffer

Data

Output

Buffer

Row

Memory Array

512

8

Column I/O

Column Decoder

A3A2A1A0

A4

Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.

1

Sep. 2006

BS6

2L

V

256

Revision

2.6

. With the

selected and the write enable is inactive, data will be present on the DQ pins and they

n PIN DESCRIPTIONS

Name Function

A0-A14 Address Input

CE Chip Enable Input

WE Write Enable Input

OE Output Enable Input

DQ0-DQ7 Data Input/Output Ports VCC

GND

n TRUTH TABLE

MODE

Not selected

(Power Down)

Output Disabled L H H High Z ICC

These 15 address inputs select one of the 32,768 x 8-bit in the RAM

CE is active LOW. Chip enable must be active when data read form or write to the device. If chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is

will be enabled. The DQ pins will be in the high impendence state when OE is inactive. There 8 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

Ground

CE WE OE

H X X High Z I

I/O OPERATION VCC CURRENT

CCSB

, I

CCSB1

Read L H L D

Write L L X DIN ICC

NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)

n ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

TERM

T

BIAS

T

Storage Temperature -60 to +150

STG

PARAMETER RATING UNITS

Terminal Voltage with Respect to GND

Temperature Under Bias

(1)

(2)

-0.5

to 7.0

-40 to +125

n OPERATING RANGE

V

O

C

O

C

PT Power Dissipation 1.0 W

n CAPACITANCE

I

DC Output Current 20 mA

OUT

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. –2.0V in case of AC pulse width less than 30 ns.

ICC

OUT

RANG

Commercial 0OC to + 70OC 2.4V ~ 5.5V

Industrial -40OC to + 85OC 2.4V ~ 5.5V

AMBIENT

TEMPERATURE

(1)

(TA = 25OC, f = 1.0MHz)

VCC

SYMBOL PAMAMETER CONDITIONS MAX. UNITS

CIN

CIO

Input Capacitance

Input/Output Capacitance

VIN = 0V 6 pF

V

= 0V 8 pF

I/O

1. This parameter is guaranteed and not 100% tested.

R0201-BS62LV256

2

Sep. 2006

BS6

2L

V

256

Revision

2.6

Data Retention Mode

V

CC

CDR

V

CC

n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

PARAMETER

NAME

PARAMETER TEST CONDITIONS MIN. TYP.

(1)

MAX. UNITS

VCC

VIL

VIH

IIL

ILO

VOL

VOH

(5)

I

CC

I

CC1

I

CCSB

I

CCSB1

1. Typical characteristics are at TA=25OC and not 100% tested.

2. Undershoot: -1.0V in case of pulse width less than 20 ns.

3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.

Power Supply 2.4 -- 5.5 V

Input Low Voltage -0.5

Input High Voltage 2.2 -- VCC+0.3

Input Leakage Current VIN = 0V to VCC -- -- 1 uA

Output Leakage Current

CE= VIH, or OE = VIH, V

= 0V to VCC

I/O

Output Low Voltage VCC = Max, IOL = 0.5mA -- -- 0.4 V

Output High Voltage VCC = Min, I

Operating Power Supply Current

Standby Current – TTL

(6)

Standby Current – CMOS

CE = VIL, IDQ = 0mA, f = F

CE = VIL, IDQ = 0mA, f = 1MHz

CE = VIH, IDQ = 0mA

CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V

= -0.5mA 2.4 -- -- V

OH

VCC=3.0V

MAX

(4)

4. F

MAX

5. I

CC (MAX.)

6. I

CCSB1(MAX.)

VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V

=1/t

RC.

is 20mA/35mA at VCC=3.0V/5.0V and TA=70OC.

is 0.4uA/4.0uA at VCC=3.0V/5.0V and TA=70OC.

n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.

(2)

-- 0.8 V

(3)

V

-- -- 1 uA

-- -- 25

-- -- 40

-- -- 1

-- -- 2

-- -- 1.0

-- -- 2.0

-- 0.01 0.7

-- 0.4 5.0

(1)

MAX. UNITS

mA

uA

n LOW VCC DATA RETENTION WAVEFORM (CE Controlled)

R0201-BS62LV256

VDR

I

CCDR

t

CDR

tR

VCC for Data Retention

(3)

Data Retention Current Chip Deselect to Data

Retention Time Operation Recovery Time

1. VCC=1.5V, TA=25OC and not 100% tested.

2. tRC = Read Cycle Time.

3. I

is 0.4uA at TA=70OC.

CCDR(Max.)

V

CC

CE

CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V

See Retention Waveform

VDR≧1.5V

t

V

IH

CE≧VCC - 0.2V

3

1.5 -- -- V

-- 0.01 0.7 uA

0 -- -- ns

(2)

t

-- -- ns

RC

t

R

V

IH

Sep. 2006

BS6

2L

V

256

Revision

2.6

(1)

1

TTL

→ ←

CC

GND

→ ←

n AC TEST CONDITIONS

(Test Load and Input/Output Reference)

n KEY TO SWITCHING WAVEFORMS

Input Pulse Levels Vcc / 0V

Input Rise and Fall Times 1V/ns Input and Output Timing

Reference Level

t

, t

CLZ

OLZ

Output Load

Output

1. Including jig and scope capacitance.

C

Others

L

CHZ

V

CL = 5pF+1TTL

OHZ

WHZ

10%

Rise Time : 1V/ns

0.5Vcc

C

L

100pF+1TTL

ALL INPUT PULSES

90%

=

90%

Fall Time : 1V/ns

10%

WAVEFORM INPUTS OUTPUTS

n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

READ CYCLE

JEDEC

PARAMETER

NAME

PARANETER

NAME

DESCRIPTION

MUST BE STEADY

MAY CHANGE FROM “H” TO “L”

MAY CHANGE FROM “L” TO “H”

DON’T CARE ANY CHANGE PERMITTED

DOES NOT APPLY

CYCLE TIME : 55ns

(VCC = 4.5~5.5V)

MIN. TYP. MAX. MIN. TYP. MAX.

CYCLE TIME : 70ns

(VCC = 3.0~5.5V)

MUST BE STEADY

WILL BE CHANGE FROM “H” TO “L”

WILL BE CHANGE FROM “L” TO “H”

CHANGE : STATE UNKNOW

CENTER LINE IS HIGH INPEDANCE “OFF” STATE

UNITS

t

tRC

AVAX

t

tAA

AVQX

t

E1LQV

t

tOE

GLQV

t

E1LQX

t

GLQX

t

E1HQZ

t

GHQZ

t

tOH

AVQX

ACS

CLZ

OLZ

CHZ

OHZ

Read Cycle Time 55 -- -- 70 -- -- ns

Address Access Time -- -- 55 -- -- 70 ns

Chip Select Access Time Output Enable to Output Valid -- -- 25 -- -- 35 ns

Chip Select to Output Low Z Output Enable to Output Low Z 10 -- -- 10 -- -- ns

Chip Select to Output High Z Output Enable to Output High Z -- -- 25 -- -- 30 ns

Data Hold from Address Change 10 -- -- 10 -- -- ns

-- -- 55 -- -- 70 ns

10 -- -- 10 -- -- ns

-- -- 30 -- -- 35 ns

R0201-BS62LV256

4

Sep. 2006

BS6

2L

V

256

Revision

2.6

(5)

OUT

CE

ACS

(

5)

OH

RC

OE

(5)

ACS

CHZ

(1,5)

(5)

OLZ

AA

OH

AA

n SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE 1

(1,2,4)

ADDRESS

t

OH

D

OUT

READ CYCLE 2

(1,3,4)

D

t

CLZ

READ CYCLE 3

(1, 4)

ADDRESS

CE

D

OUT

t

CLZ

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = VIL.

3. Address valid prior to or coincident with CE transition low.

4. OE = VIL.

5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested.

t

RC

t

CHZ

t

OHZ

t

R0201-BS62LV256

5

Sep. 2006

BS6

2L

V

256

Revision

2.6

(3)

(11)

(2)

(4,10)

AS

tDH

tDW

CE OE

(5)

n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

WRITE CYCLE

JEDEC

PARAMETER

NAME

PARANETER

NAME

DESCRIPTION

CYCLE TIME : 55ns

(VCC = 4.5~5.5V)

MIN. TYP. MAX. MIN. TYP. MAX.

CYCLE TIME : 70ns

(VCC = 3.0~5.5V)

UNITS

t

tWC

AVAX

t

tAW

AVWH

t

tCW

E1LWH

t

tWP

WLWH

t

tAS

AVWL

t

tWR

WHAX

t

WLQZ

t

tDW

DVWH

t

tDH

WHDX

t

GHQZ

t

tOW

WHQX

WHZ

OHZ

Write Cycle Time 55 -- -- 70 -- -- ns

Address Valid to End of Write 55 -- -- 70 -- -- ns

Chip Select to End of Write 55 -- -- 70 -- -- ns

Write Pulse Width 35 -- -- 40 -- -- ns

Address Set up Time 0 -- -- 0 -- -- ns

Write Recovery Time (CE, WE)

Write to Output High Z -- -- 25 -- -- 30 ns

Data to Write Time Overlap 35 -- -- 40 -- -- ns

Data Hold from Write Time 0 -- -- 0 -- -- ns

Output Disable to Output in High Z -- -- 25 -- -- 30 ns

End of Write to Output Active 5 -- -- 5 -- -- ns

n SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE 1

(1)

0 -- -- 0 -- -- ns

ADDRESS

WE

D

OUT

D

IN

t

OHZ

t

WC

t

WR

t

CW

t

AW

t

WP

R0201-BS62LV256

6

Sep. 2006

BS6

2L

V

256

Revision

2.6

t

WC

(11)

(2)

(4,10)

AS

tDH

tDW

OUT

CE

OW

(7) (8) (8,9)

(5)

WRITE CYCLE 2

(1,6)

ADDRESS

t

CW

t

WHZ

t

AW

t

WP

t

WE

t

D

IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. tWR is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to

the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = VIL).

7. D

is the same phase of write data of this write cycle.

OUT

8. D

is the read data of next address.

OUT

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. Transition is measured ± 500mV from steady state with CL = 5pF.

The parameter is guaranteed but not 100% tested.

11. tCW is measured from the later of CE going low to the end of write.

R0201-BS62LV256

7

Sep. 2006

BS6

2L

V

256

Revision

2.6

θ

b

b1

PACKAGE

P: PDIP

GRADE

I: -40oC ~ +85

C

SPEED

70: 70ns

PKG MATERIAL

n ORDERING INFORMATION

BS62LV256 X X Z Y Y

55: 55ns

-: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant

C: +0oC ~ +70oC

D: DICE S: SOP T: TSOP (8mm x 13.4mm)

o

Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.

n PACKAGE DIMENSIONS

SOP - 28

0.020 ± 0.005X45°

WITH PLATING

c1 c

BASE METAL

R0201-BS62LV256

8

Sep. 2006

BS6

2L

V

256

Revision

2.6

1

28

c1

D E

e

A

MM

c1 b1 b

°

A2

L

A

0

n PACKAGE DIMENSIONS (continued)

HD

c

L

14

D

14

15

"A"

15

28

12°(2x)

A1

"A" DATAIL VIEW

WITH PLATING

c

BASE METAL

12°(2x)

e

E

b

Seating Plane

SEATING PLANE

SECTION A-A

12°(2x)

UNIT

SYMBOL

A1 A2 b b1 c

y

HD L

GAUGE PLANE

A

L1

L1 y 0

0.254

INCH

0.0433±0.004

0.0045±0.0026

0.039±0.002

0.009±0.002

0.008±0.001

0.004 ~ 0.008

0.004 ~ 0.006

0.465±0.004

0.315±0.004

0.022±0.004

0.528±0.008

+0.008

0.0197

- 0.004

0.0315±0.004

0.004 Max. 0°~ 8°

1.10±0.10

0.115±0.065

1.00±0.05

0.22±0.05

0.20±0.03

0.10 ~ 0.21

0.10 ~ 0.16

11.80±0.10

8.00±0.10

0.55±0.10

13.40±0.20

+0.20

0.50

- 0.10

0.80±0.10

0.1 Max. 0°~ 8°

TSOP - 28

PDIP - 28

R0201-BS62LV256

9

Sep. 2006

BS6

2L

V

256

Revision

2.6

n Revision History

Revision No. History Draft Date Remark

2.4 Add Icc1 characteristic parameter Jan. 13, 2006

2.5 Change I-grade operation temperature range May. 25, 2006

- from –25OC to –40OC

2.6 Revised I

- from 1.0uA to 4.0uA for 5V C-grade

- from 2.0uA to 5.0uA for 5V I-grade

- from 0.2uA to 0.4uA for 3V C-grade

- from 0.4uA to 0.7uA for 3V I-grade

Revised I

- from 0.2uA to 0.4uA for C-grade

- from 0.4uA to 0.7uA for I-grade

sepc. Sep. 05, 2006

CCSB1

sepc.

CCDR

R0201-BS62LV256

10

Sep. 2006