Datasheet BS62LV256PC, BS62LV256JI, BS62LV256JC, BS62LV256DI, BS62LV256DC Datasheet (BSI)

BSI

Very Low Power/Voltage CMOS SRAM 32K X 8 bit

BS62LV256

 FEATURES

• Wide Vcc operation voltage : 2.4V ~ 5.5V

• Very low power consumption : Vcc = 3.0V C-grade : 20mA (Max.) operating current

I- grade : 25mA (Max.) operating current

0.01uA (Typ.) CMOS standby current

Vcc = 5.0V C-grade : 35mA (Max.) operating current

I- grade : 40mA (Max.) operating current

0.4uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc=3.0V

 DESCRIPTION

The BS62LV256 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 words by 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of

0.01uA and maximum access time of 70ns in 3V operation. Easy memory expansion is provided by active LOW chip enable (CE), active LOW output enable (OE) and three-state output drivers. The BS62LV256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected.

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

The BS62LV256 is available in the DICE form, JEDEC standard

28pin 330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and

8mmx13.4mm TSOP (normal type).

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

 PRODUCT FAMILY

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

SPEED

(ns)

Vcc=

3.0V

BS62LV256SC SOP-28 BS62LV256TC TSOP-28 BS62LV256PC PDIP-28

O

C to +70

0

O

C 2.4V ~ 5.5V 70 1uA 0.2uA 35mA 20mA BS62LV256JC SOJ-28 BS62LV256DC BS62LV256SI SOP-28 BS62LV256TI TSOP-28 BS62LV256PI PDIP-28

-40

O

C to +85

O

C 2.4V ~ 5.5V 70 2uA 0.4uA 40mA 25mA BS62LV256JI SOJ-28 BS62LV256DI

 PIN CONFIGURATIONS

•

1

A14

2

A12

3

A7

4

A6

5

A5

BS62LV256SC

6

A4

BS62LV256SI

7

A3

BS62LV256PC BS62LV256PI

8

A2

BS62LV256JC

9

A1

BS62LV256JI

10

A0

11

DQ0

12

DQ1

13

DQ2

14

GND

•

1

OE

2

A11

3

A9

4

A8

5

A13

6

WE

VCC

A14 A12

7 8 9 10

A7

11

A6

12

A5

13

A4

14

A3

BS62LV256TC BS62LV256TI

28

VC

C

27

WE

26

A13

25

A8

24

A9

23

A11

22

OE

21

A10

20

CE

19

DQ7

18

DQ6

17

DQ5

16

DQ4

15

DQ3

A10

28

CE

27

DQ7

26

DQ6

25

DQ5

24

DQ4

23

DQ3

22

GND

21

DQ2

20

DQ1

19

DQ0

18

A0

17

A1

16

A2

15

 BLOCK DIAGRAM

A5

A6

A7 A12

A14

A13

A8

A9 A11

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CE

WE

OE

Vdd

Gnd

POWER DISSIPATION

STANDBY

(I

, Max)

CCSB1

Vcc=

5.0V

Address

Input

Buffer

8

Control

Vcc=

3.0V

18

Decoder

Data Input Buffer

Data

Output

Buffer

Row

Operating

(ICC, Max)

Vcc=

5.0V

512

8

Vcc=

3.0V

Memory Array

512 x 512

Column I/O

Write Driver

Sense Amp

Column Decoder

Address Input Buffer

A4

A3 A2 A1 A0 A10

PKG

TYPE

DICE

512

64

12

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS62LV256

1

Revision 2.2 April 2001

BSI

 PIN DESCRIPTIONS

Name Function

BS62LV256

A0-A14 Address Input

CE Chip Enable Input

WE Write Enable Input

OE Output Enable Input

DQ0 – DQ7 Data Input/Output

These 15 address inputs select one of the 32768 x 8-bit words in the RAM

CE is active LOW. Chip enables must be active when data read from or write to the

device. If chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

These 8 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Gnd

Power Supply

Ground

 TRUTH TABLE

MODE WE CE OE I/O OPERATION Vcc CURRENT

Not selected X H X High Z I

Output Disabled H L H High Z I

Read H L L D

Write L L X D

OUT

IN

CCSB

I

, I

CC

CCSB1

 ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PARAM ETER RATING UNITS

TERM

V

BIAS

T

STG

T

P

OUT

I

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

R0201-BS62LV256

Terminal Voltage with Respect to GND

Temperature Under Bias -40 to +125

Storage Temperature -60 to +150

Power Dissipation 1.0 W

DC Output Current 20 mA

-0.5 to

Vcc+0.5

 OPERATING RANGE

V

O

C

O

C

RANGE

Commercial 0 OC to +70

Industrial -40

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

C

1. This parameter is guaranteed and not tested.

IN

DQ

Input Capacitance Input/Output Capacitance

2

AMBIENT

TEMPERATURE

O

C2.4V ~ 5.5V

O

(1)

(TA = 25oC, f = 1.0 MHz)

O

C to +85

VIN=0V 6

I/O

V

=0V 8

C2.4V ~ 5.5V

Vcc

pF

Revision 2.2 April 2001

BSI

C

BS62LV256

 DC ELECTRICAL CHARACTERISTICS ( TA =0

PAR AMETER

NAME

IL

V

IH

V

IL

I

OL

I

OL

V

OH

V

CC

I

CCSB

I

CCSB1

I

PAR AMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage Guaranteed Input High

(2)

Voltage

Input Leakage Current Vcc = Max, V

Output Leakage Current

Output Low Voltage Vcc = Max, IOL = 2mA

Output High Voltage Vcc = Min, IOH = -1mA

Operating Power Supply Current

Standby Current-TTL CE = VIH, IDQ = 0mA

Standby Current-CMOS

Vcc = Max, CE = V

I/O

= 0V to Vcc

V

CE = V

CE Њ Vcc-0.2V,

IN

Њ Vcc - 0.2V or VINЉ 0.2V

V

o

C to + 70oC)

(1)

MAX.

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

IN

= 0V to Vcc -- -- 1 uA

IH

, or OE = VIH,

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

IL

, IDQ = 0mA, F = Fm ax

(3)

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

-0.5 -- 0.8 V

2.0

2.2

-- Vcc+0.2 V

-- -- 1 uA

-- -- 0.4 V

2.4 -- -- V

-- -- 20

-- -- 35

-- -- 1

-- -- 2

-- 0.01 0.2

-- 0.4 1.0

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

 DATA RETENTION CHARACTERISTICS ( TA = 0

.

RC

o

C to + 70oC )

UNITS

mA

uA

SYMBOL PAR AMETER TEST CONDITIONS MIN. TYP.

V

I

CCDR

t

CDR

DR

t

R

Vcc for Data Retention

Data Retention Current

Chip Deselect to Data Retention Time

Operation Recovery Time

1. Vcc = 1.5V, TA= + 25OC

2. t

= Read Cycle Time

RC

 LOW V

DATA RETENTION WAVEFORM ( CE Controlled )

CC

Vcc

CE Њ Vcc - 0.2V

Њ

Vcc - 0.2V or V

IN

V

CE Њ Vcc -0.2V

Њ

Vcc - 0.2V or V

IN

V

See Retention Waveform

Data Retention Mode

Vcc

t CDR

CE Vcc - 0.2V

IN

≥

VDR 1.5V

≥

Љ

0.2V

1.5 -- -- V

-- 0.01 0.20 uA

0---- ns

T

R

Vcc

CE

(1)

MAX. UNITS

(2)

-- -- ns

t R

VIHVIH

R0201-BS62LV256

3

Revision 2.2 April 2001

BSI

BS62LV256

 AC TEST CONDITIONS

Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level

Vcc/0V 5ns

0.5Vcc

 AC TEST LOADS AND WAVEFORMS

3.3V

OUTPUT

INCLUDING JIG AND SCOPE

OUTPUT

Vcc

GND

1269

100PF

1404

FIGURE 1A

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

→

Ω

←

OUTPUT

Ω667

90%

FIGURE 2

3.3V

INCLUDING JIG AND SCOPE

→

←

1.73V

10%

5ns

Ω

 AC ELECTRICAL CHARACTERISTICS ( TA =0

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVA X

t

AVQ V

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXOX

PARAME TER

NAME

t

RC

t

AA

t

ACS

t

OE

t

CLZ

t

OLZ

t

CHZ

t

OHZ

t

OH

Read Cycle Time

Address Access Time

Chip Select Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Output Disable to Output in High Z

Output Disable to Output Address Change

Ω

1269

5PF

1404

FIGURE 1B

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Ω

o

C to + 70oC and Vcc=3.0V)

DESCRIPTION

MUST BE STEADY

MAY CHANGE FROM H TO L

MAY CHANGE FROM L TO H

,

DON T CAR ANY CHANG PERMITTED

DOES NOT APPLY

BS62LV256

MIN. TYP. MAX.

E: CHANGE :

E STATE

MUST BE STEADY

WILL BE CHANGE FROM H TO L

WILL BE CHANGE FROM L TO H

UNKNOWN

CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE

UNIT

70 -- -- ns

-- -- 70 ns

-- -- 50 ns

10 -- -- ns

0--35 ns

0--30 ns

10 -- -- ns

R0201-BS62LV256

4

Revision 2.2 April 2001

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t AA

t OH

OUT

BS62LV256

t RC

t OH

READ CYCLE2

CE

D

OUT

READ CYCLE3

ADDRESS

OE

CE

(1,3,4)

(1,4)

t CLZ

t ACS

(5)

t CHZ

(5)

t RC

t AA

t OE

t OH

t OLZ

t OHZ

t CHZ

(5)

(1,5)

t CLZ

t ACS

(5)

D

OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.

4. OE = V

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.

R0201-BS62LV256

IL .

IL.

±

5

Revision 2.2 April 2001

BSI

BS62LV256

 AC ELECTRICAL CHARACTERISTICS ( TA =0

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVA X

t

E1LWH

t

AVW L

t

AVW H

t

WLWH

t

WHAX

t

WLOZ

t

DVWH

t

WHDX

t

GHOZ

t

WHQX

PARAME TER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

DESCRIPTION

Write Cycle Time

Chip Select to End of Write

Address Set up Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time (CE , WE)

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End ot Write to Output Active

o

C to + 70oC and Vcc=3.0V)

BS62LV256

MIN. TYP. MAX.

70 -- -- ns

0---- ns

70 -- -- ns

50 -- -- ns

0---- ns

-- -- 30 ns

40 -- -- ns

0---- ns

0--30 ns

5---- ns

UNIT

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

ADDRESS

OE

CE

WE

(1)

(5)

t AS

(4,10)

t OHZ

D

OUT

D

IN

t AW

t WC

t CW

t WP

(11)

(3)

t WR

(2)

t DH

t DW

R0201-BS62LV256

6

Revision 2.2 April 2001

BSI

BS62LV256

WRITE CYCLE2

(1,6)

t WC

ADDRESS

(11)

t CW

t WP

(2)

CE

WE

t AS

(5)

t AW

(4,10)

t WHZ

D

OUT

t DW

t DH

D

IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

WR is measured from the earlier of CE or WE going high at the end of write cycle.

3. T

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7.

DOUT is the same phase of write data of this write cycle.

OUT is the read data of next address.

8. D

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

The parameter is guaranteed but not 100% tested.

11. T

CW is measured from the later of CE going low to the end of write.

IL ).

±

L = 5pF as shown in Figure 1B.

t DH

(7) (8)

(8,9)

R0201-BS62LV256

7

Revision 2.2 April 2001

BSI

 ORDERING INFORMATION

BS62LV256 X X ˀˀ Y Y

BS62LV256

SPEED

70: 70ns

GRADE

C: +0oC ~ +70oC

o

C ~ +85oC

I: -40

PACKAGE

J: SOJ S: SOP P: PDIP T: TSOP (8mm x 13.4mm) D: DICE

 PACKAGE DIMENSIONS PACKAGE DIMENSIONS

WITH PLATING

BASE METAL

0.020  0.005X45

θ

b

c1c

b1

R0201-BS62LV256

SOP - 28

8

Revision 2.2 April 2001

BSI

 PACKAGE DIMENSIONS (continued)

HD

c

L

1

14

D

14

28

15

"A"

15

A

12(2x)

A2

A1

"A" DATAIL VIEW

12(2x)

SEATING PLANE

e

E

b

Seating Plane

12 (2X)

12(2X)

BS62LV256

UNIT

0.04330.004

A

0.00450.0026

A1

0.0390.002

A2

0.0090.002

b

0.0080.001

b1

0.004 ~ 0.008

c

0.004 ~ 0.006

c1

0.4650.004

D

0.3150.004

E

0.0220.004

e

0.5280.008

HD

L

L1

0.004 Max.

y

0~ 8

0

INCH

+0.008

0.0197

-0.004

0.03150.004

SYMBOL

y

GAUGE PLANE

A

L

L1

0.254

0

MM

1.100.10

0.1150.065

1.000.05

0.220.05

0.200.03

0.10 ~ 0.21

0.10 ~ 0.16

11.800.10

8.000.10

0.550.10

13.400.20

+0.20

0.50

-0.10

0.800.10

0.1 Max.

0~ 8

WITH PLATING

1

28

c

BASE METAL

b

c1

b1

SECTION A-A

TSOP - 28

R0201-BS62LV256

PDIP - 28

9

Revision 2.2 April 2001

BSI

 PACKAGE DIMENSIONS (continued)

SOJ - 28

BS62LV256

R0201-BS62LV256

10

Revision 2.2 April 2001

BSI

BS62LV256

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

R0201-BS62LV256

11

Revision 2.2 April 2001