Datasheet BS62LV2565TI, BS62LV2565TC, BS62LV2565SI, BS62LV2565SC, BS62LV2565PI Datasheet (BSI)

BSI

Very Low Power/Voltage CMOS SRAM 32K X 8 bit

BS62LV2565

 FEATURES

• Wide Vcc operation voltage : 4.5V ~ 5.5V

• Very low power consumption : Vcc = 5.0V C-grade : 35mA (Max.) operating current

I- grade : 40mA (Max.) operating current

0.4uA (Typ.) CMOS standby current

• High speed access time :

-55 55ns (Max.) = 5.0V

-70 70ns (Max.) = 5.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

 DESCRIPTION

The BS62LV2565 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 words by 8 bits and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of

0.4uA and maximum access time of 55ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and three-state output drivers. The BS62LV2565 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV2565 is available in the JEDEC standard 28 pin

330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and

8mmx13.4mm TSOP (normal type).

 PRODUCT FAMILY

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

SPEED

(ns)

Vcc=5.0V Vcc=5.0V Vcc=5.0V

BS62LV2565SC SOP-28 BS62LV2565TC TSOP-28 BS62LV2565PC PDIP-28

O

0

C to +70OC 4.5V ~ 5.5V 55 / 70 1.0uA 35mA BS62LV2565JC SOJ-28 BS62LV2565DC BS62LV2565SI SOP-28 BS62LV2565TI TSOP-28 BS62LV2565PI PDIP-28

O

-40

C to +85OC 4.5V ~ 5.5V 55 / 70 2.0uA 40mA

BS62LV2565JI SOJ-28

BS62LV2565DI

 PIN CONFIGURATIONS

•

1

A14

2

A12

3

A7

4

A6

5

A5

BS62LV2565SC

6

A4

BS62LV2565SI BS62LV2565PC

7

A3

BS62LV2565PI

8

A2

BS62LV2565JC BS62LV2565JI

9

A1

10

A0

11

DQ0

12

DQ1

13

DQ2

14

GND

•

1

OE

2

A11

3

A9

4

A8

5

A13

6

WE

VCC

A14 A12

7 8 9 10

A7

11

A6

12

A5

13

A4

14

A3

BS62LV2565TC BS62LV2565TI

28

VC

C

27

WE

26

A13

25

A8

24

A9

23

A11

22

OE

21

A10

20

CE

19

DQ7

18

DQ6

17

DQ5

16

DQ4

15

DQ3

A10

28

CE

27

DQ7

26

DQ6

25

DQ5

24

DQ4

23

DQ3

22

GND

21

DQ2

20

DQ1

19

DQ0

18

A0

17

A1

16

A2

15

 BLOCK DIAGRAM

A5

A6

A7 A12

A14

A13

A8

A9 A11

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CE

WE

OE

Vdd

Gnd

POWER DISSIPATION

STANDBY

CCSB1

(I

, Max)

Address

Input

Buffer

8

Control

18

Row

Decoder

Data Input Buffer

Data

Output

Buffer

Operating

(ICC, Max)

512

8

Address Input Buffer

A4

DICE

Memory Array

512 x 512

512

Column I/O

Write Driver

Sense Amp

64

Column Decoder

12

A3 A2 A1 A0 A10

PKG

TYPE

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS62LV2565

1

Revision 2.2 April 2001

BSI

 PIN DESCRIPTIONS

Name Function

BS62LV2565

A0-A14 Address Input

CE Chip Enable Input

WE Write Enable Input

OE Output Enable Input

DQ0-DQ7 Data Input/Output

These 15 address input select one of the 32768 x 8-bit wordsin the RAM

CE is active LOW. Chip enables must be active to read from or write to the device. If

chip enable is not active, the device is deselected and is in a standby power mode.

The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

These 8 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Gnd

Power Supply

Ground

 TRUTH TABLE

MODE WE CE OE I/O OPERATION Vcc CURRENT

Not selected X H X High Z I

Output Disabled H L H High Z I

Read H L L D

Write L L X D

OUT

IN

CCSB

I

, I

CCSB1

CC

 ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PARAMETER RATING UNITS

TERM

V

BIAS

T

STG

T

P

OUT

I

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

R0201-BS62LV2565

Terminal Voltage with Respect to GND

Temperature Under Bias -40 to +125

Storage Temperature -60 to +150

Power Dissipation 1.0 W

DC Output Current mA20

-0.5 to +6.0 V

 OPERATING RANGE

RANGE

O

C

O

C

Commercial 0

Industrial -40

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

Input

IN

C

1. This parameter is guaranteed and not tested.

DQ

Capacitance Input/Output Capacitance

2

AMBIENT

TEMPERATURE

O

C to +70

O

(1)

O

C4.5V ~ 5.5V

C to +85

O

C4.5V ~ 5.5V

(TA = 25oC, f = 1.0 MHz)

VIN=0V 6 pF

I/O

V

=0V 8 pF

Vcc

Revision 2.2 April 2001

BSI

BS62LV2565

 DC ELECTRICAL CHARACTERISTICS ( TA = 0

PARAMETER

NAME

IL

V

IH

V

IL

I

IOL Output Leakage Current

VOL Output Low Voltage Vcc = Max, IOL = 2mA

VOH Output High Voltage Vcc = Min, IOH = -1mA

CC

I

CCSB

I

Standby Current-TTL CE = VIH, IDQ = 0mA

CCSB1

I

Standby Current-CMOS

PARAMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage Guaranteed Input High

(2)

Voltage

Input Leakage Current Vcc = Max, V

Vcc = Max, CE = V

I/O

V

= 0V to Vcc

Operating Power Supply Current

CE = V

CE Њ Vcc-0.2V,

IN

Њ

V

o

C to + 70oC )

IN

= 0V to Vcc -- -- 1 uA

IH

, or OE = VIH,

IL

, IDQ = 0mA, F = Fmax

Vcc - 0.2V or V

IN

Љ

0.2V

(1)

MAX.

Vcc=5.0V

-0.5 -- 0.8 V

2.2 -- Vcc+0.2 V

-- -- 1 uA

Vcc=5.0V

(3)

Vcc=5.0V

-- -- 0.4 V

2.4 -- -- V

-- -- 35

-- -- 2

-- 0.4 1.0

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

 DATA RETENTION CHARACTERISTICS ( TA = 0

SYMBOL PAR AMETE R TEST CONDITIONS MIN. TYP.

V

.

RC

o

C to + 70oC )

(1)

MAX. UNITS

DR

Vcc for Data Retention

CE Њ Vcc - 0.2V V

IN Њ Vcc - 0.2V or VIN Љ 0.2V

1.5 -- -- V

UNITS

mA

uA

I

CCDR

t

CDR

t

R

1. Vcc = 1.5V, TA= + 25OC = Read Cycle Time

2. t

RC

 LOW V

DATA RETENTION WAVEFORM (1) ( CE Controlled )

CC

Vcc

CE

R0201-BS62LV2565

Data Retention Current

Chip Deselect to Data Retention Time

Operation Recovery Time

CE Њ Vcc -0.2V V

INЊ Vcc - 0.2V or VIN Љ 0.2V

See Retention Waveform

Data Retention Mode

Vcc

VDR 1.5V

t CDR

≥

CE Vcc - 0.2V

3

-- 0.01 0.40 uA

0---- ns

(2)

T

RC

≥

Vcc

-- -- ns

t R

VIHVIH

Revision 2.2 April 2001

BSI

BS62LV2565

 AC TEST CONDITIONS

Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level

Vcc/0V 5ns

0.5Vcc

 AC TEST LOADS AND WAVEFORMS

5.0V

OUTPUT

INCLUDING JIG AND SCOPE

OUTPUT

Vcc

GND

Ω

1928

100PF

Ω

1020

FIGURE 1A

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

→

90%

←

FIGURE 2

5.0V

OUTPUT

INCLUDING JIG AND SCOPE

Ω667

90%

→

10%

←

1928

5PF

FIGURE 1B

1.73V

5ns

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

 KEY TO SWITCHING WAVEFORMS

Ω

1020

o

C to + 70oC, Vcc=5V )

WAVEFORM INPUTS OUTPUTS

MUST BE STEADY

MAY CHANGE FROM H TO L

MAY CHANGE FROM L TO H

,

DON T CAR ANY CHANG PERMITTED

DOES NOT APPLY

E: CHANGE :

E STATE

MUST BE STEADY

WILL BE CHANGE FROM H TO L

WILL BE CHANGE FROM L TO H

UNKNOWN

CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXOX

PARAMETER

NAME

t

RC

t

AA

t

ACS

t

OE

t

CLZ

t

OLZ

t

CHZ

t

OHZ

t

OH

DESCRIPTION

Read Cycle Time

Address Access Time

Chip Select Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Output Disable to Output in High Z

Output Disable to Output Address Change

BS62LV2565-55

MIN. TYP. MAX.

BS62LV2565-70

MIN. TYP. MAX.

UNIT

55 -- -- 70 -- -- ns

-- -- 55 -- -- 70 ns

-- -- 25 -- -- 35 ns

10 -- -- 10 -- -- ns

0--300--35 ns

0--250--30 ns

10 -- -- 10 -- -- ns

R0201-BS62LV2565

4

Revision 2.2 April 2001

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t AA

t OH

OUT

BS62LV2565

t RC

t OH

READ CYCLE2

CE

D

OUT

READ CYCLE3

ADDRESS

OE

CE

(1,3,4)

(1,4)

t CLZ

t ACS

(5)

t CHZ

(5)

t RC

t AA

t OE

t OH

t OLZ

t OHZ

t CHZ

(5)

(1,5)

t CLZ

t ACS

(5)

D

OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.

4. OE = V

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.

R0201-BS62LV2565

IL .

The parameter is guaranteed but not 100% tested.

IL.

±

5

Revision 2.2 April 2001

BSI

BS62LV2565

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

WRITE CYCLE

JEDEC

PARAMET ER

NAME

t

AVAX

t

E1LWH

t

AVW L

t

AVW H

t

WLWH

t

WHAX

t

WLOZ

t

DVWH

t

WHDX

t

GHOZ

t

WHQX

PARAM ETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

DESCRIPTION

Write Cycle Time

Chip Select to End of Write

Address Set up Time

Address Valid to End of Write

Write Pulse W idth

Write Recover y Time (CE , WE)

Write to Out put in Hi gh Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End ot Write to Output Active

o

C to + 70oC, Vcc=5V )

BS62LV2565-55

MIN. TYP. MAX.

55 -- -- 70 -- -- ns

0 -- -- 0 -- -- ns

55 -- -- 70 -- -- ns

35 -- -- 45 -- -- ns

0 -- -- 0 -- -- ns

-- -- 25 -- -- 30 ns

35 -- -- 40 -- -- ns

0 -- -- 0 -- -- ns

0 --25ns--30 ns

5 -- -- 5 -- -- ns

BS62LV2565-70

MIN. TYP. MAX.

UNIT

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

ADDRESS

OE

CE

WE

(1)

(5)

t AS

(4,10)

t OHZ

D

OUT

D

IN

t AW

t WC

t CW

t WP

(11)

(3)

t WR

(2)

t DH

t DW

R0201-BS62LV2565

6

Revision 2.2 April 2001

BSI

BS62LV2565

WRITE CYCLE2

ADDRESS

CE

WE

D

OUT

D

IN

(1,6)

t AS

(5)

t AW

(4,10)

t WHZ

t WC

t CW

t WP

(11)

(2)

t DH

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. T

WR is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7.

DOUT is the same phase of write data of this write cycle.

OUT is the read data of next address.

8. D

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

The parameter is guaranteed but not 100% tested.

CW is measured from the later of CE going low to the end of write.

11. T

IL ).

±

L = 5pF as shown in Figure 1B.

R0201-BS62LV2565

7

Revision 2.2 April 2001

BSI

 ORDERING INFORMATION

BS62LV2565 X X ˀˀ Y Y

BS62LV2565

SPEED

55 : 55ns 70: 70ns

GRADE

C: +0oC ~ +70oC

o

C ~ +85oC

I: -40

PACKAGE

J: SOJ S: SOP P: PDIP T: TSOP (8mm x 13.4mm) D: DICE

 PACKAGE DIMENSIONS PACKAGE DIMENSIONS

0.020  0.005X45

WITH PLATING

c1c

BASE METAL

θ

b

b1

R0201-BS62LV2565

SOP - 28

8

Revision 2.2 April 2001

BSI

 PACKAGE DIMENSIONS (continued)

HD

c

L

1

14

D

14

28

15

"A"

15

A

12(2x)

A2

A1

"A" DATAIL VIEW

12(2x)

SEATING PLANE

e

b

Seating Plane

BS62LV2565

UNIT

A

A1

A2

b

b1

c

c1

D

E

e

HD

L

L1

y

0

INCH

0.04330.004

0.00450.0026

0.0390.002

0.0090.002

0.0080.001

0.004 ~ 0.008

0.004 ~ 0.006

0.4650.004

0.3150.004

0.0220.004

0.5280.008

+0.008

0.0197

-0.004

0.03150.004

0.004 Max.

0~ 8

SYMBOL

E

y

12(2X)

GAUGE PLANE

12 (2X)

A

L

L1

0.254

0

MM

1.100.10

0.1150.065

1.000.05

0.220.05

0.200.03

0.10 ~ 0.21

0.10 ~ 0.16

11.800.10

8.000.10

0.550.10

13.400.20

+0.20

0.50

-0.10

0.800.10

0.1 Max.

0~ 8

WITH PLATING

1

28

c

BASE METAL

b

c1

b1

SECTION A-A

TSOP - 28

R0201-BS62LV2565

PDIP - 28

9

Revision 2.2 April 2001

BSI

 PACKAGE DIMENSIONS (continued)

SOJ - 28

BS62LV2565

R0201-BS62LV2565

10

Revision 2.2 April 2001

BSI

BS62LV2565

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

R0201-BS62LV2565

11

Revision 2.2 April 2001