Datasheet BS62LV2563PC, BS62LV2563JI, BS62LV2563JC, BS62LV2563DI, BS62LV2563DC Datasheet (BSI)

R0201-BS62LV2563

Revision 2.2 April 2001

1

A6

Very Low Power/Voltage CMOS SRAM 32K X 8 bit

• Wide Vcc operation voltage : 2.4V ~ 3.6V

• Very low power consumption : Vcc = 3.0V C-grade : 20mA (Max.) operating current

I- grade : 25mA (Max.) operating current

0.01uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc = 3.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

The BS62LV2563 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 words by 8 bits and operates from a wide range of 2.4V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of

0.01uA and maximum access time of 70ns in 3V operation. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and three-state output drivers. The BS62LV2563 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV2563 is available in the JEDEC standard 28 pin

330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and

8mmx13.4mm TSOP (normal type).

 DESCRIPTION

 FEATURES

 BLOCK DIAGRAM

 PRODUCT FAMILY

 PIN CONFIGURATIONS

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

Address

Input

Buffer

Row

Decoder

Memory Array

512 x 512

Column I/O

Sense Amp

Write Driver

Column Decoder

Data

Buffer

Output

Address Input Buffer

A3 A2 A1 A0 A10

Data

Buffer

Input

Control

Gnd

Vdd

OE

WE

CE

DQ5

DQ4

A12

A8

A7

8

DQ7

DQ6

DQ3

DQ2

DQ1

DQ0

A11

A9

A5

12

64

512

18

A14

A13

A4

28 27 26 25 24 23 22 21 20 19 18 17 16 15

A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2

1 2 3 4 5 6 7 8 9 10 11 12 13 14

OE

A11

A9 A8

A13

WE

VCC

A14 A12

A7 A6 A5 A4 A3

BS62LV2563

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

DQ1

DQ2

GND

VC

WE

A13

A8

A9

A11

OE

A10

CE

DQ7

DQ6

DQ5

DQ4

DQ3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

C

•

BS62LV2563TC BS62LV2563TI

BS62LV2563SC BS62LV2563SI BS62LV2563PC BS62LV2563PI BS62LV2563JC BS62LV2563JI

POWER DISSIPATION

SPEED

(ns)

STANDBY

(ICCSB1, Max)

Operating

(ICC, Max)

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

Vcc=3.0V Vcc=3.0V Vcc=3.0V

PKG

TYPE

BS62LV2563SC SOP-28 BS62LV2563TC TSOP-28 BS62LV2563PC PDIP-28 BS62LV2563JC SOJ-28 BS62LV2563DC

0

O

C to +70

O

C 2.4V ~ 3.6V 70 0.2uA 20mA

DICE BS62LV2563SI SOP-28 BS62LV2563TI TSOP-28 BS62LV2563PI PDIP-28 BS62LV2563JI SOJ-28 BS62LV2563DI

-40

O

C to +85

O

C 2.4V ~ 3.6V 70 0.4uA 25mA

DICE

BSI

R0201-BS62LV2563

Revision 2.2 April 2001

2

BSI

C

IN

Input Capacitance

VIN=0V 6 pF

C

DQ

Input/Output Capacitance

V

I/O

=0V 8 pF

 ABSOLUTE MAXIMUM RATINGS

(1)

 OPERATING RANGE

 CAPACITANCE

(1)

(TA = 25oC, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

1. This parameter is guaranteed and not tested.

SYMBOL PARAMETER RATING UNITS

V

TERM

Terminal Voltage with Respect to GND

-0.5 to

Vcc+0.5

V

T

BIAS

Temperature Under Bias -40 to +125

O

C

T

STG

Storage Temperature -60 to +150

O

C

P

T

Power Dissipation 1.0 W

I

OUT

DC Output Current 20 mA

BS62LV2563

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial 0

O

C to +70

O

C2.4V ~ 3.6V

Industrial -40

O

C to +85

O

C2.4V ~ 3.6V

Name Function

A0-A14 Address Input

These 15 address inputs select one of the 32768 x 8-bit wordsin the RAM

CE Chip Enable Input

CE is active LOW. Chip enables must be active when data read from or write to the

device. If chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

DQ0-DQ7 Data Input/Output Ports

These 8 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

Gnd

Ground

 TRUTH TABLE

 PIN DESCRIPTIONS

MODE WE CE OE I/O OPERATION Vcc CURRENT

Not selected X H X High Z I

CCSB

, I

CCSB1

Output Disabled H L H High Z I

CC

Read H L L D

OUT

I

CC

Write L L X D

IN

I

CC

SYMBOL PARAMETER CONDITIONS MAX. UNIT

R0201-BS62LV2563

Revision 2.2 April 2001

3

PARAMETER

NAME

PARAMETER TEST CONDITIONS MIN. TYP.

(1)

MAX.

UNITS

V

IL

Guaranteed Input Low Voltage

(2)

Vcc=3.0V

-0.5 -- 0.8 V

V

IH

Guaranteed Input High Voltage

(2)

Vcc=3.0V

2.0 -- Vcc

+0.2

V

I

IL

Input Leakage Current Vcc = Max, V

IN

= 0V to Vcc -- -- 1 uA

IOL Output Leakage Current

Vcc = Max, CE = V

IH

, or OE = VIH,

V

I/O

= 0V to Vcc

-- -- 1 uA

VOL Output Low Voltage Vcc = Max, IOL = 2mA

Vcc=3.0V

-- -- 0.4 V

VOH Output High Voltage Vcc = Min, IOH = -1mA

Vcc=3.0V

2.4 -- -- V

I

CC

Operating Power Supply Current

CE = V

IL

, IDQ = 0mA, F = Fmax

(3)

Vcc=3.0V

-- -- 20 mA

I

CCSB

Standby Current-TTL CE = VIH, IDQ = 0mA

Vcc=3.0V

-- -- 1 mA

I

CCSB1

Standby Current-CMOS

CE Њ Vcc-0.2V, V

IN

Њ

Vcc - 0.2V or V

IN

Љ

0.2V

Vcc=3.0V

-- 0.01 0.2 uA

 DC ELECTRICAL CHARACTERISTICS ( TA = 0

o

C to + 70oC)

BSI

BS62LV2563

SYMBOL PAR AMETER TEST CONDITIONS MIN. TYP.

(1)

MAX. UNITS

V

DR

Vcc for Data Retention

CE Њ Vcc - 0.2V V

IN

Њ

Vcc - 0.2V or V

IN

Љ

0.2V

1.5 -- -- V

I

CCDR

Data Retention Current

CE Њ Vcc -0.2V V

IN

Њ

Vcc - 0.2V or V

IN

Љ

0.2V

-- 0.01 0.20 uA

t

CDR

Chip Deselect to Data Retention Time

0---- ns

t

R

Operation Recovery Time

See Retention Waveform

T

RC

(2)

-- -- ns

 DATA RETENTION CHARACTERISTICS ( TA = 0

o

C to + 70oC)

1. Vcc = 1.5V, TA= + 25OC

2. t

RC

= Read Cycle Time

 LOW V

CC

DATA RETENTION WAVEFORM (1) ( CE Controlled )

CE

Data Retention Mode

Vcc

t CDR

Vcc

t R

VIHVIH

Vcc

VDR 1.5V

≥

CE Vcc - 0.2V

≥

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

RC

.

R0201-BS62LV2563

Revision 2.2 April 2001

4

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS62LV2563-70

MIN. TYP. MAX.

UNIT

t

AVAX

Read Cycle Time

t

RC

70 -- -- ns

t

AVQV

t

AA

Address Access Time

-- -- 70 ns

t

ELQV

t

ACS

Chip Select Access Time

-- -- 70 ns

t

GLQV

t

OE

Output Enable to Output Valid

-- -- 50 ns

t

ELQX

t

CLZ

Chip Select to Output Low Z

10 -- -- ns

t

GLQX

t

OLZ

Output Enable to Output in Low Z

10 -- -- ns

t

EHQZ

t

CHZ

Chip Deselect to Output in High Z

0--35 ns

t

GHQZ

t

OHZ

Output Disable to Output in High Z

0--30 ns

t

AXOX

t

OH

Output Disable to Output Address Change

10 -- -- ns

Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level

Vcc/0V 5ns

0.5Vcc

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

o

C to + 70oC,Vcc=3.0V)

READ CYCLE

 AC TEST CONDITIONS

 AC TEST LOADS AND WAVEFORMS

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

MUST BE STEADY

MAY CHANGE FROM H TO L

DON T CAR ANY CHANG PERMITTED

E: CHANGE :

E STATE

DOES NOT APPLY

MUST BE STEADY

WILL BE CHANGE FROM H TO L

UNKNOWN

CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE

MAY CHANGE FROM L TO H

WILL BE CHANGE FROM L TO H

,

BSI

BS62LV2563

R0201-BS62LV256

Ω667

THEVENIN EQUIVALENT

ALL INPUT PULSES

→

10%

90%

←

Vcc

GND

→

←

5ns

90%

10%

1.73V

OUTPUT

FIGURE 2

3.3V

OUTPUT

INCLUDING JIG AND SCOPE

Ω

1269

Ω

1404

5PF

FIGURE 1B

3.3V

INCLUDING JIG AND SCOPE

Ω

1269

Ω

100PF

FIGURE 1A

1404

OUTPUT

R0201-BS62LV2563

Revision 2.2 April 2001

5

BSI

BS62LV2563

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

t RC

t OH

t AA

D

OUT

ADDRESS

t OH

READ CYCLE3

(1,4)

READ CYCLE2

(1,3,4)

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = V

IL.

3. Address valid prior to or coincident with CE transition low.

4. OE = V

IL .

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.

t CLZ

t CHZ

(5)

D

OUT

CE

(5)

t ACS

t OH

t RC

t OE

D

OUT

CE

OE

ADDRESS

t CLZ

(5)

t ACS

t CHZ

(1,5)

t OHZ

(5)

t OLZ

t AA

±

R0201-BS62LV2563

Revision 2.2 April 2001

6

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS62LV2563-70

MIN. TYP. MAX.

UNIT

t

AVAX

Write Cycle Time

t

WC

70 -- -- ns

t

E1LWH

t

CW

Chip Select to End of Write

70 -- -- ns

t

AVWL

t

AS

Address Set up Time

0---- ns

t

AVWH

t

AW

Address Valid to End of Write

70 -- -- ns

t

WLWH

t

WP

Write Pulse Width

50 -- -- ns

t

WHAX

t

WR

Write Recovery Time (CE , WE)

0---- ns

t

WLOZ

t

WHZ

Write to Output in High Z

-- -- 30 ns

t

DVWH

t

DW

Data to Write Time Overlap

40 -- -- ns

t

WHDX

t

DH

Data Hold from Write Time

0---- ns

t

GHOZ

t

OHZ

Output Disable to Output in High Z

0--30 ns

t

WHQX

t

OW

End ot Write to Output Active

5---- ns

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

o

C to + 70oC, Vcc=3.0V )

WRITE CYCLE

BSI

BS62LV2563

WRITE CYCLE1

(1)

t WR

(3)

t CW

(11)

(2)

t WP

t AW

t OHZ

(4,10)

t AS

t DH

t DW

D

IN

D

OUT

WE

CE

OE

ADDRESS

(5)

t WC

 SWITCHING WAVEFORMS (WRITE CYCLE)

R0201-BS62LV2563

Revision 2.2 April 2001

7

BSI

BS62LV2563

WRITE CYCLE2

(1,6)

t WC

t CW

(11)

(2)

t WP

t AW

t WHZ

(4,10)

t AS

t DH

t DW

D

IN

D

OUT

WE

CE

ADDRESS

(5)

t DH

(7) (8)

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. T

WR is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

IL ).

7.

DOUT is the same phase of write data of this write cycle.

8. D

OUT is the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

L = 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

11. T

CW is measured from the later of CE going low to the end of write.

±

R0201-BS62LV2563

Revision 2.2 April 2001

8

PACKAGE

J: SOJ S: SOP P: PDIP T: TSOP (8mm x 13.4mm) D: DICE

 ORDERING INFORMATION

BSI

BS62LV2563 X X ˀˀ Y Y

GRADE

C: +0oC ~ +70oC I: -40

o

C ~ +85oC

SPEED

70: 70ns

BS62LV2563

 PACKAGE DIMENSIONS PACKAGE DIMENSIONS

θ

b

BASE METAL

WITH PLATING

c1c

b1

SOP - 28

0.020  0.005X45

R0201-BS62LV2563

Revision 2.2 April 2001

9

 PACKAGE DIMENSIONS (continued)

BSI

BS62LV2563

PDIP - 28

1

14

D

1

HD

c

L

28

15

"A"

15

28

WITH PLATING

SECTION A-A

BASE METAL

c

c1

b1

b

12(2X)

12 (2X)

A

SEATING PLANE

"A" DATAIL VIEW

A1

A2

Seating Plane

12(2x)

E

b

12(2x)

e

GAUGE PLANE

L1

L

A

0

0.254

y

0.004 ~ 0.006

0.004 ~ 0.008

0.00450.0026

0.03150.004

0.0197

0.0220.004

0.0080.001

0~ 8

0.004 Max.

0.5280.008

0.3150.004

0.4650.004

0.0090.002

0.0390.002

0.04330.004

INCH

c1

L1

0

y

D

E

HD

L

e

SYMBOL

c

A

A1

b

A2

b1

UNIT

0.10 ~ 0.16

0.800.10

0~ 8

0.1 Max.

0.550.10

11.800.10

0.50

13.400.20

8.000.10

-0.004

+0.008

-0.10

+0.20

0.1150.065

MM

0.10 ~ 0.21

0.200.03

0.220.05

1.000.05

1.100.10

TSOP - 28

R0201-BS62LV2563

Revision 2.2 April 2001

10

BSI

BS62LV2563

 PACKAGE DIMENSIONS (continued)

SOJ - 28

R0201-BS62LV2563

Revision 2.2 April 2001

11

BSI

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

BS62LV2563