• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns(Max.) at Vcc = 3.0V
-10 100ns(Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV2007HC 0
BS62LV2007HI -40
OPERATING
TEMPERATURE
O
C to +70
O
C to +85
O
C70/100 6 uA 0.7 uA 35 mA 20 mA
O
C
2.4V ~5.5V
Vcc
RANGE
DESCRIPTION
The BS62LV2007 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates in a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2007 is available in the JEDEC standard 36 pin
Mini BGA 6x8 mm.
SPEED
(ns)
Vcc=
3.0V
70/100 25 uA 1.5 uA 40 mA 25 mA
POWER DISSIPATION
STANDBY
(I
, Max)
CCSB1
Vcc=
5.0V
Vcc=
3.0V
Operating
(ICC, Max)
Vcc=
5.0V
Vcc=
3.0V
BGA-36-
PKG
TYPE
0608
PIN CONFIGURATIONS
BLOCK DIAGRAM
A13
A17
A15
A16
A14
A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
Vdd
Gnd
A7
A6
A5
A4
WE
OE
OE
Address
Input
Buffer
20
8
8
Control
Decoder
Data
Input
Buffer
Data
Output
Buffer
Row
1024
8
8
A11
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV2007
1
Memory Array
1024 x 2048
2048
Column I/O
Write Driver
Sense Amp
256
Column Decoder
16
Address Input Buffer
A9
A8 A3 A2 A1A10
Revision 2.0
April 2002
A0
Page 2
BSI
PIN DESCRIPTIONS
NameFunction
BS62LV2007
A0-A17 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
DQ0 – DQ7 Data Input/Output
These 18 address inputs select one of the 262,144 x 8-bit words in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc
Gnd
Power Supply
Ground
TRUTH TABLE
MODEWECE1CE2OEI/O OPERATIONVcc CURRENT
Not selected
(Power Down)
Output DisabledHLHHHigh ZI
ReadHLHLD
WriteLLHXD
XHXX
XXLX
High Z
OUT
IN
I
CCSB
I
I
, I
CCSB1
CC
CC
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOLPARAMETERRATINGUNITS
TERM
V
BIAS
T
STG
T
T
P
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS62LV2007
R0201-BS62LV2007
Terminal Voltage with
Respect to GND
Temperature Under BiasC-40 to +125
Storage TemperatureC-60 to +150
Power Dissipation1.0W
DC Output CurrentmA20
-0.5 to
Vcc+0.5
OPERATING RANGE
V
O
O
Commercial0
Industrial-40
CAPACITANCE
RANGE
SYMBOLPARAMETERCONDITIONSMAX.UNIT
C
C
1. This parameter is guaranteed and not tested.
IN
DQ
Input
Capacitance
Input/Output
Capacitance
2
AMBIENT
TEMPERATURE
O
C to +70
O
(1)
(TA = 25oC, f = 1.0 MHz)
O
C2.4V ~ 5.5V
C to +85
O
C2.4V ~ 5.5V
VIN=0V6pF
I/O
V
=0V8pF
Vcc
Revision 2.0
April 2002
Page 3
BSI
BS62LV2007
DC ELECTRICAL CHARACTERISTICS ( TA = 0
PAR AM ETE R
NAME
V
V
I
IOL Output Leakage Current
VOL Output Low Voltage Vcc = Max, IOL = 2mA
VOH Output High Voltage Vcc = Min, IOH = -1mA
I
I
I
IL
IH
IL
CC
CCSB
Standby Current-TTL
CCSB1
Standby Current-CMOS
PAR AM ETE R TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage CurrentVcc = Max, V
Vcc = Max, CE1= V
OE = V
Operating Power Supply
Current
CE1 = VIL, or CE2 = VIH,
DQ
= 0mA, F = Fmax
I
CE1 = V
DQ
I
= 0mA, F = Fmax
CE1ЊVcc-0.2V, CE2Љ0.2V,
IN
Њ
V
Vcc-0.2V or V
o
C to + 70oC )
(1)
MAX.
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
IN
= 0V to Vcc-- -- 1 uA
IH
I/O
, V
= 0V to Vcc
IH
, or CE2 = VIL,
IH
, CE2= V
(3)
(3)
IN
Љ
0.2V
IL,
or
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
-0.5 -- 0.8 V
2.0
2.2
-- Vcc+0.2 V
-- -- 1 uA
-- -- 0.4 V
2.4 -- -- V
-- -- 20
-- -- 35
-- -- 1
-- -- 2
-- 0.1 0.7
-- 0.6 6
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
DATA RETENTION CHARACTERISTICS ( TA = 0
SYMBOL PAR AM ETE R TEST CONDITIONS MIN. TYP.
V
DR
.
RC
Vcc for Data Retention
o
C to + 70oC )
CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,
IN Њ
V
Vcc - 0.2V or V
IN Љ
0.2V
(1)
MAX. UNITS
1.5 -- -- V
UNITS
mA
mA
uA
I
CCDR
t
CDR
t
R
1. Vcc = 1.5V, TA= + 25OC
2. t
= Read Cycle Time
RC
LOW V
DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
CC
Vcc
CE1
LOW V
DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
CC
Vcc
CE2
R0201-BS62LV2007
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,
IN Њ
V
Vcc - 0.2V or V
IN Љ
See Retention Waveform
Data Retention Mode
≥
Vcc
VDR 1.5V
t CDR
≥
CE1 Vcc - 0.2V
Data Retention Mode
Vcc
VDR Њ 1.5V
t CDR
VIL
CE2 Љ 0.2V
3
0.2V
-- 0.01 0.5 uA
0 -- -- ns
(2)
T
RC
Vcc
-- -- ns
t R
VIHVIH
Vcc
t R
VIL
Revision 2.0
April 2002
Page 4
BSI
BS62LV2007
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
OUTPUT
Vcc
GND
1269
100PF
Ω
1404
FIGURE 1A
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
→
←
OUTPUT
Ω667
90%
90%
FIGURE 2
3.3V
INCLUDING
JIG AND
SCOPE
→
←
1.73V
10%
5ns
Ω
AC ELECTRICAL CHARACTERISTICS ( TA = 0
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
E2HOV
t
GLQV
t
E1LQX
t
E2HOX
t
GLQX
t
E1HQZ
t
E2HQZ
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ1
t
OHZ
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time(CE1)
Chip Select Access Time(CE2)
Output Enable to Output Valid
Chip Select to Output Low Z(CE1)
Chip Select to Output Low Z(CE2)
Output Enable to Output in Low Z
Chip Deselect to Output in High Z(CE1)
Chip Deselect to Output in High Z(CE2)
Output Disable to Output in High Z
Output Disable to Output Address Change
Ω
1269
5PF
Ω
1404
FIGURE 1B
o
DESCRIPTION
KEY TO SWITCHING WAVEFORMS
WAVEFORMINPUTSOUTPUTS
C to + 70oC, Vcc = 3.0V )
BS62LV2007-70
MIN. TYP. MAX.
70----100----ns
----70----100ns
----70----100ns
----70----100ns
----35----50ns
10----15----ns
10----15----ns
10----15----ns
0--350--40ns
0--350--40ns
0--300--35ns
10----15----ns
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CAR
ANY CHANG
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
E:CHANGE :
ESTATE
MIN. TYP. MAX.
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
BS62LV2007-10
UNIT
R0201-BS62LV2007
R0201-BS62LV2007
4
Revision 2.0
April 2002
Page 5
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
(1,2,4)
t AA
t OH
OUT
BS62LV2007
t RC
t OH
READ CYCLE2
CE1
CE2
D
OUT
READ CYCLE3
ADDRESS
OE
CE1
(1,3,4)
(1,4)
t CLZ
(5)
t ACS1
t ACS2
t CLZ1
(5)
t AA
t OLZ
t ACS1
t OE
t RC
t CHZ1, t CHZ2
t OH
(5)
t OHZ
(1,5)
t CHZ1
(5)
CE2
D
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE1 = V
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV2007
R0201-BS62LV2007
IL .
OUT
t ACS2
(2,5)
(5)
t CLZ2
IL and CE2= VIH.
t CHZ2
±
5
Revision 2.0
April 2002
Page 6
BSI
BS62LV2007
AC ELECTRICAL CHARACTERISTICS ( TA = 0
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
E2LAX
t
WLOZ
t
DVWH
t
WHDX
t
GHOZ
t
WHQX
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1
t
WR2
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Set up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time(CE1 , WE)
Write Recovery Time(CE2)
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
o
C to + 70oC, Vcc = 3.0V )
BS62LV2007-70
MIN. TYP. MAX.
70----100----ns
70----100----ns
0----0----ns
70----100----ns
35----50----ns
0----0----ns
0----0----ns
0--300--40 ns
30----40----ns
0----0----ns
0--300--40 ns
5----10---- ns
BS62LV2007-10
MIN. TYP. MAX.
UNIT
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
ADDRESS
OE
CE1
CE2
WE
(1)
(5)
(5)
t AS
(4,10)
t OHZ
D
OUT
t AW
t WC
t CW
t CW
t WP
(11)
(11)
(2)
t DW
t WR1
t WR2
t DH
(3)
(3)
D
IN
R0201-BS62LV2007
R0201-BS62LV2007
6
Revision 2.0
April 2002
Page 7
BSI
BS62LV2007
WRITE CYCLE2
ADDRESS
CE1
CE2
WE
D
OUT
D
IN
(1,6)
t AS
(5)
(5)
t AW
(4,10)
t WHZ
t WC
t CW
t CW
t WP
(11)
(11)
(2)
t DW
t WR2
t DH
(3)
t DH
(7)(8)
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
WR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
3. T
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
7.
DOUT is the same phase of write data of this write cycle.
OUT is the read data of next address.
8. D
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
parameter is guaranteed but not 100% tested.
11. T
CW is measured from the later of CE1 going low or CE2 going high to the end of write.
IL ).
±
L = 5pF as shown in Figure 1B. The
R0201-BS62LV2007
7
Revision 2.0
April 2002
Page 8
BSI
ORDERING INFORMATION
BS62LV2007X Xˀˀ Y Y
BS62LV2007
SPEED
70: 70ns
10: 100ns
GRADE
o
C: +0
C ~ +70oC
o
I: -40
C ~ +85oC
PACKAGE
H : 36 Pin Mini BGA (6mm x 8mm)
PACKAGE DIMENSIONS
A1 Ball Pad Corner
1
.
0
±
0
.
8
6.0±0.1
TOP VIEW
.
X
A
M
4
.
1
SIDE VIEW
A1 Ball Pad Corner
5
7
3
.
1
5
2
.
5
5
7
.
0
1.1253.75
6453
12
A
B
C
D
E
F
G
H
DETAIL A
0.75
DETAIL A
SOLDER BALL
)
s
l
l
a
b
6
3
x
(
5
0
.
0
±
5
3
.
0
O
BOTTOM VIEW ( BALL SIDE )
5
0
.
0
±
5
2
.
0
NOTE:
1. PIN#1 DOT MARKING IS BY LASER OR PAD PRINT.
R0201-BS62LV2007
36 mini-BGA (6 x 8)
8
Revision 2.0
April 2002
Page 9
BSI
BS62LV2007
REVISION HISTORY
Revision Description Date Note
1.0 Data Sheet release Jan. 10, 2002
2.0 Modify some AC parameters.
Modify 5V ICCSB1_Max(I-grade)
from 10uA to 25uA.
April,12,2002
R0201-BS62LV2007
9
Revision 2.0
April 2002
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