Datasheet BS62LV2003TI, BS62LV2003TC, BS62LV2003STI, BS62LV2003STC, BS62LV2003SI Datasheet (BSI)

BSI

Very Low Power/Voltage CMOS SRAM 256K X 8 bit

BS62LV2003

 FEATURES

• Wide Vcc operation voltage : 2.4V ~ 3.6V

• Very low power consumption : Vcc = 3.0V C-grade : 20mA (Max.) operating current

I- grade : 25mA (Max.) operating current

0.1uA (Typ.) CMOS standby current

 DESCRIPTION

The BS62LV2003 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.4V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of

0.1uA and maximum access time of 70ns in 3.0V operation.

• High speed access time :

-70 70ns(Max.) at Vcc = 3.0V

-10 100ns(Max.) at Vcc = 3.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE2, CE1, and OE options

Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV2003 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV2003 is available in the JEDEC standard 32 pin 450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.

 PRODUCT FAMILY

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

SPEED

(ns)

Vcc= 3.0V Vcc=3.0V Vcc=3.0V BS62LV2003TC TSOP-32 BS62LV2003STC STSOP-32

O

+0

C to +70OC 2.4V ~ 3.6V 70 / 100 0.7uA 20mA BS62LV2003SC BS62LV2003TI TSOP-32 BS62LV2003STI STSOP-32

O

C to +85OC 2.4V ~3.6V 70 / 100 1.5uA 25mA

-40

BS62LV2003SI

POWER DISSIPATION

STANDBY

CCSB1

(I

, Max)

Operating

(ICC, Max)

PKG TYPE

SOP-32

 PIN CONFIGURATIONS

•

1

A11

2

A9

3

A8

4

A13

5

WE

6

CE2

A15

VCC

A17 A16 A14 A12

7 8 9 10 11 12 13

A7

14

A6

15

A5

16

A4

A17 A16 A14 A12

DQ0 DQ1 DQ2

GND

A7 A6 A5 A4 A3 A2 A1 A0

BS62LV2003TC BS62LV2003STC BS62LV2003TI BS62LV2003STI

•

1 2 3 4 5 6 7

BS62LV2003SC BS62LV2003SI

8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3

32

OE

31

A10

30

CE1

29

DQ7

28

DQ6

27

DQ5

26

DQ4

25

DQ3

24

GND

23

DQ2

22

DQ1

21

DQ0

20

A0

19

A1

18

A2

17

A3

 BLOCK DIAGRAM

A13

A17 A15 A16 A14 A12

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CE1

CE2

Vdd

Gnd

A7 A6 A5 A4

WE

OE

Address

Input

Buffer

20

8

Control

Decoder

Data Input Buffer

Data

Output

Buffer

Row

1024

8

A11

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS62LV2003

1

Memory Array

1024 x 2048

2048

Column I/O

Write Driver

Sense Amp

256

Column Decoder

16

Address Input Buffer

A9

A8 A3 A2 A1 A10

Revision 2.4 April 2002

A0

BSI

 PIN DESCRIPTIONS

Name Function

BS62LV2003

A0-A17 Address Input

CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input

WE Write Enable Input

OE Output Enable Input

DQ0-DQ7 Data Input/Output

These 18 address inputs select one of the 262,144 x 8-bit words in the RAM

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when

data read from or write to the device. If either chip enable is not active, the device is

deselected and is in a standby power mode. The DQ pins will be in the high

impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

These 8 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Gnd

Power Supply

Ground

 TRUTH TABLE

MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT

Not selected

(Power Down)

Output Disabled H L H H High Z I

Read H L H L D

Write L L H X D

XHXX

XXLX

High Z I

OUT

IN

CCSB

I

, I

CCSB1

CC

 ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PARAMETER RATING UNITS

TERM

V

BIAS

T

STG

T

P

OUT

I

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

R0201-BS62LV2003

Terminal Voltage with Respect to GND

Temperature Under Bias C-40 to +125

Storage Temperature C-60 to +150

Power Dissipation 1.0 W

DC Output Current 20 mA

-0.5 to

Vcc+0.5

 OPERATING RANGE

RANGE

V

O

Commercial 0

Industrial -40

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

C

1. This parameter is guaranteed and not tested.

IN

DQ

Input Capacitance Input/Output Capacitance

2

AMBIENT

TEMPERATURE

O

C to +70

O

(1)

(TA = 25oC, f = 1.0 MHz)

O

C2.4V ~ 3.6V

C to +85

O

C2.4V ~3.6V

VIN=0V 6 pF

I/O

V

=0V 8 pF

Vcc

Revision 2.4 April 2002

BSI

 DC ELECTRICAL CHARACTERISTICS ( TA = 0

PAR AMETER

NAME

V

I

V

I

IL

IH

IL

OL

OH

CC

PAR AMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage Guaranteed Input High

(2)

Voltage

Input Leakage Current Vcc = Max, V

Output Leakage Current

Output Low Voltage Vcc = Max, IOL = 2mA

Output High Voltage Vcc = Min, IOH = -1mA

Operating Power Supply Current

Vcc = Max, CE1= V

IH

I/O

OE = V

, V

CE1 = VIL, or CE2 = VIH,

DQ

= 0mA, F = Fmax

I

BS62LV2003

o

C to + 70oC )

(1)

MAX.

Vcc=3.0V

IN

= 0V to Vcc -- -- 1 uA

IH

, CE2= V

IL,

or

= 0V to Vcc

Vcc=3.0V

(3)

Vcc=3.0V

-0.5 -- 0.8 V

2.0 -- Vcc+0.2 V

-- -- 1 uA

-- -- 0.4 V

2.4----V

-- -- 20 mA

UNITS

I

CCSB

CCSB1

Standby Current-TTL

Standby Current-CMOS

CE1 = V I

CE1ЊVcc-0.2V, CE2Љ0.2V, V

IH

DQ

, or CE2 = VIL,

= 0mA, F = Fmax

IN

Њ

Vcc-0.2V or V

(3)

IN

Љ

0.2V

Vcc=3.0V

-- -- 1 mA

-- 0.1 0.7 uA

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

 DATA RETENTION CHARACTERISTICS ( TA = 0

SYMBOL PAR AMETE R TEST CONDITIONS MIN. TYP.

V

I

CCDR

t

CDR

.

RC

o

C to + 70oC )

(1)

MAX. UNITS

DR

Vcc for Data Retention

Data Retention Current

CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V, V

IN Њ Vcc - 0.2V or VIN Љ 0.2V

CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V, V

IN Њ Vcc - 0.2V or VIN Љ 0.2V

Chip Deselect to Data Retention Time

t

R

Operation Recovery Time

See Retention Waveform

1.5 -- -- V

-- 0.01 0.5 uA

0 -- -- ns

(2)

T

RC

-- -- ns

1. Vcc = 1.5V, TA= + 25OC

= Read Cycle Time

2. t

RC

 LOW V

Vcc

CE1

DATA RETENTION WAVEFORM (1) ( CE1 Controlled )

CC

Data Retention Mode

Vcc

t CDR

CE1 Vcc - 0.2V

≥

VDR 1.5V

≥

Vcc

t R

VIHVIH

 LOW V

DATA RETENTION WAVEFORM (2) ( CE2 Controlled )

CC

Vcc

CE2

R0201-BS62LV2003

Data Retention Mode

Vcc

VDR Њ 1.5V

t CDR

VIL

CE2 Љ 0.2V

3

Vcc

t R

VIL

Revision 2.4 April 2002

BSI

BS62LV2003

 AC TEST CONDITIONS

Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level

Vcc/0V 5ns

0.5Vcc

 AC TEST LOADS AND WAVEFORMS

3.3V

OUTPUT

INCLUDING JIG AND SCOPE

OUTPUT

Vcc

GND

1269

100PF

1404

FIGURE 1A

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

→

Ω

←

FIGURE 2

90%

3.3V

OUTPUT

INCLUDING JIG AND SCOPE

Ω667

90%

→

←

1.73V

10%

5ns

Ω

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

E1LQV

t

E2HOV

t

GLQV

t

E1LQX

t

E2HOX

t

GLQX

t

E1HQZ

t

E2HQZ

t

GHQZ

t

AXOX

PARAMETER

NAME

t

RC

t

AA

t

ACS1

t

ACS2

t

OE

t

CLZ1

t

CLZ2

t

OLZ

t

CHZ1

t

CHZ2

t

OHZ

t

OH

DESCRIPTION

Read Cycle Time

Address Access Time

Chip Select Access Time (CE1)

Chip Select Access Time (CE2)

Output Enable to Output Valid

Chip Select to Output Low Z (CE1)

Chip Select to Output Low Z (CE2)

Output Enable to Output in Low Z

Chip Deselect to Output in High Z (CE1)

Chip Deselect to Output in High Z (CE2)

Output Disable to Output in High Z

Output Disable to Output Address Change

Ω

1269

5PF

1404

FIGURE 1B

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Ω

o

C to + 70oC, Vcc = 3.0V )

BS62LV2003-70

MIN. TYP. MAX.

70 -- -- 100 -- -- ns

-- -- 70 -- -- 100 ns

-- -- 35 -- -- 50 ns

10 -- -- 15 -- -- ns

0--350--40ns

0--300--35ns

10 -- -- 15 -- -- ns

MUST BE STEADY

MAY CHANGE FROM H TO L

MAY CHANGE FROM L TO H

,

DON T CAR ANY CHANG PERMITTED

DOES NOT APPLY

BS62LV2003-10

MIN. TYP. MAX.

MUST BE STEADY

WILL BE CHANGE FROM H TO L

WILL BE CHANGE FROM L TO H

E: CHANGE :

E STATE

UNKNOWN

CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE

UNIT

R0201-BS62LV2003

4

Revision 2.4 April 2002

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t AA

t OH

OUT

BS62LV2003

t RC

t OH

READ CYCLE2

CE1

CE2

D

OUT

READ CYCLE3

ADDRESS

OE

CE1

(1,3,4)

(1,4)

t CLZ

(5)

t ACS1

t ACS2

t CLZ1

(5)

t AA

t OLZ

t ACS1

t OE

t RC

t CHZ1, t CHZ2

t OH

(5)

t OHZ

(1,5)

t CHZ1

(5)

CE2

D

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = V

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = V

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.

R0201-BS62LV2003

IL .

OUT

t ACS2

(2,5)

(5)

t CLZ2

IL and CE2= VIH.

t CHZ2

±

5

Revision 2.4 April 2002

BSI

BS62LV2003

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

WRITE CYCLE

JEDEC

PARAMETER

NAME

tt

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

E2LAX

t

WLOZ

t

DVWH

t

WHDX

t

GHOZ

t

WHQX

PARAMETER

NAME

WC

t

CW

t

AS

t

AW

t

WP

t

WR1

t

WR2

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

DESCRIPTION

Write Cycle Time

Chip Select to End of Write

Address Set up Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time (CE1 , WE)

Write Recovery Time (CE2)

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

o

C to + 70oC, Vcc = 3.0V )

BS62LV2003-70

MIN. TYP. MAX.

70 -- -- 100 -- -- ns

0 -- -- 0 -- -- ns

70 -- -- 100 -- -- ns

35 -- -- 50 -- -- ns

0 -- -- 0 -- -- ns

0--300--40 ns

30 -- -- 40 -- -- ns

0 -- -- 0 -- -- ns

0--300--40 ns

5----10---- ns

BS62LV2003-10

MIN. TYP. MAX.

UNIT

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

ADDRESS

OE

CE1

CE2

WE

(1)

(5)

t AS

(4,10)

t OHZ

D

OUT

t AW

t WC

t CW

t WP

(11)

(3)

t WR1

t WR2

(3)

(2)

t DH

t DW

D

IN

R0201-BS62LV2003

6

Revision 2.4 April 2002

BSI

BS62LV2003

WRITE CYCLE2

ADDRESS

CE1

CE2

WE

D

OUT

D

IN

(1,6)

t AS

(5)

t AW

(4,10)

t WHZ

t WC

t CW

t WP

(11)

t WR2

(3)

(2)

t DH

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. T

WR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write

cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7.

DOUT is the same phase of write data of this write cycle.

OUT is the read data of next address.

8. D

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

parameter is guaranteed but not 100% tested.

CW is measured from the later of CE1 going low or CE2 going high to the end of write.

11. T

IL ).

±

L = 5pF as shown in Figure 1B. The

R0201-BS62LV2003

7

Revision 2.4 April 2002

BSI

 ORDERING INFORMATION

BS62LV2003 X X ˀˀ Y Y

BS62LV2003

SPEED

70: 70ns 10: 100ns

GRADE

o

C ~ +70oC

C: +0

o

C ~ +85oC

I: -40

PACKAGE

T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) S: SOP

 PACKAGE DIMENSIONS

R0201-BS62LV2003

STSOP - 32

8

Revision 2.4 April 2002

BSI

 PACKAGE DIMENSIONS (continued)

BS62LV2003

TSOP - 32

SOP -32

WITH PLATING

c c1

BASE METAL

b

b1

SECTION A-A

R0201-BS62LV2003

9

Revision 2.4 April 2002

BSI

BS62LV2003

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

2.3 Modify Standby Current (Typ. and Max.)

2.4 Modify some AC parameters April,11,2002

Jun. 29, 2001

R0201-BS62LV2003

10

Revision 2.4 April 2002