Datasheet BS62LV2000TI, BS62LV2000TC, BS62LV2000STI, BS62LV2000STC, BS62LV2000SI Datasheet (BSI)

BSI

Very Low Power/Voltage CMOS SRAM 256K X 8 bit

BS62LV2000

 FEATURES

• Wide Vcc operation voltage : 2.7V ~ 5.5V

• Very low power consumption : Vcc = 3.0V C-grade : 20mA (Max.) operating current

I- grade : 25mA (Max.) operating current

0.15uA (Typ.) CMOS standby current

Vcc = 5.0V C-grade : 40mA (Max.) operating current

I- grade : 45mA (Max.) operating current 3uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns(Max.) at Vcc = 3.0V

-10 100ns(Max.) at Vcc = 3.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

 DESCRIPTION

The BS62LV2000 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.7V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of

0.15uA and maximum access time of 70ns in 3V operation. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV2000 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV2000 is available in the JEDEC standard 32 pin 450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE2, CE1, and OE options

• All I/O pins are 3V/5V tolerant

 PRODUCT FAMILY

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

SPEED

(ns)

Vcc=3V Vcc=5V Vcc=3V Vcc=5V Vcc=3V

BS62LV2000TC TSOP-32

O

C to +70

BS62LV2000STC STSOP-32

+0

O

2.7V ~ 5.5V 70 / 100 10uA 3uA mA40 20mA

C

BS62LV2000SC

BS62LV2000TI TSOP-32

-

40

BS62LV2000STI STSOP-32

C to +85

O

C 2.7V ~ 5.5V 70 / 100 20uA 5uA 45mAO25mA

BS62LV2000SI

 PIN CONFIGURATIONS

A11

A13

CE2

A15

VCC

A17 A16 A14 A12

WE

•

1 2

A9

3

A8

4 5 6

BS62LV2000TC

7

BS62LV2000STC

8

BS62LV2000TI

9

BS62LV2000STI

10 11 12 13

A7

14

A6

15

A5

16

A4

•

A17 A16 A14 A12

DQ0 DQ1 DQ2

GND

A7 A6 A5 A4 A3 A2 A1 A0

1 2 3 4 5 6 7

BS62LV2001SC BS62LV2001SI

8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3

OE

32

A10

31

CE1

30

DQ7

29

DQ6

28

DQ5

27

DQ4

26

DQ3

25

GND

24

DQ2

23

DQ1

22

DQ0

21

A0

20

A1

19

A2

18

A3

17

 BLOCK DIAGRAM

A13

A17 A15 A16 A14 A12

A7 A6 A5 A4

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6 DQ7

CE1

CE2

WE

OE

OE Vdd

Gnd

POWER DISSIPATION

STANDBY

(I

, Max)

CCSB1

Address

Input

Buffer

8

Control

20

Data Input Buffer

Data

Output

Buffer

Operating

CC

(I

Row

Decoder

, Max)

1024

8

PKG TYPE

SOP

Memory Array

1024 x 2048

Column I/O

Write Driver

Sense Amp

Column Decoder

Address Input Buffer

A8 A3 A2 A1 A10

A9

A11

-

2048

256

16

32

A0

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS62LV2000

1

Revision 2.3 April 2002

BSI

 PIN DESCRIPTIONS

Name Function

BS62LV2000

A0-A17 Address Input

CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input

WE Write Enable Input

OE Output Enable Input

DQ0-DQ7 Data Input/Output

These 18 address inputs select one of the 262,144 x 8-bit words in the RAM

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when

data read from or write to the device. If either chip enable is not active, the device is

deselected and is in a standby power mode. The DQ pins will be in the high

impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

These 8 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Gnd

Power Supply

Ground

 TRUTH TABLE

MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT

Not selected

(Power Down)

Output Disabled H L H H High Z I

Read H L H L D

Write L L H X D

XHXX

XXLX

High Z I

OUT

IN

CCSB

I

, I

CCSB1

CC

 ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PARAMETER RATING UNITS

TERM

V

BIAS

T

STG

T

P

OUT

I

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

R0201-BS62LV2000

Terminal Voltage with Respect to GND

Temperature Under Bias C-40 to +125

Storage Temperature C-60 to +150

Power Dissipation 1.0 W

DC Output Current mA20

-0.5 to

Vcc+0.5

 OPERATING RANGE

RANGE

V

O

Commercial 0

Industrial -40

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

Input

IN

C

1. This parameter is guaranteed and not tested.

DQ

Capacitance Input/Output Capacitance

2

AMBIENT

TEMPERATURE

O

C to +70

O

(1)

(TA = 25oC, f = 1.0 MHz)

O

C2.7V ~ 5.5V

C to +85

O

C2.7V ~ 5.5V

VIN=0V 6 pF

I/O

V

=0V 8 pF

Vcc

Revision 2.3 April 2002

BSI

 DC ELECTRICAL CHARACTERISTICS ( TA = 0

PAR AMET ER

NAME

IL

V

IH

V

IL

I

OL

I

OL

V

OH

V

CC

I

CCSB

I

CCSB1

I

PAR AMET ER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage Guaranteed Input High

(2)

Voltage

Input Leakage Current Vcc = Max, V

Output Leakage Current

Output Low Voltage Vcc = Max, IOL = 2mA

Output High Voltage Vcc = Min, IOH = -1mA

Operating Power Supply Current

Standby Current-TTL

Standby Current-CMOS

Vcc = Max, CE1 = V or OE = VIH, V

Vcc = Max, CE1= VIL, CE2=V IDQ = 0mA, F = Fmax

Vcc = Max, CE1 = V IDQ = 0mA

Vcc = Max, CE1ЊVcc-0.2V or CE2Љ0.2V ;V

IN

Љ

0.2V

V

o

C to + 70oC )

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

IN

= 0V to Vcc -- -- 1 uA

IH

or CE2=V

I/O

= 0V to Vcc

(3)

IH

or CE2=V

IN

Њ

Vcc - 0.2V or

IL

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

IH

Vcc=5.0V

Vcc=3.0V

IL

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

BS62LV2000

(1)

MAX.

-0.5 -- 0.8 V

2.0

2.2

-- -- 1 uA

-- -- 0.4 V

2.4 -- -- V

-- -- 20

-- -- 40

-- -- 1

-- -- 2

-- 0.15 3

-- 3 10

-- Vcc+0.2 V

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

 DATA RETENTION CHARACTERISTICS ( TA = 0

SYMBOL PAR AMETER TEST CONDITIONS MIN. TYP.

V

.

RC

o

C to + 70oC )

(1)

MAX. UNITS

DR

Vcc for Data Retention

CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V, V

IN Њ Vcc - 0.2V or VIN Љ 0.2V

1.5 -- -- V

UNITS

mA

uA

I

CCDR

t

CDR

t

R

Data Retention Current

Chip Deselect to Data Retention Time

Operation Recovery Time

1. Vcc = 1.5V, TA= + 25OC = Read Cycle Time

2. t

RC

 LOW V

DATA RETENTION WAVEFORM (1) ( CE1 Controlled )

CC

Vcc

CE1

 LOW V

DATA RETENTION WAVEFORM (2) ( CE2 Controlled )

CC

Vcc

CE2

CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V, V

IN Њ Vcc - 0.2V or VIN Љ 0.2V

See Retention Waveform

Data Retention Mode

Vcc

VDR 1.5V

t CDR

≥

CE1 Vcc - 0.2V

Data Retention Mode

Vcc

VDR Њ 1.5V

t CDR

VIL

CE2 Љ 0.2V

-- 0.01 1 uA

0---- ns

(2)

T

RC

≥

Vcc

-- -- ns

t R

VIHVIH

Vcc

t R

VIL

R0201-BS62LV2000

3

Revision 2.3 April 2002

BSI

BS62LV2000

 AC TEST CONDITIONS

Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level

Vcc/0V 5ns

0.5Vcc

 AC TEST LOADS AND WAVEFORMS

3.3V

OUTPUT

INCLUDING JIG AND SCOPE

OUTPUT

Vcc

GND

1269

100PF

Ω

1404

FIGURE 1A

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

→

←

OUTPUT

Ω667

90%

FIGURE 2

3.3V

INCLUDING JIG AND SCOPE

→

←

1.73V

10%

5ns

Ω

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

E1LQV

t

E2HOV

t

GLQV

t

E1LQX

t

E2HOX

t

GLQX

t

E1HQZ

t

E2HQZ

t

GHQZ

t

AXOX

PARAMETER

NAME

t

RC

t

AA

t

ACS1

t

ACS2

t

OE

t

CLZ1

t

CLZ2

t

OLZ

t

CHZ1

t

CHZ2

t

OHZ

t

OH

DESCRIPTION

Read Cycle Time

Address Access Time

Chip Select Access Time (CE1)

Chip Select Access Time (CE2)

Output Enable to Output Valid

Chip Select to Output Low Z (CE1)

Chip Select to Output Low Z (CE2)

Output Enable to Output in Low Z

Chip Deselect to Output in High Z (CE1)

Chip Deselect to Output in High Z (CE2)

Output Disable to Output in High Z

Output Disable to Output Address Change

Ω

1269

5PF

1404

FIGURE 1B

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Ω

o

C to + 70oC, Vcc = 3.0V )

BS62LV2000-70

MIN. TYP. MAX.

70 -- -- 100 -- -- ns

-- -- 70 -- -- 100 ns

-- -- 35 -- -- 50 ns

10 -- -- 15 -- -- ns

0--350--40ns

0--300--35ns

10 -- -- 15 -- -- ns

MUST BE STEADY

MAY CHANGE FROM H TO L

MAY CHANGE FROM L TO H

,

DON T CAR ANY CHANG PERMITTED

DOES NOT APPLY

BS62LV2000-10

MIN. TYP. MAX.

MUST BE STEADY

WILL BE CHANGE FROM H TO L

WILL BE CHANGE FROM L TO H

E: CHANGE :

E STATE

UNKNOWN

CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE

UNIT

R0201-BS62LV2000

4

Revision 2.3 April 2002

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t AA

t OH

OUT

BS62LV2000

t RC

t OH

READ CYCLE2

CE1

CE2

D

OUT

READ CYCLE3

ADDRESS

OE

CE1

(1,3,4)

(1,4)

t CLZ

(5)

t ACS1

t ACS2

t CLZ1

(5)

t AA

t AC S1

t OLZ

t OE

t RC

(5)

t CHZ1, t CHZ2

t OH

(5)

t OHZ

(1,5)

t CHZ1

CE2

D

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = V

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = V

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.

R0201-BS62LV2000

IL .

OUT

t ACS2

(5)

(2,5)

t CHZ2

t CLZ2

IL and CE2= VIH.

±

5

Revision 2.3 April 2002

BSI

BS62LV2000

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

E2LAX

t

WLOZ

t

DVWH

t

WHDX

t

GHOZ

t

WHQX

PARAMETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR1

t

WR2

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

DESCRIPTION

Write Cycle Time

Chip Select to End of Write

Address Set up Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time (CE1 , WE)

Write Recovery Time (CE2)

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

o

C to + 70oC, Vcc = 3.0V )

BS62LV2000-70

MIN. TYP. MAX.

70 -- -- 100 -- -- ns

0 -- -- 0 -- -- ns

70 -- -- 100 -- -- ns

35 -- -- 50 -- -- ns

0 -- -- 0 -- -- ns

0--300--40 ns

30 -- -- 40 -- -- ns

0 -- -- 0 -- -- ns

0--300--40 ns

5----10---- ns

BS62LV2000-10

MIN. TYP. MAX.

UNIT

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

ADDRESS

OE

CE1

CE2

WE

(1)

(5)

t AS

(4,10)

t OHZ

D

OUT

t AW

t WC

t CW

t WP

(11)

(3)

t WR1

t WR2

(3)

(2)

t DH

t DW

D

IN

R0201-BS62LV2000

6

Revision 2.3 April 2002

BSI

BS62LV2000

WRITE CYCLE2

ADDRESS

CE1

CE2

WE

D

OUT

D

IN

(1,6)

t AS

(5)

t AW

(4,10)

t WHZ

t WC

t CW

t WP

(11)

t WR2

(3)

(2)

t DH

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going

inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. T

WR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write

cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the

outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low

transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7.

DOUT is the same phase of write data of this write cycle.

OUT is the read data of next address.

8. D

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input

signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

parameter is guaranteed but not 100% tested.

CW is measured from the later of CE1 going low or CE2 going high to the end of write.

11. T

IL ).

±

L = 5pF as shown in Figure 1B. The

R0201-BS62LV2000

7

Revision 2.3 April 2002

BSI

 ORDERING INFORMATION

BS62LV2000 X X ˀˀ Y Y

BS62LV2000

SPEED

70: 70ns 10: 100ns

GRADE

C: +0oC ~ +70oC

o

C ~ +85oC

I: -40

PACKAGE

T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) S: SOP

 PACKAGE DIMENSIONS

R0201-BS62LV2000

STSOP - 32

8

Revision 2.3 April 2002

BSI

 PACKAGE DIMENSIONS (continued)

BS62LV2000

TSOP - 32

SOP -32

WITH PLATING

c c1

BASE METAL

b

b1

SECTION A-A

R0201-BS62LV2000

9

Revision 2.3 April 2002

BSI

BS62LV2000

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

2.3 Modify some AC parameters April,11,2002

R0201-BS62LV2000

10

Revision 2.3 April 2002