Page 1
Very Low Power/Voltage CMOS SRAM
BSI
FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 17mA (@55ns) operating current
Vcc = 5.0V C-grade : 46mA (55ns) operating current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV1027SC SOP-32
BS62LV1027TC TSOP -32
BS62LV1027STC STSOP-32
BS62LV1027PC PDIP-32
BS62LV1027JC SOJ-32
BS62LV1027DC
BS62LV1027SI SOP-32
BS62LV1027TI TSOP -32
BS62LV1027STI STSOP-32
BS62LV1027PI PDIP-32
BS62LV1027JI SOJ-32
BS62LV1027DI
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS62LV1027
I- grade : 18mA (@55ns) operating current
C-grade : 14mA (@70ns) operating current
I- grade : 15mA (@70ns) operating current
0.1uA (Typ.) CMOS standby current
I- grade : 47mA (55ns) operating current
C-grade : 38mA (70ns) operating current
I- grade : 39mA (70ns) operating current
0.6uA (Typ.) CMOS standby current
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
•
1
A11
2
A9
3
A8
4
A13
5
WE
6
CE2
7
A15
8
VCC
9
NC
10
A16
11
A14
12
A12
13
A7
14
A6
15
A5
16
A4
128K X 8 bit
OPERATING
TEMPERATURE
+0O C to +70O C 2.4V ~ 5.5V 55/70
-40O C to +85O C2.4V ~ 5.5V
•
1
2
3
4
5
6
7
BS62LV1027SC
8
BS62LV1027SI
BS62LV1027PC
9
BS62LV1027PI
10
BS62LV1027JC
11
BS62LV1027JI
12
13
14
15
16
BS62LV1027TC
BS62LV1027STC
BS62LV1027TI
BS62LV1027STI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
Vcc
RANGE
OE
32
A10
31
CE1
30
DQ7
29
DQ6
28
DQ5
27
DQ4
26
DQ3
25
GND
24
DQ2
23
DQ1
22
DQ0
21
A0
20
A1
19
A2
18
A3
17
55ns : 3.0~5.5V
70ns : 2.7~5.5V
BS62LV1027
• Easy expansion with CE2, CE1, and OE options
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
DESCRIPTION
The BS62LV1027 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA at 3V/25oC and maximum access time of 55ns at 3V/85oC.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1027 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1027 is available in DICE form , JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP,8mm x13.4
mm STSOP and 8mmx20mm TSOP.
SPEED
(ns)
55/70
BLOCK DIAGRAM
A6
A7
A12
A14
A16
A15
A13
A8
A9
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE2
CE1
WE
OE
Vdd
Gnd
1
POWER DISSIPATION
STANDBY
(ICCSB1, Max)
Vcc=5.0V Vcc=3.0V
8.0uA
20uA
Address
Input
Buffer
1.3uA
2.5uA
20
8
8
Control
Decoder
Data
Input
Buffer
Data
Output
Buffer
Operating
Vcc=3V
70ns
14mA
15mA
Row
(ICC, Max)
Vcc=5V
1024
8
8
70ns
38mA
39mA
Address Input Buffer
A5
PKG TYPE
DICE
DICE
Memory Array
1024 x 1024
Column I/O
Write Driver
Sense Amp
Column Decoder
A4
A3 A2 A1 A0 A10
1024
128
14
Revision 2.1
Jan. 2004
Page 2
BSI
PIN DESCRIPTIONS
Name Function
BS62LV1027
A0-A16 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc
Gnd
Power Supply
Ground
TRUTH TABLE
MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT
Not selected
(Power Down)
Output Disabled H L H H High Z I
Read H L H L D
Write L L H X D
XHXX
XXLX
High Z I
OUT
IN
CCSB
, I
CCSB1
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL PARAMETER RATING UNITS
TERM
V
BIAS
T
STG
T
T
P
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS62LV1027
Terminal Voltage with
Respect to GND
Temperature Under Bias -40 to +85
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current 20 mA
-0.5 to
Vcc+0.5
OPERATING RANGE
RANGE
V
O
C
O
C
Commercial 0O C to +70O C2.4V ~ 5.5V
Industrial -40O C to +85O C2.4V ~ 5.5V
CAPACITANCE
SYMBOL PARAMETER CONDITIONS MAX. UNIT
C
C
1. This parameter is guaranteed and not 100% tested.
IN
DQ
Input
Capacitance
Input/Output
Capacitance
2
AMBIENT
TEMPERATURE
(1)
(TA = 25oC, f = 1.0 MHz)
VIN=0V 6 pF
I/O
V
=0V 8 pF
Vcc
Revision 2.1
Jan. 2004
Page 3
BSI
BS62LV1027
DC ELECTRICAL CHARACTERISTICS ( TA = -40
PAR AME TER
NAME
IL
V
IH
V
IL
I
Input Leakage Current Vcc = Max, V
ILO Output Leakage Current
VOL Output Low Voltage Vc c = Max, IOL = 2.0mA
VOH Output High Voltage Vcc = Min, IOH = -1.0mA
(5)
CC
I
CCSB
I
Standby Current-TTL
(4)
CCSB1
I
Standby Current-CMOS
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
4. IccSB1_Max. is 1.3uA/8.0uA at Vcc=3.0V/5.0V and TA=70oC.
RC
PAR AME TER TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Vcc = Max, CE1= V
IH
OE = V
Operating Power Supply
Current
.
CE1 = V
DQ
I
= 0mA, F = Fmax
CE1 = V
DQ
= 0mA
I
CE1≧Vcc-0.2V or CE2≦0.2V,
V
Vcc-0.2V or V
≧
IN
o
C to + 85oC )
(1)
MAX.
70ns
IL,
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
or
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
IN
= 0V to Vcc -- -- 1 uA
IH
I/O
, V
IL
, or CE2 = VIH,
IH
, or CE2 = VIL,
, CE2= V
= 0V to Vcc
(3)
0.2V
≦
IN
-0.5 -- 0.8 V
2.0
2.2
-- Vcc+0.3 V
-- -- 1 uA
-- -- 0.4 V
2.4 -- -- V
-- -- 15
-- -- 39
-- -- 0.5
-- -- 1.0
-- 0.1 2.5
-- 0.6 20
5. Icc_Max. is 18mA(@3V)/ 47mA(@5V) under 55ns operation.
DATA RETENTION CHARACTERISTICS ( TA = -40
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.
V
DR
I
CCDR
t
CDR
t
R
1. Vcc = 1.5V, TA= + 25OC
2. t
= Read Cycle Time
RC
3. IccDR_MAX. is 0.2uA at TA=70OC.
LOW V
Vcc for Data Retention
(3)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
CC
Vcc
CE1
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
IN
≧ Vcc - 0.2V or VIN ≦ 0.2V
V
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
IN
V
≧ Vcc - 0.2V or VIN ≦ 0.2V
See Retention Waveform
Vcc
t CDR
o
C to + 85oC )
Data Retention Mode
≥
VDR 1.5V
≥
CE1 Vcc - 0.2V
(1)
MAX. UNITS
1.5 -- -- V
-- 0.05 0.3 uA
0 -- -- ns
(2)
T
RC
Vcc
-- -- ns
t R
VIHVIH
UNITS
mA
mA
uA
LOW V
DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
CC
Vcc
CE2
R0201-BS62LV1027
Data Retention Mode
Vcc
VDR ≧ 1.5V
t CDR
VIL
CE2 ≦ 0.2V
3
Vcc
t R
VIL
Revision 2.1
Jan. 2004
Page 4
BSI
BS62LV1027
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
Vcc / 0V
1V/ns
0.5Vcc
CL = 30pF+1TTL
C
= 100pF+1TTL
L
AC ELECTRICAL CHARACTERISTICS ( TA = -40
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
E2HOV
t
GLQV
t
E1LQX
t
E2HOX
t
GLQX
t
E1HQZ
t
E2HQZ
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
DESCRIPTION UNIT
Read Cycle Time
Address Access Time
Chip Select Access Time (CE1)
Chip Select Access Time (CE2)
Output Enable to Output Valid
Chip Select to Output Low Z (CE1)
Chip Select to Output Low Z (CE2)
Output Enable to Output in Low Z
Chip Deselect to Output in High Z (CE1)
Chip Deselect to Output in High Z (CE2)
Output Disable to Output in High Z
Data Hold from Address Change
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
o
C to + 85oC )
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
MIN. TYP. MAX.
55 -- -- 70 -- -- ns
-- -- 55 -- -- 70 ns
-- -- 55 -- -- 70 ns
-- -- 55 -- -- 70 ns
-- -- 30 -- -- 40 ns
10 -- -- 10 -- -- ns
10 -- -- 10 -- -- ns
10 -- -- 10 -- -- ns
-- -- 35 -- -- 40 ns
-- -- 35 -- -- 40 ns
-- -- 30 -- -- 35 ns
10 -- -- 10 -- -- ns
R0201-BS62LV1027
4
Revision 2.1
Jan. 2004
Page 5
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
(1,2,4)
t AA
t OH
OUT
BS62LV1027
t RC
t OH
READ CYCLE2
CE1
CE2
D
OUT
READ CYCLE3
ADDRESS
OE
CE1
(1,3,4)
(1,4)
t CLZ
(5)
t ACS1
t ACS2
t CLZ1
(5)
t AA
t ACS1
t OLZ
t OE
t RC
(5)
t CHZ1, t CHZ2
t OH
(5)
t OHZ
(1,5)
t CHZ1
CE2
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
R0201-BS62LV1027
t CLZ2
t ACS2
(5)
5
(2,5)
t CHZ2
Revision 2.1
Jan. 2004
Page 6
BSI
BS62LV1027
AC ELECTRICAL CHARACTERISTICS ( TA = -40
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
E2LAX
t
WLOZ
t
DVWH
t
WHDX
t
GHOZ
t
WHQX
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1
t
WR2
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION UNIT
Write Cycle Time
Chip Select to End of Write
Address Set up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time (CE1 , WE)
Write Recovery Time (CE2)
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
o
C to + 85oC )
t WC
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
MIN. TYP. MAX.
55 -- -- 70 -- -- ns
55 -- -- 70 -- -- ns
0 -- -- 0 -- -- ns
55 -- -- 70 -- -- ns
35 -- -- 50 -- -- ns
0 -- -- 0 -- -- ns
0 -- -- 0 -- -- ns
-- -- 25 -- -- 30 ns
25 -- -- 30 -- -- ns
0 -- -- 0 -- -- ns
-- -- 25 -- -- 30 ns
5 -- -- 5 -- -- ns
ADDRESS
OE
CE1
CE2
WE
D
D
R0201-BS62LV1027
OUT
IN
t AS
(4,10)
t OHZ
(3)
t WR1
(11)
(5)
(5)
t AW
t CW
t CW
t WP
(11)
t WR2
(3)
(2)
t DH
t DW
6
Revision 2.1
Jan. 2004
Page 7
BSI
BS62LV1027
WRITE CYCLE2
ADDRESS
CE1
CE2
WE
D
OUT
D
IN
(1,6)
t AS
(5)
(5)
(4,10)
t WHZ
t AW
t WC
t CW
t CW
t WP
(11)
(11)
t WR2
(3)
(2)
t OW
(7) (8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
WR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
3. T
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7.
DOUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BS62LV1027
7
Revision 2.1
Jan. 2004
Page 8
BSI
BS62LV1027
ORDERING INFORMATION
BS62LV1027 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
J: SOJ
S: SOP
P: PDIP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
SOP -32
WITH PLATING
c c1
BASE METAL
b
b1
SECTION A-A
R0201-BS62LV1027
8
Revision 2.1
Jan. 2004
Page 9
BSI
PACKAGE DIMENSIONS (continued)
BS62LV1027
STSOP - 32
TSOP - 32
R0201-BS62LV1027
9
Revision 2.1
Jan. 2004
Page 10
BSI
PACKAGE DIMENSIONS (continued)
PDIP - 32
BS62LV1027
R0201-BS62LV1027
SOJ - 32
10
Revision 2.1
Jan. 2004
Loading...