Datasheet BS616UV8021BC, BS616UV8021FI, BS616UV8021FC, BS616UV8021DI, BS616UV8021DC Datasheet (BSI)

BSI

Ultra Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable

BS616UV8021

 FEATURES

• Ultra low operation voltage : 1.8 ~ 2.3V

• Ultra low power consumption :
Vcc = 2.0V C-grade: 20mA (Max.) operating current

I-grade : 25mA (Max.) operating current

0.6uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc=2.0V

-10 100ns (Max.) at Vcc=2.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE1, CE2 and OE options

 DESCRIPTION

The BS616UV8021 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 1.8V to 2.3V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/100ns in 2.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616UV8021 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV8021 is available in DICE form and 48-pin BGA type.

• I/O Configuration x8/x16 selectable by CIO, LB and UB pin

 PRODUCT FAMILY

SPEED

PRODUCT

FAMILY

BS616UV8021DC DICE
BS616UV8021BC BGA-48-0810

OPERATING

TEMPERATURE

O

C to +70OC 1.8V ~ 2.3V 70 / 100 15uA 20mA

+0

Vcc RANGE

(ns)

Vcc=2.0V Vcc=2.0V Vcc=2.0V

BS616UV8021FC
BS616UV8021DI DICE
BS616UV8021BI BGA-48-0810

O

C to +85OC 1.8V ~ 2.3V 70 / 100 20uA 25mA

-40

BS616UV8021FI

POWER DISSIPATION

STANDBY

CCSB1

(I

, Max)

Operating

(ICC, Max)

PKG TYPE

BGA-48-0912

BGA-48-0912

 PIN CONFIGURATIONS

123456

A

LB OE A0 A1 A2

B

D8 UB A3 A4 CE1

D9 D10 A5 A 6 D1 D2

C

D11 A17

VSS

D

E

VCC

F

D14

D15

G

A18

H

48-Ball CSP top View

D12 A16 D4

CIO.

A8 A9

A7 D3

Vss

A15D13 A14

A12 A13

A10 A11

CE2

D0

VCC

VSS

D5 D6

WE D7

SAE.

 BLOCK DIAGRAM

A15
A14
A13

A12

Address
A11
A10

A9

A8
A17
A7
A6

D15

CE1

CE2

CIO

Vdd

Vss

WE

UB

D0

.

.

.

.

.

.

.

.

OE

LB

Input

Buffer

16(8)

16(8)

Control

22

Data
Input
Buffer

Data

Output

Buffer

Row

Decoder

16(8)

16(8)

2048

A16

Memory Array

2048 x 4096

Write Driver

Sense Amp

Column Decoder

Address Input Buffer

A0

A1 A2 A3

Column I/O

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS616UV8021

1

4096

256(512)

16(18)

A4

A5

A18

(SAE)

Revision 2.2
April 2001

Preliminary

Preliminary

BSI

 PIN DESCRIPTIONS

Name Function

A0-A18 Address Input

SAE Address Input

CIO x8/x16 select input

CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input

WE Write Enable Input

OE Output Enable Input

LB and UB Data Byte Control Input

D0 - D15 Data Input/Output Ports

BS616UV8021

These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.

This address input incorporate with the above 19 address inputs select one of the

1,048,576 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.

This input selects the organization of the SRAM. 524,288 x 16-bit words configuration
is selected if CIO is HIGH. 1,048,576 x 8-bit bytes configuration is selected if CIO is
LOW.

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when

data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

Lower byte and upper byte data input/output control pins. The chip is deselected when

both LB and UB pins are HIGH.

These 16 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Gnd

R0201-BS616UV8021

Power Supply

Ground

2

Revision 2.2
April 2001

BSI

 TRUTH TABLE

MODE CE1 CE2 OE WE CIO LB UB SAE D0~7 D8~15 VCC Current

BS616UV8021

Fully Standby

XL

XX X

XX

XHigh

Output Disable L H H H X X X X High

HX XX

Read from SRAM

LHLH H

( WORD mode )

LH

HL High-Z Dout

X

LL

LH Din X

Write to SRAM

( WORD mode )

LHXL H

HL X Din

X

LL

Read from SRAM

LHLH L

X X A-1 Dout High-Z

( BYTE Mode )

Write to SRAM

LHXL L

XXA-1 Din X

( BYTE Mode )

-ZHigh-Z

-

Z

High

-Z

Dout High-Z

Dout Dout

Din Din

I

CCSB

, I

I

I

I

I

I

CCSB1

CC

CC

CC

CC

CC

 ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PARAM E TER RATING UNITS

V

T

T

P

I

TERM

BIAS

STG

T

OUT

Terminal Voltage with
Resp ect to G ND

Temperature Under Bias -40 to +125

Storage Temperature -60 to +150

Power Dissipation 1.0 W

DC Output Current 20 mA

-0.5 to

Vcc+0.5

O

O

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

R0201-BS616UV8021

 OPERATING RANGE

V

C

C

RANGE

Commercial 0OC to +70OC1.8V ~ 2.3V

Industrial -40OC to +85OC1.8V ~ 2.3V

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

Input

IN

C

C

DQ

Capacitance
Input/Output
Capacitance

1. This parameter is guaranteed and not tested.

3

AMBIENT

TEMPERATURE

(1)

(TA = 25oC, f = 1.0 MHz)

VIN=0V 6 pF

I/O

V

=0V 8 pF

Vcc

Revision 2.2
April 2001

BSI

BS616UV8021

IH I/O

0.2V;V

o

C to + 70oC)

= 0V to Vcc

OL

OH

Њ

Vcc-0.2V,

Њ

IN

IH

, or CE2 = ViL, or

Vcc

(3)

IH

or CE2 = VIL,

Vcc - 0.2V or

Vcc=2.0V

Vcc=2.0V

Vcc=2.0V

Vcc=2.0V

Vcc=2.0V

Vcc=2.0V

Vcc=2.0V

(1)

MAX. UNITS

-0.5 -- 0.6 V

1.4 --

Vcc+0.2

-- -- 1 uA

-- -- 1 uA

-- -- 0.4 V

1.6 -- -- V

-- -- 20 mA

-- -- 0.6 mA

-- 0.6 15 uA

 DC ELECTRICAL CHARACTERISTICS ( TA = 0

PARAMETER

NAME

IL

V

IH

V

IL

I

OL

I

OL

V

OH

V

CC

I

CCSB

I

CCSB1

I

PARAMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage
Guaranteed Input High

(2)

Voltage

Input Leakage Current Vcc = Max, VIN

Output Leakage Current

Output Low Voltage = 1mAVcc= max, I

Output High Voltage = -0.5mAVcc= Min, I

Operating Power Supply
Current

Standby Current-TTL

Standby Current

-CMOS

Vcc = Max, CE1 = V
OE = V , V = 0V to

Vcc= max, CE1=VILand CE2 = V IH,

DQ

= 0mA, F = Fmax

I

Vcc= max, CE1 = V

DQ

I= 0mA

Vcc= max,CE1
or CE2

Љ

IN

Љ

V

0.2V

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/ t

.

RC

V

R0201-BS616UV8021

4

Revision 2.2
April 2001

BSI

BS616UV8021

 DATA RETENTION CHARACTERISTICS ( TA = 0

o

C to +70oC )

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.

V

I

CCDR

t

CDR

t

DR

R

Vcc for Data Retention

Data Retention Current

Chip Deselect to Data
Retention Time

Operation Recovery Time

1. Vcc = 1.5V, TA= + 25OC
= Read Cycle Time

2. t

RC

 LOW V

DATA RETENTION WAVEFORM (1) ( CE1 Controlled )

CC

Vcc

CE1 ЊVcc - 0.2V or CE2 Љ0.2V ;
V

Њ

IN

Vcc - 0.2V or V

0.2V

Љ

IN

CE1 ЊVcc - 0.2V or CE2 Љ0.2V
V

Vcc - 0.2V or V

Њ

IN

0.2V

Љ

IN

See Retention Waveform

Data Retention Mode

Vcc

VDR Њ 1.5V

t CDR

CE1 Њ Vcc - 0.2V

1.5 -- --

T

RC

Vcc

t R

CE1

(1)

MAX. UNITS

-- 0.4 10 uA

0----

(2)

-- --

VIHVIH

ns

ns

V

 LOW V

DATA RETENTION WAVEFORM (2) ( CE2 Controlled )

CC

Vcc

CE2

R0201-BS616UV8021

Data Retention Mode

Vcc

VDR Њ 1.5V

t CDR

VIL

CE2 Љ 0.2V

5

Vcc

t R

VIL

Revision 2.2
April 2001

BSI

BS616UV8021

 AC TEST CONDITIONS

Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level

Vcc/0V
5ns

0.5Vcc

 AC TEST LOADS AND WAVEFORMS

2V

OUTPUT

INCLUDING
JIG AND
SCOPE

Vcc

GND

1333

100PF

FIGURE 1A

OUTPUT

10%

Ω

2000

THEVENIN EQUIVALENT

ALL INPUT PULSES

→

←

OUTPUT

Ω800

90%

90%

FIGURE 2

2V

INCLUDING
JIG AND
SCOPE

→

10%

← 5ns

1.2V

1333

5PF

2000

FIGURE 1B

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

MAY CHANGE
FROM L TO H

,

DON T CARE:
ANY CHANGE

Ω

PERMITTED

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

WILL BE
CHANGE
FROM L TO H

CHANGE :
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

E1LQV

t

E2LQV

t

BA

t

GLQV

t

ELQX

t

BE

t

GLQX

t

EHQZ

t

BDO

t

GHQZ

t

AXQX

PARAMETER

NAME

t

RC

t

AA

t

ACS1

t

ACS2

t

BA

t

OE

t

CLZ

t

BE

t

OLZ

t

CHZ

t

BDO

t

OHZ

t

OH

Read Cycle Time

Address Access Time

Chip Select Access Time

Chip Select Access Time
Data Byte Control Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Data Byte Control to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Data Byte Control to Output High Z

Output Disable to Output in High Z

Output Disable to Output Address Change

DESCRIPTION

o

C to +70oC, Vcc=2.0V )

BS616UV8021-70

MIN. TYP. MAX.

70

(CE1)
(CE2)

(LB,UB)

(CE2,CE1)

(LB,UB)

10

10

10

(CE2,CE1)

(LB,UB)

0

0

0

10

BS616UV8021-10

MIN. TYP. MAX.

100

70

70

70

50

50

15

15

15

35

30

30

0

0

0

15

100

100

100

60

60

40

35

35

UNIT

ns
ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

R0201-BS616UV8021

6

Revision 2.2
April 2001

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t OH

OUT

t AA

BS616UV8021

t RC

t OH

READ CYCLE2

CE2

CE1

D

OUT

READ CYCLE3

ADDRESS

OE

CE2

CE1

(1,3,4)

(1,4)

t CLZ

(5)

t ACS2

t ACS1

t CLZ

(5)

t AA

t OLZ

t ACS1

t ACS2

t OE

t RC

t OHZ

t CHZ

(1,5)

t CHZ

t OH

(5)

(5)

LB,UB

t BE

t BA

D

OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = V

3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.

4. OE = V

5. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.

R0201-BS616UV8021

IL .

±

The parameter is guaranteed but not 100% tested.

IL and CE2 = VIH.

7

t BDO

Revision 2.2
April 2001

BSI

BS616UV8021

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

BW

t

WLQZ

t

DVWH

t

WHDX

t

GHQZ

t

WHQX

PARAMETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR

t

BW

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

Write Cycle Time

Chip Select to End of Write

Address Set up Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time

Data Byte Control to End of Write

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

DESCRIPTION

(CE2, CE1, WE)

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

o

C to +70oC, Vcc=2.0V)

BS616UV8021-70

MIN. TYP. MAX.

70

70

0

70

50

0

(LB,UB)

60

0

30

0

0

5

t WC

BS616UV8021-10

MIN. TYP. MAX.

100

100

0

100

70

0

80

30

30

0

40

0

0

10

40

40

UNIT

ns
ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ADDRESS

OE

CE2

CE1

LB,UB

WE

D

OUT

t AS

(4,10)

t OHZ

(3)

t WR

(5)

(11)

(5)

t CW

t BW

(5)

t AW

t WP

(2)

(3)

t DH

t DW

D

IN

R0201-BS616UV8021

8

Revision 2.2
April 2001

BSI

BS616UV8021

WRITE CYCLE2

ADDRESS

CE2

CE1

LB,UB

WE

D

OUT

D

IN

(1,6)

t AS

(5)

(5)

(4,10)

t WHZ

t AW

t WC

t CW

t BW

t WP

(11)

t WR

(3)

(2)

t DH

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.

3. T

WR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.

5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT is the same phase of write data of this write cycle.

8. D

OUT is the read data of next address.

9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

11. T

CW is measured from the later of CE2 going high or CE1 going low to the end of write.

R0201-BS616UV8021

IL ).

±

9

Revision 2.2
April 2001

BSI

 ORDERING INFORMATION

BS616UV8021 X X -- Y Y

BS616UV8021

SPEED

70: 70ns
10: 100ns

GRADE

o

C: +0

C ~ +70oC

o

I: -40

C ~ +85oC

PACKAGE

B :BGA - 48 PIN(8x10mm)
F :BGA - 48 PIN(9x12mm)
D :DICE

 PACKAGE DIMENSIONS

1.4 Max.

e

VIEW A

SIDE VIEW

D0.1

D1

0.05

0.25 

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

N ED

48 10.0 8.0

0.1

E1

E

E1D1 e

3.755.25 0.75

SOLDER BALL 0.350.05

48 mini-BGA (8 x 10mm)

R0201-BS616UV8021

10

Revision 2.2
April 2001

BSI

 PACKAGE DIMENSIONS (continued)

1.4 Max.

SIDE VIEW

0.05



0.25

BS616UV8021

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

D0.1

3.375

e

VIEW A

D1

48 mini-BGA (9 x 12mm)

E1

2.625

N ED

48 12.0 9.0



E0.1

E1D1 e

3.755.25 0.75

SOLDER BALL 0.350.05

R0201-BS616UV8021

11

Revision 2.2
April 2001

BSI

BS616UV8021

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

R0201-BS616UV8021

12

Revision 2.2
April 2001