Page 1
BSI
Ultra Low Power/Voltage CMOS SRAM
1M X 16 bit
BS616UV1610
FEATURES
DESCRIPTION
• Ultra low operation voltage : 1.8 ~ 2.3V
• Ultra low power consumption :
Vcc = 2.0V C-grade: 25mA (Max.) operating current
I-grade : 30mA (Max.) operating current
1.2uA (Typ.) CMOS standby current
The BS616UV1610 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 1,048,576 words by 16 bits and
operates from a wide range of 1.8V to 2.3V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc=2V
-10 100ns (Max.) at Vcc=2V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
of 1.2uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by an active LOW chip enable(CE1),
active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616UV1610 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV1610 is available in 48-pin BGA package.
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
SPEED
PRODUCT FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
(ns)
Vcc=2V Vcc=2V Vcc=2V
BS616UV1610BC BGA
BS616UV1610FC
BS616UV1610BI BGA
BS616UV1610FI
O
C to +70
+0
40OC to +85OC
-
O
1.8 ~ 2.3V
C
1.8 ~ 2.3V 70 / 100
70 / 100
POWER DISSIPATION
STANDBY
(I
CCSB1
, Max)
30uA
40uA 30mA
Operating
(ICC, Max)
25mA
PKG TYPE
-
48
BGA
-
48
-
48
BGA
-
48
0810
-
0912
-
0810
-
0912
-
PIN CONFIGURATIONS
123456
LB OE A0 A1 A2
A
A3 A4
B
C
D
E
F
G
H
UB
D9 D10 A5 A6 D1 D2
D11 A17 A7
VSS
D12 A16 D4
VCC
D14 D13 A14
D15 NC.A1
A18
48-Ball CSP top View
VSS
A8 A9
A15
2A13
A10 A11 A19.
CE2
CE1
D3
VCC
VSS
D5 D6
WE
D0D8
D7
BLOCK DIAGRAM
A4
A3
A2
A1
Address
D0
D15
A17
A16
A15
A14
A13
A12
Vcc
Gnd
A0
CE2
CE1
WE
UB
Input
Buffer
16
.
.
.
.
.
.
.
OE
LB
16
.
Control
22
Data
Input
Buffer
Data
Output
Buffer
Row
Decoder
2048
16
16
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616UV1610
1
Column Decoder
Address Input Buffer
A9
A11
A10
Memory Array
2048 x 8192
Column I/O
Write Driver
Sense Amp
512
A8
A7
8192
18
A18
A6
A5
Revision 2.2
April 2001
A19
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BSI
PIN DESCRIPTIONS
Name Function
BS616UV1610
A0-A19 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Vcc
Gnd
These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM.
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE CE1 CE2 WE OE LB UB D0~D7 D8~D15 Vcc CURRENT
Not selected
(Power Down)
Output Disabled
Read L H H L
Write L H L X
H
X
L
ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAM ETER RATING UNITS
TERM
V
BIAS
T
STG
T
T
P
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Terminal Voltage with
Respect to GND
Temperature Under Bias -40 to +125
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current 20 mA
X X X X X High Z High Z I
L X X X X High Z High Z I
H H H X X High Z High Z I
L L Dout Dout I
HL High Z Dout I
L H Dout High Z I
LL Din Din I
HL X Din I
LH Din X I
(1)
-0.5 to
Vcc+0.5
V
O
C
O
C
, I
CCSB
CCSB1
, I
CCSB
CCSB1
CC
CC
CC
CC
CC
CC
CC
OPERATING RANGE
RANGE
Commercial 0OC to +70OC1.8V ~ 2.3V
Industrial -40OC to +85OC 1.8V ~ 2.3V
CAPACITANCE
SYMBOL PARAMETER CONDITIONS MAX. UNIT
IN
C
DQ
C
1. This parameter is guaranteed and not tested.
AMBIENT
TEMPERATURE
(1)
(TA = 25oC, f = 1.0 MHz)
Input
Capacitance
Input/Output
Capacitance
Vcc
VIN=0V 10 pF
I/O
V
=0V 12 pF
R0201-BS616UV1610
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Revision 2.2
April 2001
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BSI
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70
PARAMETER
NAME
IL
V
IH
V
IL
I
OL
I
OL
V
PARAMETER TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current = 0V to VccVcc = Max, V
Output Leakage Current
Vcc = Max, CE1 = V
OE = V , V = 0V to
Output Low Voltage = 1mAVcc = Max, I
IN
IH I/O
OL
o
C )
IH
, or CE2 = ViL, or
Vcc
Vcc=2V
Vcc=2V
Vcc=2V
BS616UV1610
(1)
MAX.
-0.5 -- 0.6 V
1.4 --
Vcc+0.2
-- -- 1 uA
-- -- 1 uA
-- -- 0.4 V
UNITS
V
V
CC
I
CCSB
I
CCSB1
I
OH
Output High Voltage = -0.5mAVcc = Min, I
Operating Power Supply
Current
Standby Current-TTL
Vcc= max, CE1 = V
IH
V
, IDQ= 0mA, F =
Vcc= max, CE1 = V
IL
, IDQ= 0mA
V
Vcc= max,CE1
0.2V, V
Standby Current-
CMOS
CE2
or V
Љ
IN
0.2V
Љ
OH
IL
and
Fmax
IH
or CE2 =
Vcc-0.2V, or
Њ
IN
Vcc - 0.2V
Њ
CE2 =
(3)
Vcc=2V
Vcc=2V
Vcc=2V
Vcc=2V
1.6 -- -- V
-- -- 25 mA
-- -- 0.8 mA
-- 1.2 30 uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.
V
DR
I
CCDR
t
CDR
t
R
.
RC
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
o
C )
CE1 ЊVcc - 0.2V or CE2Љ0.2V
IN
V
Њ
Vcc - 0.2V or V
IN
0.2V
Љ
CE1 ЊVcc - 0.2V or CE2Љ0.2V
IN
V
Њ
Vcc - 0.2V or V
IN
0.2V
Љ
See Retention Waveform
(1)
MAX. UNITS
1.5 -- -- V
-- 0.8 15 uA
0--- n-s
(2)
T
RC
-- -- ns
1. Vcc = 1.5V, TA= + 25OC
= Read Cycle Time
2. t
RC
LOW VCCDATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
≥
Vcc
Vcc
VDR 1.5V
t CDR
≥
CE1 Vcc - 0.2V
CE1
LOW VCCDATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
Vcc
CE2
R0201-BS616UV1610
Vcc
t CDR
VIL
VDR Њ 1.5V
CE2 Љ 0.2V
3
Vcc
t R
VIHVIH
Vcc
t R
VIL
Revision 2.2
April 2001
Page 4
BSI
BS616UV1610
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
AC TEST LOADS AND WAVEFORMS
Ω
Vcc
GND
1333
100PF
2000
FIGURE 1A
OUTPUT
10%
→
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
Vcc/0V
5ns
0.5Vcc
2V
OUTPUT
90%
Ω800
→
INCLUDING
JIG AND
SCOPE
Ω
THEVENIN EQUIVALENT
ALL INPUT PULSES
90%
←
FIGURE 2
10%
← 5ns
1.2V
Ω
1333
5PF
2000
FIGURE 1B
Ω
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Output Disable to Address Change
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
o
C, Vcc=2V)
DON T CAR
ANY CHANG
PERMITTED
DOES NOT
APPLY
BS616UV1610-70
MIN. TYP. MAX.
E: CHANGE :
E STATE
BS616UV1610-100
MIN. TYP. MAX.
70 -- -- 100 -- -- ns
-- -- 70 -- -- 100 ns
(CE1) -- -- 70 -- -- 100 ns
(CE2) -- -- 70 -- -- 100 ns
(LB,UB)-- --50-- --60 ns
-- -- 50 -- -- 60 ns
(CE2,CE1) 10 -- -- 15 -- -- ns
(LB,UB) 10 -- -- 15 -- -- ns
10 -- -- 15 -- -- ns
(CE2,CE1) 0 -- 35 0 -- 40 ns
(LB,UB) 0 -- 30 0 -- 35 ns
0--300--35 ns
10 -- -- 15 -- -- ns
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
UNIT
R0201-BS616UV1610
4
Revision 2.2
April 2001
Page 5
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
(1,2,4)
t AA
t OH
OUT
BS616UV1610
t RC
t OH
READ CYCLE2
CE2
CE1
D
OUT
READ CYCLE3
ADDRESS
OE
CE2
CE1
(1,4)
(1,3,4)
t CLZ
(5)
t CLZ
t ACS2
t ACS1
t ACS1
(5)
t AA
t ACS2
t OLZ
t OE
t RC
t OHZ
t CHZ
t OH
(1,5)
(5)
t CHZ
(5)
LB,UB
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
3. Address valid prior to or coincident with CE transition low.
4. OE = V
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
R0201-BS616UV1610
IL .
The parameter is guaranteed but not 100% tested.
t BE
t BDO
t BA
IL and CE2 = VIH.
±
5
Revision 2.2
April 2001
Page 6
BSI
BS616UV1610
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
VWL
A
t
AVWH
t
WLWH
t
WHAX
t
BW
t
WLQZ
t
DVWH
t
WHDX
t
GHQZ
t
WHOX
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1
t
BW
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write recovery Time
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
(CE2,CE1,WE) 0 -- -- 0 -- -- ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
o
C, Vcc=2V)
BS616UV1610-70
MIN. TYP. MAX.
BS616UV1610-10
MIN. TYP. MAX.
UNIT
70 -- -- 100 -- -- ns
70 -- -- 100 -- -- ns
0 -- -- 0 -- -- ns
70 -- -- 100 -- -- ns
50 -- -- 70 -- -- ns
(LB,U ) 6B 0 -- -- 80 -- -- ns
0 -- 30 0 -- 40 ns
30 -- -- 40 -- -- ns
0 -- -- 0 -- -- ns
0 -- 30 0 -- 40 ns
5----10---- ns
t WC
ADDRESS
OE
CE2
CE1
LB,UB
WE
D
OUT
t AS
(4,10)
t OHZ
(3)
t WR
(5)
(11)
(5)
t CW
t BW
(5)
t AW
t WP
(2)
(3)
t DH
t DW
D
IN
R0201-BS616UV1610
6
Revision 2.2
April 2001
Page 7
BSI
BS616UV1610
WRITE CYCLE2
ADDRESS
CE2
CE1
LB,UB
WE
D
OUT
(1,6)
t AS
(5)
(5)
t AW
(4,10)
t WHZ
t WC
t CW
t BW
t WP
(11)
t WR
(3)
(2)
t DH
(7) (8)
t DW
t DH
(8,9)
D
IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. T
WR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
OUT is the same phase of write data of this write cycle.
7. D
OUT is the read data of next address.
8. D
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
The parameter is guaranteed but not 100% tested.
11. T
CW is measured from the later of CE2 going high or CE1 going low to the end of write.
IL ).
±
L = 5pF as shown in Figure 1B.
R0201-BS616UV1610
7
Revision 2.2
April 2001
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BSI
ORDERING INFORMATION
BS616UV1610 X X -- Y Y
BS616UV1610
SPEED
70: 70ns
10: 100ns
GRADE
o
C: +0
C ~ +70oC
o
I: -40
C ~ +85oC
PACKAGE
B :BGA - 48 PIN(8x10mm)
F :BGA - 48 PIN(9x12mm)
PACKAGE DIMENSIONS
1.4 Max.
e
VIEW A
SIDE VIEW
D0.1
D1
0.05
0.25
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
N ED
48 10.0 8.0
E1
E0.1
E1D1 e
3.755.25 0.75
SOLDER BALL 0.350.05
48 mini-BGA (8 x 10mm)
R0201-BS616UV1610
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Revision 2.2
April 2001
Page 9
BSI
PACKAGE DIMENSIONS (continued)
1.4 Max.
SIDE VIEW
0.05
0.25
BS616UV1610
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
D0.1
3.375
e
VIEW A
D1
48 mini-BGA (9 x 12mm)
E1
2.625
N ED
48 12.0 9.0
E0.1
E1D1 e
3.755.25 0.75
SOLDER BALL 0.350.05
R0201-BS616UV1610
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Revision 2.2
April 2001
Page 10
BSI
BS616UV1610
REVISION HISTORY
Revision Description Date Note
2.2 2001 Data Sheet release Apr. 15, 2001
R0201-BS616UV1610
10
Revision 2.2
April 2001
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