Datasheet BS616UV1010EI, BS616UV1010EC, BS616UV1010CI, BS616UV1010AI, BS616UV1010AC Datasheet (BSI)
Page 1
Revision 2.2
April 2001
1
R0201-BS616UV1010
POWER DISSIPATION
SPEED
(ns)
STANDBY
(I
CCSB1
, Max)
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=3.0V Vcc=3.0V Vcc=2.0V Vcc=3.0V Vcc=2.0V
PKG TYPE
BS616UV1010EC TSOP2-44
BS616UV1010AC
+0
O
C to +70OC 1.8V ~ 3.6V 150 0.5uA 0.3uA 15mA 10mA
BGA-48-0608
BS616UV1010EI TSOP2-44
BS616UV1010AI
-40
O
C to +85OC 1.8V ~ 3.6V 150 1uA 20mA1.5uA 15mA
BGA-48-0608
Ultra Low Power/Voltage CMOS SRAM
64K X 16 bit
• Ultra low operation voltage : 1.8 ~ 3.6V
• Ultra low power consumption :
Vcc = 2.0V C-grade : 10mA (Max.) operating current
I- grade : 15mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade : 15mA (Max.) operating current
I- grade : 20mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
• High speed access time :
-15 150ns (Max.) at Vcc = 3.0V
• Input levels are CMOS-compatible
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616UV1010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.01uA and maximum access time of 150ns in 2V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616UV1010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV1010 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin mini-BGA.
DESCRIPTION
FEATURES
Row
Decoder
Memory Array
512 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A3 A2 A1
Data
Input
Buffer
Control
Gnd
Vcc
OE
DQ0
A7
A15
A13
16
16
16
16
WE
CE
DQ15
A5
A6
14
128
2048
BLOCK DIAGRAM
512
18
A14
A12
A9
A4
A0
A11
A8
Address
Input
Buffer
A10
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
BS616UV1010
G
H
F
E
D
C
B
A
12345
A9A8NC
IO15
IO14NCIO13
A12
A14
NCA11A10
A13
A15WEIO5
IO7
IO6
VCC
VSS
IO9
IO12
IO11
IO10
NC
NC
A5
NC
A7
A6
IO4
IO3
IO1
VSS
VCC
IO2
IO8LBUBOEA3A0A4A1CEA2IO0
NC
6
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ7
DQ6
WE
A15
A14
A13
A12
NC
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
1
2
3
4
5
18
20
22
43
41
39
28
26
24
23
6
7
8
9
10
11
12
13
14
16
37
36
35
34
33
32
31
30
BS616UV1010EC
BS616UV1010EI
15
17
19
21
44
42
40
38
29
27
25
BSI
Page 2
Revision 2.2
April 2001
2
R0201-BS616UV1010
Name Function
A0-A15 Address Input
These 16 address input select one of the 65,536 x 16-bit words in the RAM.
CE Chip Enable Input
CE is active LOW. Chip enables must be active to read from or write to the device. if
chip enable is not active, the device is deselected and is in a standby power mode.
The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
These 16 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc
Power Supply
Gnd
Ground
TRUTH TABLE
PIN DESCRIPTIONS
BSI
BS616UV1010
MODE CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT
Not selected
(Power Down)
H X X X X High Z High Z I
CCSB
, I
CCSB1
Output Disabled L H H X X High Z High Z I
CC
L L Dout Dout I
CC
H L High Z Dout I
CC
Read L H L
L H Dout High Z I
CC
L L Din Din I
CC
H L X Din I
CC
Write L L X
L H Din X I
CC
Page 3
Revision 2.2
April 2001
3
R0201-BS616UV1010
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.
(1)
MAX. UNITS
V
DR
Vcc for Data Retention
CEЊVcc - 0.2V
V
IN
Њ
Vcc - 0.2V or V
IN
Љ
0.2V
1.5 -- -- V
I
CCDR
Data Retention Current
CEЊVcc -0.2V
V
IN
Њ
Vcc - 0.2V or V
IN
Љ
0.2V
-- 0.01 0.2 uA
t
CDR
Chip Deselect to Data
Retention Time
0---- ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-- -- ns
SYMBOL PARAMETER CONDITIONS MAX. UNIT
C
IN
Input
Capacitance
VIN=0V 6 pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V 8 pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial 0OC to +70OC1.8V ~ 3.6V
Industrial -40OC to +85OC1.8V ~ 3.6V
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
DATA RETENTION CHARACTERISTICS ( TA = 0
o
C to + 70oC )
1. Vcc = 1.5V, TA= + 25OC
2. t
RC
= Read Cycle Time
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
DC ELECTRICAL CHARACTERISTICS ( TA = 0
o
C to + 70oC )
SYMBOL PARAMETER RATING UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias C-40 to +125
O
T
STG
Storage Temperature C-60 to +150
O
P
T
Power Dissipation 1.0 W
I
OUT
DC Output Current 20 mA
BSI
BS616UV1010
PARAMETER
NAME
PARAMETER TEST CONDITIONS MIN. TYP.
(1)
MAX.
UNITS
Vcc=2.0V
0.6
V
IL
Guaranteed Input Low
Voltage
(2)
Vcc=3.0V
-0.5 --
0.8
V
Vcc=2.0V
1.4
V
IH
Guaranteed Input High
Voltage
(2)
Vcc=3.0V
2.0
-- Vcc+0.2 V
I
IL
Input Leakage Current Vcc = Max, V
IN
= 0V to Vcc -- -- 1 uA
IOL Output Leakage Current
Vcc = Max, CE = V
IH
, or OE = VIH,
V
I/O
= 0V to Vcc
-- -- 1 uA
Vcc=2.0V
VOL Output Low Voltage Vcc = Max, IOL = 1mA
Vcc=3.0V
-- -- 0.4 V
Vcc=2.0V
1.6
VOH Output High Voltage Vcc = Min, IOH = -0.5mA
Vcc=3.0V
2.4
-- -- V
Vcc=2.0V
-- -- 10
I
CC
Operating Power Supply
Current
CE = V
IL
, IDQ = 0mA, F = Fmax
(3)
Vcc=3.0V
-- -- 15
mA
Vcc=2.0V
-- -- 0.5
I
CCSB
Standby Current-TTL CE = VIH, IDQ = 0mA
Vcc=3.0V
-- -- 1
mA
Vcc=2.0V
-- 0.01 0.3
I
CCSB1
Standby Current-CMOS
CE Њ Vcc-0.2V,
V
IN
Њ
Vcc - 0.2V or V
IN
Љ
0.2V
Vcc=3.0V
-- 0.02 0.5
uA
Page 4
Revision 2.2
April 2001
4
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616UV1010-15
MIN. TYP. MAX.
UNIT
t
AVAX
t
RC
Read Cycle Time
150 -- -- ns
t
AVQV
t
AA
Address Access Time
-- -- 150 ns
t
ELQV
t
ACS
Chip Select Access Time
(CE) -- -- 150 ns
t
BA
t
BA
Data Byte Control Access Time
(LB,UB) -- -- 150 ns
t
GLQV
t
OE
Output Enable to Output Valid
-- -- 80 ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
(CE) 15 -- -- ns
t
BE
t
BE
Data Byte Control to Output Low Z
(LB,UB) 15 -- -- ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
15 -- -- ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
(CE) 0 -- 45 ns
t
BDO
t
BDO
Data Byte Control to Output High Z
(LB,UB) 0 -- 40 ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0--40ns
t
AXOX
t
OH
Output Disable to Output Address Change
15 -- -- ns
R0201-BS616UV1010
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS ( TA = 0
o
C to + 70oC, Vcc = 2.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CAR
ANY CHANG
PERMITTED
E: CHANGE :
E STATE
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
LOW V
CC
DATA RETENTION WAVEFORM ( CE Controlled )
CE
Data Retention Mode
Vcc
t CDR
Vcc
t R
VIHVIH
Vcc
VDR 1.5V
≥
CE Vcc - 0.2V
≥
BSI
BS616UV1010
Ω800
THEVENIN EQUIVALENT
ALL INPUT PULSES
→
10%
90%
←
Vcc
GND
→
←
5ns
90%
10%
1.2V
OUTPUT
FIGURE 2
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1333
Ω
2000
5PF
FIGURE 1B
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1333
Ω
100PF
FIGURE 1A
2000
Page 5
Revision 2.2
April 2001
5
R0201-BS616UV1010
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t RC
t OH
t AA
D
OUT
ADDRESS
t OH
t OH
READ CYCLE3
(1,4)
t RC
t OE
D
OUT
LB,UB
CE
OE
ADDRESS
t CLZ
(5)
t ACS
t CHZ
(1,5)
t OHZ
(5)
t OLZ
t AA
READ CYCLE2
(1,3,4)
t CLZ
t CHZ
(5)
D
OUT
LB,UB
CE
(5)
t BA
t ACS
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = V
IL.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL .
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
±
t BE
t BDO
t BDO
t BA
t BE
BSI
BS616UV1010
Page 6
Revision 2.2
April 2001
6
R0201-BS616UV1010
t WR
AC ELECTRICAL CHARACTERISTICS ( TA = 0
o
C to + 70oC, Vcc = 2.0V )
WRITE CYCLE
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
t WC
(3)
t CW
(11)
t BW
(2)
t WP
t AW
t OHZ
(4,10)
t AS
(3)
t DH
t DW
D
IN
D
OUT
WE
LB,UB
CE
OE
ADDRESS
(5)
BSI
BS616UV1010
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616UV1010-15
MIN. TYP. MAX.
UNIT
t
AVAX
Write Cycle Time
t
WC
150 -- -- ns
t
E1LWH
t
CW
Chip Select to End of Write
150 -- -- ns
t
AVWL
t
AS
Address Setup Time
0---n-s
t
AVWH
t
AW
Address Valid to End of Write
150 -- -- ns
t
WLWH
t
WP
Write Pulse Width
80 -- -- ns
t
WHAX
t
WR
Write recovery Time
(CE,WE) 0 -- -- ns
t
BW
t
BW
Date Byte Control to End of Write
(LB,UB) 70 -- -- ns
t
WLQZ
t
WHZ
Write to Output in High Z
0--40ns
t
DVWH
t
DW
Data to Write Time Overlap
40 -- -- ns
t
WHDX
t
DH
Data Hold from Write Time
0---n-s
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0--40ns
t
WHOX
t
OW
End of Write to Output Active
5---n-s
Page 7
Revision 2.2
April 2001
7
R0201-BS616UV1010
WRITE CYCLE2
(1,6)
t WC
t CW
(11)
(2)
t WP
t AW
t WHZ
(4,10)
t AS
t WR
(3)
t DH
t DW
D
IN
D
OUT
WE
CE
ADDRESS
(5)
t DH
(7) (8)
(8,9)
t BW
LB,UB
BSI
BS616UV1010
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. T
WR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL ).
7. D
OUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. T
CW is measured from the later of CE going low to the end of write.
12. The change of Read/Write cycle must accompany with CE or address toggled.
±
Page 8
Revision 2.2
April 2001
8
R0201-BS616UV1010
PACKAGE
E: TSOP II - 44 PIN
A: BGA-48 PIN(6x8mm)
ORDERING INFORMATION
BSI
BS616UV1010 X X -- Y Y
GRADE
C: +0
o
C ~ +70oC
I: -40
o
C ~ +85oC
SPEED
15: 150ns
PACKAGE DIMENSIONS
BS616UV1010
TSOP2-44
Page 9
Revision 2.2
April 2001
9
R0201-BS616UV1010
BSI
BS616UV1010
PACKAGE DIMENSIONS (continued)
48 mini-BGA (6 x 8)
D1
VIEW A
1.4 Max.
e
E1
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
8.0 6.0
EN
48 3.75
E1D1
5.25
NOTES:
Page 10
Revision 2.2
April 2001
10
BSI
R0201-BS616UV1010
REVISION HISTORY
Revision Description Date Note
2.2 2001 Data Sheet release Apr. 15, 2001
BS616UV1010
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