Page 1
BSI
Very Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
BS616LV8025
FEATURES
DESCRIPTION
• Very low operation voltage : 4.5 ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I-grade : 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns (Max.) at Vcc= 5.0V
-70 70ns (Max.) at Vcc= 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
The BS616LV8025 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 3uA and maximum access time of 55/70ns in 5.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV8025 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8025 is available in 48-pin BGA type.
PRODUCT FAMILY
SPEED
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
(ns)
Vcc=5V Vcc=5V Vcc=5V
BS616LV8025BC +0OC to +70OC 4.5V ~ 5.5V 55/70 30uA 45mA BGA-48-0810
POWER DISSIPATION
STANDBY
(I
, Max)
CCSB1
Operating
(ICC, Max)
PKG TYPE
BS616LV8025BI -40OC to +85OC 4.5V ~5.5V 55/70
PIN CONFIGURATIONS
123456
A
B
C
D
E
F
G
H
OE A0 A1
LB
D8
D9 D10 A5 A6 D1 D2
VSS
VCC
D14 D13 A14
D15 CIO.
A18
48-Ball CSP top View
A3 A4
UB
D11 A17 A7
D12
A8 A9
A16 D4 VSS
VSS
A15
A12 A13
A10 A 11 SAE.
A2
CE1
D3
VCC
D5 D6
WE
CE2
D0
D7
100uA
BLOCK DIAGRAM
A15
A14
A13
A12
Address
A11
A10
A9
A8
A17
A7
A6
D15
CE1
CE2
WE
UB
CIO
Vdd
GND
D0
.
.
.
.
.
.
.
.
OE
LB
Input
Buffer
16(8)
16(8)
Control
22
Data
Input
Buffer
Data
Output
Buffer
50mA BGA-48-0810
2048
Row
Decoder
16(8)
16(8)
A16
A0
Memory Array
2048 x 4096
Column I/O
Write Driver
Sense Amp
256(512)
Column Decoder
Address Input Buffer
A4
A1 A2 A3
4096
16(18)
A5
A18
(SAE)
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8025
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Revision 2.4
April 2002
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BSI
PIN DESCRIPTIONS
Name Function
BS616LV8025
A0-A18 Address Input
SAE Address Input
CIO x8/x16 select input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Vcc
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
This address input incorporate with the above 19 address inputs select one of the
1,048,576 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
This input selects the organization of the SRAM. 524,288 x 16-bit words configuration
is selected if CIO is HIGH. 1,048,576 x 8-bit bytes configuration is selected if CIO is
LOW.
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Vss
R0201-BS616LV8025
Ground
2
Revision 2.4
April 2002
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BSI
TRUTH TABLE
MODE CE1 CE2 OE WE CIO LB UB SAE D0~7 D8~15 VCC Current
BS616LV8025
Fully Standby
Output Disable
Read from SRAM
( WORD mode )
Write to SRAM
( WORD mode )
Read from SRAM
( BYTE Mode )
Write to SRAM
( BYTE Mode )
HX X
XL
LHHH
LH
LH
LH
LH
X
X
H
L
L
X
H
L
L
X
X
X
H
H
L
L
X
X
L
H
L
L
H
L
X
X
X
X
XX
H
L
L
H
L
L
XA-1
XA-1
X
X
X
High-Z
High-Z
Dout
High-Z
Dout
Din
X
Din
Dout
Din
High-Z
High-Z
High-Z
Dout
Dout
X
Din
Din
High-Z
X
I
CCSB
, I
I
I
I
I
I
CCSB1
CC
CC
CC
CC
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL PAR AMETER RATING UNITS
TERM
V
BIAS
T
STG
T
T
P
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS616LV8025
Terminal Voltage with
Respect to GND
Temperature Under Bias -40 to +125
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current 20 mA
-0.5 to
Vcc+0.5
V
O
C
O
C
OPERATING RANGE
RANGE
Commercial 0OC to +70OC4.5V ~ 5.5V
Industrial -40OC to +85OC4.5V ~ 5.5V
CAPACITANCE
SYMBOL PARAMETER CONDITIONS MAX. UNIT
IN
C
DQ
C
1. This parameter is guaranteed and not tested.
3
AMBIENT
TEMPERATURE
(1)
(TA = 25oC, f = 1.0 MHz)
Input
Capacitance
Input/Output
Capacitance
Vcc
VIN=0V 10 pF
I/O
V
=0V 12 pF
Revision 2.4
April 2002
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BSI
BS616LV8025
DC ELECTRICAL CHARACTERISTICS ( TA = 0
PAR AMETER
NAME
V
V
I
IOL Output Leakage Current
VOL Output Low Voltage Vcc= max, IOL = 2mA
VOH Output High Voltage Vcc= Min, IOH = -1mA
I
I
I
IL
IH
IL
CC
CCSB
Standby Current-TTL
CCSB1
Standby Current-CMOS
PAR AMETER TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current Vcc = Max, V
Vcc = Max, CE1 = V
OE = V
Operating Power Supply
Current
Vcc= max, CE1 = VIL and CE2 =
IH
, IDQ = 0mA, F = Fmax
V
Vcc= max, CE1 = V
IL
, IDQ = 0mA
V
Vcc= max,CE1 Њ Vcc-0.2V, or
CE2 Љ 0.2V, V
IN
or V
IN
= 0V to Vcc -- -- 1 uA
IH
I/O
, V
= 0V to Vcc
Љ
0.2V
o
C to + 70oC )
IH
, or CE2 = ViL, or
(3)
IH
or CE2 =
IN
Њ
Vcc - 0.2V
Vcc=5V
Vcc=5V
Vcc=5V
Vcc=5V
Vcc=5V
Vcc=5V
Vcc=5V
(1)
MAX. UNITS
-0.5 -- 0.8 V
2.2 -- Vcc+0.2 V
-- -- 1 uA
-- -- 0.4 V
2.4 -- -- V
-- -- 45 mA
-- -- 2 mA
-- 3 30 uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/ t
.
RC
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Revision 2.4
April 2002
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BSI
BS616LV8025
DATA RETENTION CHARACTERISTICS ( TA = 0
o
C to +70oC )
SYMBOL PAR AMETER TEST CONDITIONS MIN. TYP.
V
I
CCDR
t
CDR
t
DR
R
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
1. Vcc = 1.5V, TA= + 25OC
2. tRC= Read Cycle Time
LOW V
DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
CC
Vcc
CE1
CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V ,
Њ
Vcc - 0.2V or V
V
IN
Љ
0.2V
IN
CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V,
Њ
Vcc - 0.2V or V
V
IN
Љ
0.2V
IN
See Retention Waveform
Data Retention Mode
Vcc
VDR Њ 1.5V
t CDR
CE1 Њ Vcc - 0.2V
1.5 -- --
-- 0.2 2
0 -- --
(2)
T
RC
Vcc
t R
VIHVIH
(1)
MAX. UNITS
V
uA
ns
-- -- ns
LOW V
DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
CC
Vcc
CE2
R0201-BS616LV8025
Data Retention Mode
Vcc
VDR Њ 1.5V
t CDR
VIL
CE2 Љ 0.2V
5
Vcc
t R
VIL
Revision 2.4
April 2002
Page 6
BSI
BS616LV8025
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC TEST LOADS AND WAVEFORMS
Ω
5.0V
OUTPUT
INCLUDING
JIG AND
SCOPE
Vcc
GND
1928
100PF
FIGURE 1A
OUTPUT
Ω
1020
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
→
←
FIGURE 2
90%
5.0V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω667
90%
→
10%
←
5ns
1.73V
Ω
1928
5PF
1020
FIGURE 1B
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
Ω
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = 0
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
E2LQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXQX
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
(1)
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Output Disable to Output Address Change
NOTE :
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle .
BA is 55ns/70ns (@speed=55ns/70ns) without address toggle .
t
DESCRIPTION
o
C to +70oC, Vcc=5V )
BS616LV8025-55
MIN. TYP. MAX.
(CE1)
(CE2)
(LB,UB)
(CE2,CE1)
(LB,UB)
(CE2,CE1)
(LB,UB)
55
10
10
10
10
BS616LV8025-70
UNIT
MIN. TYP. MAX.
70
55
55
55
30
30
70
70
70
35
35
10
10
10
0
0
0
30
30
25
0
0
0
35
35
30
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS616LV8025
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Revision 2.4
April 2002
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BSI
BS616LV8025
READ CYCLE1
ADDRESS
D
OUT
READ CYCLE2
CE2
CE1
D
OUT
READ CYCLE3
ADDRESS
(1,2,4)
(1,3,4)
(1,4)
t OH
t CLZ
(5)
t AA
t ACS2
t ACS1
t AA
t RC
t RC
t OH
t CHZ
(5)
OE
t OE
CE2
CE1
t CLZ
LB,UB
(5)
t ACS2
t OLZ
t ACS1
t BE
t BA
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
±
IL and CE2 = VIH.
t OHZ
t CHZ
t BDO
t OH
(5)
(1,5)
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BSI
BS616LV8025
AC ELECTRICAL CHARACTERISTICS ( TA = 0
o
C to +70oC, Vcc=5V)
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
BW
t
WLQZ
t
DVWH
t
WHDX
t
GHQZ
t
WHQX
NOTE :
1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
(1)
t
BW
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
Write Cycle Time
Chip Select to End of Write
Address Set up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
DESCRIPTION
(CE2, CE1, WE)
(LB,UB)
BS616LV8025-55
MIN. TYP. MAX.
55
55
0
55
30
0
25
0
25
0
0
5
25
25
BS616LV8025-70
MIN. TYP. MAX.
70
70
0
70
35
0
30
0
30
0
0
5
30
30
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
t WC
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADDRESS
OE
CE2
CE1
LB,UB
WE
D
OUT
t AS
(4,10)
t OHZ
(3)
t WR
(5)
(11)
(5)
t CW
t BW
(5)
t AW
t WP
(2)
(3)
t DH
t DW
D
IN
R0201-BS616LV8025
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Revision 2.4
April 2002
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BSI
BS616LV8025
WRITE CYCLE2
ADDRESS
CE2
CE1
LB,UB
WE
D
OUT
D
IN
(1,6)
t AS
(5)
(5)
(4,10)
t WHZ
t AW
t WC
t CW
t BW
t WP
(11)
t WR
(3)
(2)
t DH
(7) (8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. T
WR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
7. D
OUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. T
CW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV8025
IL ).
±
9
Revision 2.4
April 2002
Page 10
BSI
ORDERING INFORMATION
BS616LV8025 X X -- Y Y
BS616LV8025
SPEED
55: 55ns
70: 70ns
GRADE
o
C: +0
C ~ +70oC
o
I: -40
C ~ +85oC
PACKAGE
B :BGA - 48 PIN(8x10mm)
PACKAGE DIMENSIONS
1.4 Max.
e
VIEW A
SIDE VIEW
D0.1
D1
0.05
0.25
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
N ED
48 10.0 8.0
0.1
E1
E
E1D1 e
3.755.25 0.75
SOLDER BALL 0.350.05
48 mini-BGA (8 x 10mm)
R0201-BS616LV8025
10
Revision 2.4
April 2002
Page 11
BSI
BS616LV8025
REVISION HISTORY
Revision Description Date Note
2.2 2001 Data Sheet release Apr. 15, 2001
2.3 Modify Standby Current (Typ. and
Max.)
2.4 Modify some AC parameters.
Modify 5V ICCSB1_Max(I-grade)
from 50uA to 100uA.
Jun. 29, 2001
April,12,2002
R0201-BS616LV8025
11
Revision 2.4
April 2002
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