Datasheet BS616LV8023BI, BS616LV8023BC Datasheet (BSI)

BSI

Very Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit switchable

BS616LV8023

 FEATURES

 DESCRIPTION

• Very low operation voltage : 2.4 ~ 3.6V

• Very low power consumption : Vcc = 3.0V C-grade: 20mA (Max.) operating current

I-grade : 25mA (Max.) operating current

0.5uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc= 3.0V

-10 100ns (Max.) at Vcc= 3.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE1, CE2 and OE options

• I/O Configuration x8/x16 selectable by CIO, LB and UB pin

The BS616LV8023 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits or 1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide range of 2.4V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.5uA and maximum access time of 70/100ns in 3.0V operation. Easy memory expansion is provided by an active HIGH chip enable2(CE2), active LOW chip enable1(CE1), active LOW output enable(OE) and three-state output drivers. The BS616LV8023 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8023 is available in 48-pin BGA type.

 PRODUCT FAMILY

SPEED

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

BS616LV8023BC +0OC to +70OC 2.4V ~ 3.6V 70 / 100

BS616LV8023BI -40OC to +85OC 2.4V ~ 3.6V 70 / 100 6uA

(ns)

Vcc=3.0V

(I

POWER DISSIPATION

STANDBY

, Max)

CCSB1

Vcc=3V

3uA

Operating

(I

, Max)

CC

Vcc=3V

20mA

25mA

PKG TYPE

BGA-48-0810

 PIN CONFIGURATIONS

123456

A

LB OE A0 A1 A2

D8

B

D9

C

D

VSS

VCC

E

D14 D13 A14

F

D15 CIO.A

G

A18

H

48-Ball CSP top View

A3 A4

UB

A5 A6 D1 D2

D10

D11 A17 A 7

D12

A8 A9

A16 D4 VSS

VSS

A15

12 A13

A10 A11 SAE.

CE1

D3

VCC

D5 D6

WE

CE2

D0

D7

 BLOCK DIAGRAM

A15 A14 A13

A12

Address

A11 A10

A9

A8 A17 A7 A6

D15

CE1

CE2

CIO

Vdd Vss

WE

UB

D0

.

OE

LB

Input

Buffer

16(8)

Control

22

Data Input Buffer

Data

Output

Buffer

Row

Decoder

16(8)

2048

A16

A0

A1 A2 A3

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS616LV8023

1

Memory Array

2048 x 4096

4096

Column I/O

Write Driver

Sense Amp

256(512)

Column Decoder

16(18)

Address Input Buffer

A4

A5

A18

(SAE)

Revision 2.0 April 2002

BSI

 PIN DESCRIPTIONS

Name Function

BS616LV8023

A0-A18 Address Input

SAE Address Input

CIO x8/x16 select input

CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input

WE Write Enable Input

OE Output Enable Input

LB and UB Data Byte Control Input

D0 - D15 Data Input/Output Ports

Vcc

These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.

This address input incorporate with the above 19 address inputs select one of the

1,048,576 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.

This input selects the organization of the SRAM. 524,288 x 16-bit words configuration

is selected if CIO is HIGH. 1,048,576 x 8-bit bytes configuration is selected if CIO is LOW.

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when

data read from or write to the device. If either chip enable is not active, the device is

deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

Lower byte and upper byte data input/output control pins. The chip is deselected when

both LB and UB pins are HIGH.

These 16 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

Vss

R0201-BS616LV8023

Ground

2

Revision 2.0 April 2002

BSI

 TRUTH TABLE

MODE CE1 CE2 OE WE CIO LB UB SAE D0~7 D8~15 VCC Current

BS616LV8023

Fully Standby

Output Disable

Read from SRAM

( WORD mode )

Write to SRAM

( WORD mode )

Read from SRAM

( BYTE Mode )

Write to SRAM

( BYTE Mode )

H

X

L

HHH

L

HLH

L

HXL

L

HLH

L

HXL

XX

X

H

L

X

L

H

L

H

L

X

XX

A-1

High-Z

X

X High-Z High-Z

Dout High-Z

X

High-Z Dout

Dout Dout

Din

X

Din

Dout High-Z

Din X

High-Z

X

Din

I

CCSB

, I

I

CCSB1

CC

 ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PAR AMET E R RATING UNITS

TERM

V

BIAS

T

STG

T

P

OUT

I

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

R0201-BS616LV8023

Terminal Voltage with Respect to GND

Temperature Under Bias -40 to +125

Storage Temperature -60 to +150

Power Dissipation 1.0 W

DC Output Current 20 mA

-0.5 to

Vcc+0.5

V

O

C

O

C

 OPERATING RANGE

RANGE

Commercial 0OC to +70OC2.4V ~ 3.6V

Industrial -40OC to +85OC2.4V ~ 3.6V

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

IN

C

DQ

C

1. This parameter is guaranteed and not tested.

3

AMBIENT

TEMPERATURE

(1)

(TA = 25oC, f = 1.0 MHz)

Input Capacitance Input/Output Capacitance

Vcc

VIN=0V 10 pF

I/O

V

=0V 12 pF

Revision 2.0 April 2002

BSI

BS616LV8023

 DC ELECTRICAL CHARACTERISTICS ( TA = 0

PAR AME TE R

NAME

V

I

IOL Output Leakage Current

IL

IH

IL

PAR AME TE R TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage Guaranteed Input High

(2)

Voltage

Input Leakage Current Vcc = Max, V

Vcc = Max, CE1 = V

IH

OE = V

o

C to + 70oC )

IN

= 0V to Vcc -- -- 1 uA

I/O

, V

= 0V to Vcc

VOL Output Low Voltage Vcc= max, IOL = 2mA

VOH Output High Voltage Vcc= Min, IOH = -1mA

I

CC

CCSB

Operating Power Supply Current

Standby Current-TTL

Vcc= max, CE1 = V

IH

V

, IDQ = 0mA, F = Fmax

Vcc= max, CE1 = V

IL

V

, IDQ = 0mA

Vcc= max,CE1 Њ Vcc-0. 2V, or

IN

I

CCSB1

Standby Current-CMOS

CE2 Љ 0.2V; V

IN

Љ

or V

0.2V

Њ Vcc - 0.2V

IH

, or CE2 = ViL, or

IL

and CE2 =

(3)

IH

or CE2 =

Vcc=3V

(1)

MAX. UNI TS

-0.5 -- 0.8 V

2.0 -- Vcc+0.2 V

-- -- 1 uA

-- -- 0.4 V

2.4 -- -- V

-- -- 20 mA

-- -- 1 mA

-- 0.5 3 uA

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/ t

R0201-BS616LV8023

.

RC

4

Revision 2.0 April 2002

BSI

BS616LV8023

 DATA RETENTION CHARACTERISTICS ( TA = 0

o

C to +70oC )

SYMBOL PAR AMET ER TEST CONDITIONS MIN. TYP.

V

I

CCDR

t

CDR

t

DR

R

Vcc for Data Retention

Data Retention Current

Chip Deselect to Data Retention Time

Operation Recovery Time

1. Vcc = 1.5V, TA= + 25OC

2. tRC= Read Cycle Time

 LOW V

DATA RETENTION WAVEFORM (1) ( CE1 Controlled )

CC

Vcc

CE1

CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V;

Њ

Vcc - 0.2V or V

V

IN

Љ

0.2V

IN

CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V

Њ

Vcc - 0.2V or V

V

IN

Љ

0.2V

IN

See Retention Waveform

Data Retention Mode

Vcc

VDR Њ 1.5V

t CDR

CE1 Њ Vcc - 0.2V

1.5 -- --

-- 0.2 2

0 -- --

(2)

T

RC

Vcc

t R

VIHVIH

(1)

MAX. UNITS

V

uA

ns

-- -- ns

 LOW V

DATA RETENTION WAVEFORM (2) ( CE2 Controlled )

CC

Vcc

CE2

R0201-BS616LV8023

Data Retention Mode

Vcc

VDR Њ 1.5V

t CDR

VIL

CE2 Љ 0.2V

5

Vcc

t R

VIL

Revision 2.0 April 2002

BSI

BS616LV8023

 AC TEST CONDITIONS

Input Pulse Levels Vcc/0V

Input Rise and Fall Times 5ns

Input and Output

0.5Vcc

Timing Reference Level

Output Load CL=100pF+1TTL

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

o

C to +70oC, Vcc=3.0V )

MUST BE STEADY

MAY CHANGE FROM H TO L

MAY CHANGE FROM L TO H

,

DON T CARE: ANY CHANGE PERMITTED

DOES NOT APPLY

MUST BE STEADY

WILL BE CHANGE FROM H TO L

WILL BE CHANGE FROM L TO H

CHANGE : STATE UNKNOWN

CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

E1LQV

t

E2LQV

t

BA

t

GLQV

t

ELQX

t

BE

t

GLQX

t

EHQZ

t

BDO

t

GHQZ

t

AXQX

NOTE :

1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle .

BA is 70ns/100ns (@speed=70ns/100ns) without address toggle .

t

PARAMETER

NAME

t

RC

t

AA

t

ACS1

t

ACS2

(1)

t

BA

t

OE

t

CLZ

t

BE

t

OLZ

t

CHZ

t

BDO

t

OHZ

t

OH

Read Cycle Time

Address Access Time

Chip Select Access Time

Chip Select Access Time Data Byte Control Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Data Byte Control to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Data Byte Control to Output High Z

Output Disable to Output in High Z

Output Disable to Output Address Change

DESCRIPTION

(CE1) (CE2)

(LB,UB)

(CE2,CE1)

(LB,UB)

(CE2,CE1)

(LB,UB)

BS616LV8023-70

MIN. TYP. MAX.

70

35

10

0

10

35

30

BS616LV8023-10

MIN. TYP. MAX.

100

50

15

0

15

40

35

UNIT

ns ns

ns

R0201-BS616LV8023

6

Revision 2.0 April 2002

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t OH

OUT

t AA

BS616LV8023

t RC

t OH

READ CYCLE2

CE2

CE1

D

OUT

READ CYCLE3

ADDRESS

OE

CE2

CE1

(1,3,4)

(1,4)

t CLZ

t ACS2

t ACS1

t CLZ

t AA

t OLZ

t ACS1

t ACS2

t OE

t RC

t OHZ

t CHZ

t OH

(1)

LB,UB

t BE

t BA

D

OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = V

3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.

4. OE = VIL .

R0201-BS616LV8023

IL and CE2 = VIH.

7

t BDO

Revision 2.0 April 2002

BSI

BS616LV8023

 AC ELECTRICAL CHARACTERISTICS ( TA = 0

o

C to +70oC, Vcc=3.0V)

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

BW

t

WLQZ

t

DVWH

t

WHDX

t

GHQZ

t

WHQX

NOTE :

1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle.

PARAMETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR

(1)

t

BW

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

Write Cycle Time

Chip Select to End of Write

Address Set up Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time

Data Byte Control to End of Write

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

DESCRIPTION

(CE2, CE1, WE)

(LB,UB)

BS616LV8023-70

MIN. TYP. MAX.

70

0

70

35

0

30

0

30

0

5

30

BS616LV8023-10

MIN. TYP. MAX.

100

0

100

50

0

40

0

40

0

10

40

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

t WC

UNIT

ns ns

ns

ADDRESS

OE

CE2

CE1

LB,UB

WE

D

OUT

t AS

(4)

t OHZ

(3)

t WR

(5)

(10)

(5)

t CW

t BW

(5)

t AW

t WP

(2)

(3)

t DH

t DW

D

IN

R0201-BS616LV8023

8

Revision 2.0 April 2002

BSI

BS616LV8023

WRITE CYCLE2

ADDRESS

CE2

CE1

LB,UB

WE

D

OUT

D

IN

(1,6)

t AS

(5)

(4)

t WHZ

t AW

t WC

t CW

t BW

t WP

(10)

t WR

(3)

(2)

t DH

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. T

WR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT is the same phase of write data of this write cycle.

8. D

OUT is the read data of next address.

9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.

CW is measured from the later of CE2 going high or CE1 going low to the end of write.

10. T

R0201-BS616LV8023

IL ).

9

Revision 2.0 April 2002

BSI

 ORDERING INFORMATION

BS616LV8023 X X -- Y Y

BS616LV8023

SPEED

70: 70ns 10: 100ns

GRADE

o

C: +0

C ~ +70oC

o

I: -40

C ~ +85oC

PACKAGE

B :BGA - 48 PIN(8x10mm)

 PACKAGE DIMENSIONS

1.4 Max.

e

VIEW A

SIDE VIEW

D0.1

D1

0.05

0.25 

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

N ED

48 10.0 8.0

0.1

E1

E

E1D1 e

3.755.25 0.75

SOLDER BALL 0.350.05

48 mini-BGA (8 x 10mm)

R0201-BS616LV8023

10

Revision 2.0 April 2002

BSI

BS616LV8023

REVISION HISTORY

Revision Description Date Note

1.0 initial release March 04, 2002

2.0 Modify some AC parameters April,12,2002

R0201-BS616LV8023

11

Revision 2.0 April 2002