Datasheet BS616LV8013BI, BS616LV8013BC Datasheet (BSI)

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BSI
Very Low Power/Voltage CMOS SRAM 512K X 16 bit
BS616LV8013
FEATURES
• Very low operation voltage : 2.4~3.6V
• Very low power consumption : Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc=3V
-10 100ns (Max.) at Vcc=3V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
PRODUCT FAMILY
OPERATING
TEMPERATURE
BS616LV8013BC +0OC to +70OC 2.4V ~ 3.6V 70 / 100
O
BS616LV8013BI -40
C to +85OC 2.4V ~ 3.6V 70 / 100
Vcc
RANGE
DESCRIPTION
The BS616LV8013 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits and operates from a wide range of 2.4V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.5uA and maximum access time of 70/100ns in 3V operation. Easy memory expansion is provided by an active LOW chip enable(CE1), active HIGH chip enable (CE2), active LOW output enable(OE) and three-state output drivers. The BS616LV8013 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8013 is available in 48-pin BGA package.
SPEED
(ns)
Vcc=3V
POWER DISSIPATION
STANDBY
(I , Max)CCSB1
Vcc=3V
3uA
6uA
Operating
(I , Max)CC
Vcc=3V
20mA
PKG TYPE
BGA-48-0810
25mA BGA-48-0810
PIN CONFIGURATIONS
123456
A
LB OE A0 A1 A2
B
D8
UB
A3 A4 CE1 D0
D9
C
VSS D11 A17 A7 D3 VCC
D
VCC
E
D14 D13 A14
F
D15
G
A8
1
H
48-Ball CSP top View
A5 A6 D1 D2
D10
VSS
D12
A12
NC.
A8 A9
A16 D4
A15
A13 WE D7
A10 A11
CE2
VSS
D5 D6
NC
BLOCK DIAGRAM
A4 A3 A2
A1
Address
D0
D15
A17
A16
A15 A14 A13 A12
Vcc Gnd
A0
CE2 CE1
WE
OE
UB
LB
Input
Buffer
16
.
.
.
.
.
. .
16
.
Control
22
Data Input Buffer
Data
Output
Buffer
Row
Decoder
2048
16
16
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8013
1
Memory Array
2048 x 4096
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
A10
A9 A8 A7
A11
4096
256
16
A5
A6
Revision 2.0 April 2002
A18
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BSI
PIN DESCRIPTIONS
Name Function
BS616LV8013
A0-A18 Address Input
CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Vcc
Gnd
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device
deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE CE1 CE2 WE OE LB UB D0~D7 D8~D15 Vcc CURRENT
Not selected
(Power Down)
Output Disabled
Read L H H L
Write L H L X
H
X
L
ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMET E R RATING UNITS
TERM
V
BIAS
T
STG
T
T
P
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Terminal Voltage with Respect to GND
Temperature Under Bias -40 to +125
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current 20 mA
XXXXX High Z High Z I
LXXXX High Z High Z I
H H H X X High Z High Z I
L L Dout Dout I
HL High Z Dout I
L H Dout High Z I
LL Din Din I
HL X Din I
LH Din X I
(1)
-0.5 to
Vcc+0.5
V
O
C
O
C
, I
CCSB
, I
CCSB
CC
CC
CC
CC
CC
CC
CC
OPERATING RANGE
RANGE
Commercial 0OC to +70OC2.4V ~ 3.6V
Industrial -40OC to +85OC2.4V ~ 3.6V
CAPACITANCE
SYMBOL PARAMETER CONDITIONS MAX. UNIT
IN
C
DQ
C
1. This parameter is guaranteed and not tested.
AMBIENT
TEMPERATURE
(1)
(TA = 25oC, f = 1.0 MHz)
Input Capacitance Input/Output Capacitance
Vcc
VIN=0V 10 pF
I/O
V
=0V 12 pF
is
CCSB1
CCSB1
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BSI
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70
PARAMETER
NAME
VIL
V
IH
IL
I
OL
I
V
OL
V
OH
PARAMETER TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current = 0V to VccVcc = Max, V
Output Leakage Current
Vcc = Max, CE1 = V OE = V , V = 0V to
Output Low Voltage = 2mA VVcc = Max, I
Output High Voltage = -1mAVcc = Min, I
IN
IH I/O
OL
OH
o
C )
, or CE2 =
IH
Vcc
ViL, or
Vcc=3V
Vcc=3V
Vcc=3V
Vcc=3V
BS616LV8013
(1)
MAX.
-0.5
2.0 --
-- -- 1 uA
-- -- 1 uA
-- --
2.4
--
Vcc+0.2
-- --
0.8
0.4
UNITS
V
V
V
CC
I
I
CCSB
CCSB1
I
Operating Power Supply Current V
Standby Current-TTL
Standby Current-CMOS
Vcc= max, CE1 = V
IH
, IDQ= 0mA, F =
Vcc= max, CE1 = V
IL DQ
V, I = 0mA
Vcc= max,CE1
Љ
0.2V, V
CE2
Љ
IN
0.2V
or V
IL
Fmax
IH
Њ
Vcc-0.2V, or
Њ
IN
Vcc - 0.2V
and CE2 =
(3)
or CE2 =
Vcc=3V
Vcc=3V
Vcc=3V
--
--
--
--
--
0.5 3
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.
V
DR
I
CCDR
t
CDR
t
R
.
RC
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
o
C )
CE1 ЊVcc - 0.2V or CE2Љ0.2V
IN
V
Њ
Vcc - 0.2V or V
IN
0.2V
Љ
CE1 ЊVcc - 0.2V or CE2Љ0.2V
IN
V
Њ
Vcc - 0.2V or V
IN
0.2V
Љ
See Retention Waveform
(1)
MAX. UNITS
1.5 -- -- V
-- 0.2 2 uA
0--- n-s
(2)
T
RC
-- -- ns
1. Vcc = 1.5V, TA= + 25OC = Read Cycle Time
2. t
RC
LOW VCCDATA RETENTION WAVEFORM (1) ( CE1 Controlled )
20
mA
1
mA
uA
Data Retention Mode
Vcc
Vcc
VDR 1.5V
t CDR
CE1 Vcc - 0.2V
CE1
LOW VCCDATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
Vcc
CE2
R0201-BS616LV8013
Vcc
t CDR
VIL
VDR Њ 1.5V
CE2 Љ 0.2V
3
Vcc
t R
VIHVIH
Vcc
t R
VIL
Revision 2.0 April 2002
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BSI
BS616LV8013
AC TEST CONDITIONS
Input Pulse Levels Vcc/0V
Input Rise and Fall Times 5ns
Input and Output
0.5Vcc
Timing Reference Level
Output Load CL=100pF+1TTL
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70
READ CYCLE
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
o
C, Vcc=3V)
MUST BE STEADY
MAY CHANGE FROM H TO L
MAY CHANGE FROM L TO H
,
DON T CAR ANY CHANG PERMITTED
DOES NOT APPLY
E: CHANGE :
MUST BE STEADY
WILL BE CHANGE FROM H TO L
WILL BE CHANGE FROM L TO H
E STATE
UNKNOWN
CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle .
t
BA is 70ns/100ns (@speed=70ns/100ns) without address toggle .
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
(1)
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Output Disable to Address Change
(CE1)
(CE2)
(LB,UB)
(CE2,CE1)
(LB,UB)
CE1)
(CE2,
(LB,UB)
BS616LV8013-70
MIN. TYP. MAX.
BS616LV8013-10
MIN. TYP. MAX.
UNIT
70 -- -- 100 -- -- ns
-- -- 70 -- -- 100 ns
--
-- 70 -- -- 100 ns
-- -- 70 -- -- 100 ns
-- -- 35 -- -- 50 ns
-- -- 35 -- -- 50 ns
10 -- -- 15 -- -- ns
10 -- -- 15 -- -- ns
10 -- -- 15 -- -- ns
0
-- 35 0 -- 40 ns
0 -- 35 0 -- 40 ns
0 -- 30 0 -- 35 ns
10 -- -- 15 -- -- ns
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SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
(1,2,4)
t AA
t OH
OUT
BS616LV8013
t RC
t OH
READ CYCLE2
CE2
CE1
D
OUT
READ CYCLE3
ADDRESS
OE
CE2
CE1
(1,4)
(1,3,4)
t CLZ
t CLZ
t ACS2
t ACS1
t ACS1
t AA
t ACS2
t OLZ
t RC
t OE
t OHZ
t CHZ
t CHZ
t OH
(1)
LB,UB
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
3. Address valid prior to or coincident with CE transition low.
4. OE = V
R0201-BS616LV8013
IL .
t BE
t BA
IL and CE2 = VIH.
5
t BDO
Revision 2.0 April 2002
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BSI
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70
o
C, Vcc=3V)
BS616LV8013
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
BW
t
WLQZ
t
DVWH
t
WHDX
t
GHQZ
t
WHOX
NOTE :
1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle.
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
(1)
t
BW
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write recovery Time
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
(CE2,CE1,WE) 0 -- -- 0 -- -- ns
BS616LV8013-70
MIN. TYP. MAX.
BS616LV8013-10
MIN. TYP. MAX.
70 -- -- 100 -- -- ns
70 -- -- 100 -- -- ns
0----0---- ns
70 -- -- 100 -- -- ns
35 -- -- 50 -- -- ns
(LB,UB) 30 -- -- 40 -- -- ns
0 -- 30 0 -- 40 ns
30 -- -- 40 -- -- ns
0----0---- ns
0 -- 30 0 -- 40 ns
5----10---- ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
t WC
UNIT
ADDRESS
OE
CE2
CE1
LB,UB
WE
D
OUT
t AS
(4)
t OHZ
(3)
t WR
(5)
(10)
(5)
t CW
t BW
(5)
t AW
t WP
(2)
(3)
t DH
t DW
D
IN
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BS616LV8013
WRITE CYCLE2
ADDRESS
CE2
CE1
LB,UB
WE
D
OUT
(1,6)
t AS
(5)
(5)
t WHZ
t WC
(10)
t CW
t BW
t AW
(4)
t WP
(2)
t WR
(3)
t DH
(7) (8)
t DW
t DH
(8,9)
D
IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.
3. T
WR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
OUT is the same phase of write data of this write cycle.
7. D
OUT is the read data of next address.
8. D
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.
CW is measured from the later of CE2 going high or CE1 going low to the end of write.
10. T
IL ).
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BSI
ORDERING INFORMATION
BS616LV8013 X X -- Y Y
BS616LV8013
SPEED
70:70ns 10: 100ns
GRADE
o
C: +0
C ~ +70oC
o
I: -40
C ~ +85oC
PACKAGE
B :BGA - 48 PIN(8x10mm)
PACKAGE DIMENSIONS
1.4 Max.
e
VIEW A
SIDE VIEW
D0.1
D1
0.05
0.25
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
N ED
48 10.0 8.0
E1
E0.1
E1D1 e
3.755.25 0.75
SOLDER BALL 0.350.05
48 mini-BGA (8 x 10mm)
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BS616LV8013
REVISION HISTORY
Revision Description Date Note
1.0 Initial release March 04, 2002
2.0 Modify some AC parameters April,11,2002
R0201-BS616LV8013
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Revision 2.0 April 2002
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