Datasheet BS616LV4015EI, BS616LV4015EC, BS616LV4015DI, BS616LV4015DC, BS616LV4015BI Datasheet (BSI)

BSI

Very Low Power/Voltage CMOS SRAM 256K X 16 bit

BS616LV4015

 FEATURES

• Operation voltage : 4.5 ~ 5.5V

• Low power consumption : Vcc = 5.0V C-grade: 45mA (Max.) operating current

I-grade: 50mA (Max.) operating current

1.5uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc = 5.0V

-55 55ns (Max.) at Vcc = 5.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 2V

• Easy expansion with CE and OE options

 DESCRIPTION

The BS616LV4015 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 16 bits and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1.5uA and maximum access time of 55ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable(CE) and active LOW output enable(OE) and three-state output drivers. The BS616LV4015 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV4015 is available in DICE form, JEDEC standard 44-pin TSOP Type II package and 48-pin BGA package.

• I/O Configuration x8/x16 selectable by LB and UB pin

 PRODUCT FAMILY

SPEED

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

( ns )

Vcc=

5.0V

BS616LV4015DC DICE BS616LV4015EC TSOP2-44 BS616LV4015BC BGA-48-0810

O

C to +70OC4.5V ~

+0

5.5V 70/55

BS616LV4015AC BS616LV4015DI DICE BS616LV4015EI TSOP2-44 BS616LV4015BI BGA-48-0810

O

-40

C to +85OC 4.5V ~ 5.5V 70/55

BS616LV4015AI

POWER DISSIPATION

STANDBY

CCSB1

( I

, Max )

Vcc=

5.0V

15uA

50uA

Operating

( ICC, Max )

Vcc=

5.0V

45mA

50mA

PKG TYPE

BGA-48-0608

 PIN CONFIGURATIONS

1

A4

2

A3

3

A2

4

A1

5

A0

6

CE

7

DQ0

8

DQ1

9

DQ2

10

DQ3 VCC

GND

DQ4 DQ5 DQ6 DQ7

WE A17 A16 A15 A14 A13

BS616LV4015EC

11 12

BS616LV4015EI

13 14 15 16 17 18 19 20 21 22

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38

DQ15

37

DQ14

36

DQ13

35

DQ12

34

GND

33

VCC

32

DQ11

31

DQ10

30

DQ9

29

DQ8

28

NC

27

A8

26

A9

25

A10

24

A11

23

A12

 BLOCK DIAGRAM

A4 A3 A2

A1

Address

A0 A17

A16

A15 A14 A13 A12

DQ0

DQ15

CE

WE

UB

Vcc Gnd

.

OE

LB

Input

Buffer

22

16

Control

Data Input Buffer

Data

Output

Buffer

Row

Decoder

2048

16

Memory Array

2048 x 2048

Column I/O

Write Driver

Sense Amp

Column Decoder

Address Input Buffer

A11

A10

A9 A8 A7

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

2048

128

14

A5

A6

R0201-BS616LV4015

1

Revision 2.4 April 2002

BSI

 PIN DESCRIPTIONS

Name Function

BS616LV4015

A0-A17 Address Input

CE Chip Enable Input

WE Write Enable Input

OE Output Enable Input

LB and UB Data Byte Control Input

DQ0 - DQ15 Data Input/Output Ports

Vcc

Gnd

 TRUTH TABLE

These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.

CE is active LOW. Chip enables must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

Lower byte and upper byte data input/output control pins.

These 16 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

Ground

MODE CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT

Not selected

(Power Down)

H X X X X High Z High Z I

Output Disabled L H H X X High Z High Z I

L L Dout Dout I

Read L H L

H L High Z Dout I

L H Dout High Z I

L L Din Din I

Write L L X

H L X Din I

L H Din X I

R0201-BS616LV4015

2

CCSB

, I

CCSB1

CC

Revision 2.4 April 2002

BSI

BS616LV4015

 ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PARAMETER RATING UNITS

V

T

P

I

TERM

BIAS

STG

T

OUT

Terminal Voltage with Respect to GND

Temperature Under Bias -40 to +125

Storage Temperature -60 to +150

Power Dissipation 1.0 W

DC Output Current mA20

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

-0.5 to

Vcc+0.5

V

O

C

O

C

 DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

PARAMETER

NAME

IL

V

IH

V

IL

I

PARAMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage

Guaranteed Input High

(2)

Voltage

Input Leakage Current = 0V to VccVcc = Max, V

IN

 OPERATING RANGE

RANGE

Commercial 0OC to +70OC4.5V ~ 5.5V

Industrial -40OC to +85OC4.5V ~ 5.5V

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

CIN

CDQ

1. This parameter is guaranteed and not tested.

o

C )

Input Capacitance Input/Output Capacitance

Vcc=5.0V

AMBIENT

TEMPERATURE

(1)

(TA = 25oC, f = 1.0 MHz)

Vcc

VIN=0V 6 pF

VI/O=0V 8 pF

(1 )

MAX.

-0.5 -- 0.8 V

2.2 --

Vcc+0.2

-- -- 1 uA

UNITS

V

0.2V

(3)

,

IH

Vcc=5.0V

-- -- 1 uA

-- -- 0.4 V

2.4 -- -- V

-- -- 45 mA

-- -- 2 mA

-- 1.5 15 uA

OL

I

V

CC

I

CCSB

I

CCSB1

I

IH

OL

OH

, or OE = V

Љ

IN

Output Leakage Current

OL

OH

Output Low Voltage = 2mAVcc = Max, I

Output High Voltage = -1mAVcc = Min, I

Operating Power Supply Current

Standby Current-TTL

Standby Current-CMOS

Vcc = Max, CE = V

I/O

V

= 0V to Vcc

IL

CE = V

, IDQ= 0mA, F = Fmax

, IDQ= 0mACE = V

IH

CE

Vcc-0.2V,

Њ

Vcc - 0.2V or V

V

IN

Њ

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

 DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.

V

I

CCDR

t

CDR

t

.

RC

DR

Vcc for Data Retention

Data Retention Current

CEЊVcc - 0.2V

IN

Vcc - 0.2V or V

V

Њ

CEЊVcc -0.2V

IN

Vcc - 0.2V or V

V

Њ

Chip Deselect to Data Retention Time

R

Operation Recovery Time

See Retention Waveform

o

C )

(1)

MAX. UNITS

IN

0.2V

Љ

IN

0.2V

Љ

1.5 -- -- V

-- 0.1 1.5 uA

0--- n-s

(2)

T

RC

-- -- ns

1. Vcc = 1.5V, TA= + 25OC = Read Cycle Time

2. t

RC

R0201-BS616LV4015

3

Revision 2.4 April 2002

BSI

 LOW VCCDATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

≥

Vcc

t CDR

CE

 AC TEST CONDITIONS

Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level

Vcc/0V 5ns

0.5Vcc

 AC TEST LOADS AND WAVEFORMS

5.0V

OUTPUT

INCLUDING JIG AND SCOPE

OUTPUT

Vcc

GND

Ω

1928

100PF

1020

FIGURE 1A

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

→

Ω

←

FIGURE 2

90%

5.0V

OUTPUT

INCLUDING JIG AND SCOPE

Ω667

90%

→

1.73V

10%

← 5ns

Ω

1928

5PF

1020

FIGURE 1B

 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

ELQV

t

BA

t

GLQV

t

ELQX

t

BE

t

GLQX

t

EHQZ

t

BDO

t

GHQZ

t

AXOX

PARAMETER

NAME

t

RC

t

AA

t

ACS

(1)

t

BA

t

OE

t

CLZ

t

BE

t

OLZ

t

CHZ

t

BDO

t

OHZ

t

OH

DESCRIPTION

Read Cycle Time

Address Access Time

Chip Select Access Time

Data Byte Control Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Data Byte Control to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Data Byte Control to Output High Z

Output Disable to Output in High Z

Output Disable to Address Change

VDR 2.0V

≥

CE Vcc - 0.2V

Ω

o

C , Vcc = 5.0V )

(LB,UB)----35----30 ns

(LB,UB)10-- --10-- -- ns

(LB,UB) 0 -- 35 0 -- 30 ns

BS616LV4015

Vcc

t R

VIHVIH

KEY TO SWITCHING WAVEFORMS



WAVEFORM INPUTS OUTPUTS

MUST BE STEADY

MAY CHANGE FROM H TO L

MAY CHANGE FROM L TO H

,

DON T CAR ANY CHANG PERMITTED

DOES NOT APPLY

BS616LV4015-70

MIN. TYP. MAX.

E:

E

MIN. TYP. MAX.

70 -- -- 55 -- -- ns

-- -- 70 -- -- 55 ns

(CE) -- -- 70 -- -- 55 ns

-- -- 35 -- -- 30 ns

(CE) 10 -- -- 10 -- -- ns

10 -- -- 10 -- -- ns

(CE) 0 -- 35 0 -- 30 ns

0--300--25ns

10 -- -- 10 -- -- ns

MUST BE STEADY

WILL BE CHANGE FROM H TO L

WILL BE CHANGE FROM L TO H

CHANGE : STATE UNKNOWN

CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE

BS616LV4015-55

UNIT

NOTE :

1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle. ; tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle.

R0201-BS616LV4015

4

Revision 2.4 April 2002

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t AA

t OH

OUT

BS616LV4015

t RC

t OH

READ CYCLE2

CE

LB,UB

D

OUT

READ CYCLE3

ADDRESS

OE

(1,3,4)

(1,4)

t CLZ

t ACS

t BA

(5)

t BE

t BDO

t CHZ

t RC

t AA

t OE

t OH

CE

LB,UB

D

OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.

4. OE = V

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.

R0201-BS616LV4015

IL .

The parameter is guaranteed but not 100% tested.

t OLZ

(5)

t CLZ

(5)

t ACS

t OHZ

t CHZ

(1,5)

t BA

t BE

IL.

t BDO

±

5

Revision 2.4 April 2002

BSI

BS616LV4015

 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

o

C , Vcc = 5.0V )

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

BW

t

WLQZ

t

DVWH

t

WHDX

t

GHQZ

t

WHOX

NOTE :

1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.

PARAMETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR1

(1)

t

BW

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

DESCRIPTION

Write Cycle Time

Chip Select to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

Write recovery Time

Date Byte Control to End of Write

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

BS616LV4015-70

MIN. TYP. MAX.

BS616LV4015-55

MIN. TYP. MAX.

70 -- -- 55 -- -- ns

0 -- -- 0 -- -- ns

70 -- -- 55 -- -- ns

35 -- -- 30 -- -- ns

(CE,WE) 0 -- -- 0 -- -- ns

(LB,U ) 3B 0 -- -- 25 -- -- ns

0--300--25ns

30 -- -- 25 -- -- ns

0 -- -- 0 -- -- ns

0--300--25ns

5 -- -- 5 -- -- ns

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

t WC

UNIT

ADDRESS

OE

CE

LB,UB

WE

D

OUT

D

IN

t AS

(4,10)

t OHZ

(3)

t WR

(11)

(5)

t CW

t BW

t AW

t WP

(2)

(3)

t DH

t DW

R0201-BS616LV4015

6

Revision 2.4 April 2002

BSI

BS616LV4015

WRITE CYCLE2

ADDRESS

CE

LB,UB

WE

D

OUT

D

IN

(1,6)

t AS

(5)

t AW

(4,10)

t WHZ

t WC

t CW

t WP

t BW

(11)

t WR

(3)

(2)

t DH

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. T

WR is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

OUT is the same phase of write data of this write cycle.

7. D

OUT is the read data of next address.

8. D

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

The parameter is guaranteed but not 100% tested.

11. T

CW is measured from the later of CE going low to the end of write.

IL ).

±

L = 5pF as shown in Figure 1B.

R0201-BS616LV4015

7

Revision 2.4 April 2002

BSI

 ORDERING INFORMATION

BS616LV4015 X X -- Y Y

BS616LV4015

SPEED

70: 70ns 55: 55ns

GRADE

o

C: +0

C ~ +70oC

o

I: -40

C ~ +85oC

PACKAGE

E: TSOP 2 B: BGA - 48 PIN(8x10mm) A: BGA - 48 PIN(6x8mm) D: DICE

 PACKAGE DIMENSIONS

R0201-BS616LV4015

TSOP2-44

8

Revision 2.4 April 2002

BSI

 PACKAGE DIMENSIONS (continued)

0.05



0.25

BS616LV4015

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

1.4 Max.

e

VIEW A

SIDE VIEW

D0.1

D1

48 mini-BGA (8 x 10mm)

N ED

48 10.0 8.0

E1



E0.1

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.

3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

E1D1 e

3.755.25 0.75

SOLDER BALL 0.350.05

1.4 Max.

e

VIEW A

48 mini-BGA (6 x 8mm)

R0201-BS616LV4015

BALL PITCH e = 0.75

D

EN

8.0 6.0

D1

E1

48 3.75

9

E1D1

5.25

Revision 2.4 April 2002

BSI

BS616LV4015

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

2.3 Modify Standby Current (Typ. and Max.)

2.4 Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 25uA to 50uA.

Jun. 29, 2001

April,11,2002

R0201-BS616LV4015

10

Revision 2.4 April 2002