Datasheet BS616LV4010EI, BS616LV4010EC, BS616LV4010DI, BS616LV4010DC, BS616LV4010BI Datasheet (BSI)

BSI

Very Low Power/Voltage CMOS SRAM
256K X 16 bit

BS616LV4010

 FEATURES

• Very low operation voltage : 2.7 ~ 3.6V

• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current

I -grade: 25mA (Max.) operating current

0.5uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc = 3.0V

-10 100ns (Max.) at Vcc = 3.0V

•Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

 DESCRIPTION

The BS616LV4010 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.5uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616LV4010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4010 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-pin BGA package.

• I/O Configuration x8/x16 selectable by LB and UB pin

 PRODUCT FAMILY

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

( ns )

Vcc=3.0V Vcc=3.0V Vcc=3.0V

BS616LV4010DC DICE

SPEED

BS616LV4010EC
BS616LV4010AC

O

C to +70OC 2.7V ~ 3.6V 70 / 100 8uA 20mA

+0

BS616LV4010BC
BS616LV4010DI DICE
BS616LV4010EI
BS616LV4010AI

O

-40

C to +85OC 2.7V ~ 3.6V 70 / 100 12uA 25mA

BS616LV4010BI

POWER DISSIPATION

STANDBY

( ICCSB1, Max )

Operating

( ICC, Max )

PKG TYPE

TSOP2-44
BGA-48-0608
BGA-48-0810

TSOP2-44
BGA-48-0608
BGA-48-0810

 PIN CONFIGURATIONS

1

A4

2

A3

3

A2

4

A1

5

A0

6

CE

7

DQ0

8

DQ1

9

DQ2

10

DQ3
VCC

GND

DQ4
DQ5
DQ6
DQ7

WE
A17
A16
A15
A14
A13

BS616LV4010EC

11

BS616LV4010EI

12
13
14
15
16
17
18
19
20
21
22

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38

DQ15

37

DQ14

36

DQ13

35

DQ12

34

GND

33

VCC

32

DQ11

31

DQ10

30

DQ9

29

DQ8

28

NC

27

A8

26

A9

25

A10

24

A11

23

A12

 BLOCK DIAGRAM

A4
A3
A2

A1

Address

A0
A17

A16

A15
A14
A13
A12

DQ0

DQ15

CE

WE

UB

Vcc
Gnd

OE

LB

Input

Buffer

16

.

.

.

.

.

.
.

16

.

Control

22

Data
Input
Buffer

Data

Output

Buffer

Row

Decoder

2048

16

16

Memory Array

2048 x 2048

Column I/O

Write Driver

Sense Amp

Column Decoder

Address Input Buffer

A10

A11

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

128

A9 A8 A7

2048

14

A5

A6

R0201-BS616LV4010

1

Revision 2.3
April. 2002

BSI

 PIN DESCRIPTIONS

Name Function

BS616LV4010

A0-A17 Address Input

CE Chip Enable Input

WE Write Enable Input

OE Output Enable Input

LB and UB Data Byte Control Input

DQ0 - DQ15 Data Input/Output
Ports

Vcc

Gnd

 TRUTH TABLE

These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.

CE is active LOW. Chip enables must be active to read from or write to the device. if

chip enable is not active, the device is deselected and is in a standby power mode.

The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

Lower byte and upper byte data input/output control pins.

These 16 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

Ground

MODE CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT

Not selected

(Power Down)

H X X X X High Z High Z I

Output Disabled L H H X X High Z High Z I

L L Dout Dout I

Read L H L

H L High Z Dout I

L H Dout High Z I

L L Din Din I

Write L L X

H L X Din I

L H Din X I

R0201-BS616LV4010

2

, I

CCSB

CC

CC

CC

CC

CC

CC

CC

Revision 2.3
April. 2002

CCSB1

BSI

BS616LV4010

 ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL PARAM ETER RATING UNITS

V

T

T

P

I

TERM

BIAS

STG

T

OUT

Terminal Voltage with
Respect to GND

Temperature Under Bias -40 to +125

Storage Temperature -60 to +150

Power Dissipation 1.0 W

DC Output Current 20 mA

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

-0.5 to

Vcc+0.5

V

O

C

O

C

 DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

PARAMETER

NAME

IL

V

IH

V

IL

I

OL

I

OL

V

PARAMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage

Guaranteed Input High

(2)

Voltage

Input Leakage Current

Output Leakage Current

Vcc = Max, V

Vcc = Max, CE = V

I/O

= 0V to Vcc

V

Output Low Voltage = 2mAVcc = Max, I

IN = 0V to Vcc

OL

 OPERATING RANGE

RANGE

Commercial 0OC to +70OC2.7V ~ 3.6V

Industrial -40OC to +85OC2.7V ~ 3.6V

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

C

C

1. This parameter is guaranteed and not tested.

o

C )

, or OE = V

IH

IN

DQ

,

IH

Input
Capacitance
Input/Output
Capacitance

Vcc=3.0V

Vcc=3.0V

Vcc=3.0V

Vcc=3.0V

AMBIENT

TEMPERATURE

(1)

(TA = 25oC, f = 1.0 MHz)

VIN=0V 6 pF

I/O

V

=0V 8 pF

(1 )

MAX.

-0.5 -- 0.8 V

2.0 -- Vcc+0.2 V

-- -- 1 uA

-- -- 1 uA

-- -- 0.4 V

Vcc

UNITS

(3)

Vcc=3.0V

Vcc=3.0V

Vcc=3.0V

Vcc=3.0V

2.4 -- -- V

-- -- 20 mA

-- -- 1 mA

-- 0.5 8 uA

OH

V

CC

I

CCSB

I

CCSB1

I

Output High Voltage = -1mAVcc = Min, I

Operating Power Supply
Current

Standby Current-TTL

Standby Current-CMOS

IL

, IDQ= 0mA, F = Fmax

CE = V

IH

, IDQ= 0mACE = V

Њ

CE

Vcc-0.2V,

IN

Њ

V

Vcc - 0.2V or V

OH

0.2V

Љ

IN

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

 DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.

V

DR

I

CCDR

t

CDR

t

R

.

RC

Vcc for Data Retention

Data Retention Current

Chip Deselect to Data
Retention Time

Operation Recovery Time

CEЊVcc - 0.2V

IN

V

Њ

Vcc - 0.2V or V

IN

CEЊVcc - 0.2V

IN

V

Њ

Vcc - 0.2V or V

IN

See Retention Waveform

o

C )

Љ

Љ

0.2V

0.2V

(1)

MAX. UNITS

1.5 -- -- V

-- 0.3 1 uA

0--- n-s

(2)

T

RC

-- -- ns

1. Vcc = 1.5V, TA= + 25OC

= Read Cycle Time

2. t

RC

R0201-BS616LV4010

3

Revision 2.3
April. 2002

BSI

 LOW VCCDATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

≥

Vcc

CE

Vcc

t CDR

VDR 1.5V

≥

CE Vcc - 0.2V

BS616LV4010

Vcc

t R

VIHVIH

 AC TEST CONDITIONS

Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level

Vcc/0V
5ns

0.5Vcc

 AC TEST LOADS AND WAVEFORMS

3.3V

OUTPUT

INCLUDING
JIG AND
SCOPE

OUTPUT

Vcc

GND

Ω

1269

100PF

1404

FIGURE 1A

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

→

Ω

90%

←

FIGURE 2

3.3V

OUTPUT

Ω667

90%

→

INCLUDING
JIG AND
SCOPE

10%

← 5ns

1.73V

Ω

1269

5PF

1404

FIGURE 1B

Ω

 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

ELQV

t

BA

t

GLQV

t

ELQX

t

BE

t

GLQX

t

EHQZ

t

BDO

t

GHQZ

t

AXOX

PARAMETER

NAME

t

RC

t

AA

t

ACS

(1)

t

BA

t

OE

t

CLZ

t

BE

t

OLZ

t

CHZ

t

BDO

t

OHZ

t

OH

DESCRIPTION

Read Cycle Time

Address Access Time

Chip Select Access Time

Data Byte Control Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Data Byte Control to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Data Byte Control to Output High Z

Output Disable to Output in High Z

Output Disable to Address Change

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

MAY CHANGE
FROM L TO H

,

o

C , Vcc = 3.0V )

BS616LV4010-70

MIN. TYP. MAX.

DON T CAR
ANY CHANG
PERMITTED

DOES NOT
APPLY

E: CHANGE :

ESTATE

BS616LV4010-10

MIN. TYP. MAX.

70 -- -- 100 -- -- ns

-- -- 70 -- -- 100 ns

(CE) -- -- 70 -- -- 100 ns

(LB,UB) -- -- 35 -- -- 50 ns

-- -- 35 -- -- 50 ns

(CE) 10 -- -- 15 -- -- ns

(LB,UB) 10 -- -- 15 -- -- ns

10 -- -- 15 -- -- ns

(CE) 0 -- 35 0 -- 40 ns

(LB,UB) 0 -- 35 0 -- 40 ns

0--300--35 ns

10 -- -- 15 -- -- ns

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

WILL BE
CHANGE
FROM L TO H

UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE

UNIT

NOTE :

1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle.

R0201-BS616LV4010

4

Revision 2.3
April. 2002

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t AA

t OH

OUT

BS616LV4010

t RC

t OH

READ CYCLE2

CE

LB,UB

D

OUT

READ CYCLE3

ADDRESS

OE

(1,3,4)

(1,4)

t CLZ

t ACS

t BA

(5)

(5)

t BE

t BDO

t CHZ

t RC

t AA

t OE

t OH

CE

LB,UB

D

OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.

4. OE = V

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.

R0201-BS616LV4010

IL .

The parameter is guaranteed but not 100% tested.

t OLZ

(5)

t CLZ

(5)

t ACS

t OHZ

t CHZ

(1,5)

t BA

t BE

IL.

t BDO

±

5

Revision 2.3
April. 2002

BSI

BS616LV4010

 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

o

C , Vcc = 3.0V )

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

BW

t

WLQZ

t

DVWH

t

WHDX

t

GHQZ

t

WHOX

NOTE :

1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle.

PARAMETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR1

(1)

t

BW

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

DESCRIPTION

Write Cycle Time

Chip Select to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

Write recovery Time

Date Byte Control to End of Write

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

BS616LV4010-70

MIN. TYP. MAX.

70 -- -- 100 -- -- ns

70 -- -- 100 -- -- ns

0 -- -- 0 -- -- ns

70 -- -- 100 -- -- ns

35 -- -- 50 -- -- ns

(CE,WE) 0 -- -- 0 -- -- ns

(LB,U ) 30B ----40---- ns

0--300--40ns

30 -- -- 40 -- -- ns

0 -- -- 0 -- -- ns

0--300--40ns

5----10---- ns

BS616LV4010-10

MIN. TYP. MAX.

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

t WC

UNIT

ADDRESS

OE

CE

LB,UB

WE

D

OUT

D

IN

t AS

(4,10)

t OHZ

(3)

t WR

(11)

(5)

t CW

t BW

t AW

t WP

(2)

(3)

t DH

t DW

R0201-BS616LV4010

6

Revision 2.3
April. 2002

BSI

BS616LV4010

WRITE CYCLE2

ADDRESS

CE

LB,UB

WE

D

OUT

D

IN

(1,6)

t AS

(5)

(4,10)

t WHZ

t AW

t WC

t CW

t WP

t BW

(11)

t WR

(3)

(2)

t DH

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

3. T

WR is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

OUT is the same phase of write data of this write cycle.

7. D

OUT is the read data of next address.

8. D

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

The parameter is guaranteed but not 100% tested.

11. T

CW is measured from the later of CE going low to the end of write.

IL ).

±

L = 5pF as shown in Figure 1B.

R0201-BS616LV4010

7

Revision 2.3
April. 2002

BSI

 ORDERING INFORMATION

BS616LV4010 X X -- Y Y

BS616LV4010

SPEED

70: 70ns
10: 100ns

GRADE

o

C: +0

C ~ +70oC

o

I: -40

C ~ +85oC

PACKAGE

E: TSOP 2
A: BGA - 48 PIN(6x8mm)
B: BGA - 48 PIN(8x10mm)
D: DICE

 PACKAGE DIMENSIONS

R0201-BS616LV4010

TSOP2-44

8

Revision 2.3
April. 2002

BSI

 PACKAGE DIMENSIONS (continued)

1.4 Max.

D1

e

VIEW A

BS616LV4010

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.

3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

BALL PITCH e = 0.75

D

EN

8.0 6.0

E1

48 3.75

E1D1

5.25

48 mini-BGA (6 x 8mm)

1.4 Max.

e

VIEW A

SIDE VIEW

D0.1

D1

0.05



0.25

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

N ED

48 10.0 8.0

E1



E0.1

E1D1 e

3.755.25 0.75

SOLDER BALL 0.350.05

48 mini-BGA (8 x 10mm)

R0201-BS616LV4010

9

Revision 2.3
April. 2002

BSI

BS616LV4010

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

2.3 Modify some AC parameters April,11,2002

R0201-BS616LV4010

10

Revision 2.3
April. 2002