Datasheet BS616LV2013TI, BS616LV2013TC, BS616LV2013EI, BS616LV2013EC, BS616LV2013DI Datasheet (BSI)

BSI

Very Low Power/Voltage CMOS SRAM 128K X 16 bit

BS616LV2013

 FEATURES

• Very low operation voltage : 2.4 ~ 3.6V

• Very low power consumption : Vcc = 3.0V C-grade: 20mA (Max.) operating current

I -grade: 25mA (Max.) operating current

0.1uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc = 3.0V

-10 100ns (Max.) at Vcc = 3.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

• I/O Configuration x8/x16 selectable by LB and UB pin

 DESCRIPTION

The BS616LV2013 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 words by 16 bits and operates from a wide range of 2.4V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.1uA and maximum access time of 70/100ns in 3V operation. Easy memory expansion is provided by active LOW chip enable(CE), active LOW output enable(OE) and three-state output drivers. The BS616LV2013 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV2013 is available in DICE form, JEDEC standard 44-pin TSOP Type II package , JEDEC standard 48-pin TSOP Type I package and 48-ball BGA package.

 PRODUCT FAMILY

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

( ns )

Vcc=3.0V Vcc=3.0V Vcc=3.0V

BS616LV2013DC DICE

SPEED

BS616LV2013EC TSOP2-44 BS616LV2013TC TSOP1-48

O

C to +70OC2.4+0 V ~3.6V 70/100 0.7uA 20mA

BS616LV2013AC BS616LV2013DI DICE BS616LV2013EI TSOP2-44 BS616LV2013TI TSOP1-48

O

-40

C to +85OC 2.4V ~ 3.6V 70/100 1.5uA 25mA

BS616LV2013AI

 PIN CONFIGURATIONS

1

A4

2

A3

3

A2

4

A1

5

A0

6

CE

7

DQ0

8

DQ1

9

DQ2

10

DQ3 VCC GND DQ4 DQ5 DQ6 DQ7

WE A16 A15 A14 A13 A12

A

B

C

VSS

D

VCC

E

F

D14D9D13

BS616LV2013EC

11 12

BS616LV2013EI

13 14 15 16 17 18 19 20 21 22

23

LB1OE A0

D8 UB

D10 A5

D11

D12

A3

N.C.

A14

A16A7D4

A15 D5

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38

DQ15

37

DQ14

36

DQ13

35

DQ12

34

GND

33

VCC

32

DQ11

31

DQ10

30

DQ9

29

DQ8

28

NC

27

A8

26

A9

25

A10

24

A11

23

NC

456

A1 A2

A4

A6 D1

N.C.

D0

CE

D2

D3

VCC

VSS

D6

 BLOCK DIAGRAM

A8 A13

A15

A16 A14

A12

A7

A6 A5 A4

DQ0

. . . .

DQ15

CE

WE

OE

UB

LB

Vcc Gnd

POWER DISSIPATION

STANDBY

CCSB1

( I

, Max )

Address

20

Input

Buffer

16

. . .

16

.

Control

Data Input Buffer

Data

Output

Buffer

Row

Decoder

Operating

( ICC, Max )

1024

16

A11

Memory Array

1024 x 2048

2048

Column I/O

Write Driver

Sense Amp

128

Column Decoder

14

Address Input Buffer

A9

A3 A2 A1

BGA-48-0608

A0

PKG TYPE

A10

G

D15

N.C.

H

A12

A13 WE

A9A8

D7

N.C.

A11A10

48-ball BGA top view

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS616LV2013

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Revision 2.5 April 2002

BSI

 PIN DESCRIPTIONS

Name Function

BS616LV2013

A0-A16 Address Input

CE Chip Enable Input

WE Write Enable Input

OE Output Enable Input

LB and UB Data Byte Control Input

DQ0 - DQ15 Data Input/Output Ports

Vcc

Gnd

 TRUTH TABLE

These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.

CE is active LOW. Chip enables must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

Lower byte and upper byte data input/output control pins.

These 16 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

Ground

MODE CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT

Not selected

(Power Down

HXXXX High Z High Z I

)

Output Disabled L H H X X High Z High Z I

L L Dout Dout I

Read L H L

H L High Z Dout I

L H Dout High Z I

LL Din Din I

Write L L X

HL X Din I

LH Din X I

R0201-BS616LV2013

2

CCSB

, I

B1

CCS

CC

Revision 2.5 April 2002

BSI

 ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNITS

TERM

V

BIAS

T

STG

T

P

OUT

I

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Terminal Voltage with Respect to GND

Temperature Under Bias C-40 to +125

Storage Temperature C-60 to +150

Power Dissipation 1.0 W

DC Output Current 20 mA

(1)

-0.5 to

Vcc+0.5

V

O

BS616LV2013

 OPERATING RANGE

RANGE

Commercial 0OC to +70OC2.4V ~ 3.6V

Industrial -40OC to +85OC2.4V ~ 3.6V

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

Input

IN

C

1. This parameter is guaranteed and not tested.

DQ

Capacitance Input/Output Capacitance

AMBIENT

TEMPERATURE

(1)

(TA = 25oC, f = 1.0 MHz)

VIN=0V 6 pF

I/O

V

=0V 8 pF

Vcc

 DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

PARAMETER

NAME

IL

V

IH

V

IL

I

OL

I

OL

V

OH

V

CC

I

CCSB

I

CCSB1

I

PARAMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(2)

Voltage Guaranteed Input High

(2)

Voltage

Input Leakage Current Vcc = Max, V

Output Leakage Current

Vcc = Max, CE = V

I/O

= 0V to Vcc

V

Output Low Voltage Vcc = Max, IOL = 2mA

Output High Voltage Vcc = Min, IOH = -1mA

Operating Power Supply Current

CE = V

Standby Current-TTL CE = VIH, IDQ = 0mA

Standby Current-CMOS

CE Њ Vcc-0.2V,

IN

Њ

V

IN

= 0V to Vcc -- -- 1 uA

IL

, IDQ = 0mA, F = Fmax

Vcc - 0.2V or V

o

C )

IH

, or OE = VIH,

IN

Љ

0.2V

(1)

MAX.

Vcc=3.0V

-0.5 -- 0.8 V

2.0 -- Vcc+0.2 V

-- -- 1 uA

Vcc=3.0V

(3)

Vcc=3.0V

-- -- 0.4 V

2.4 -- -- V

-- -- 20 mA

-- -- 1 mA

-- 0.1 0.7 uA

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

 DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70

SYMBOL PARAM ETE R TEST CONDITIONS MIN. TYP.

V

I

CCDR

t

CDR

t

.

RC

o

C )

(1)

MAX. UNITS

DR

Vcc for Data Retention

Data Retention Current

CE Њ Vcc - 0.2V V

IN Њ Vcc - 0.2V or VIN Љ 0.2V

CE Њ Vcc - 0.2V

IN

Њ Vcc - 0.2V or VINЉ 0.2V

V

Chip Deselect to Data Retention Time

R

Operation Recovery Time

See Retention Waveform

1.5 -- -- V

-- 0.05 0.5 uA

0 -- -- ns

(2)

T

RC

-- -- ns

1. Vcc = 1.5V, TA= + 25OC = Read Cycle Time

2. t

RC

UNITS

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Revision 2.5 April 2002

BSI

 LOW VCCDATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

≥

Vcc

CE

Vcc

t CDR

VDR 1.5V

≥

CE Vcc - 0.2V

BS616LV2013

Vcc

t R

VIHVIH

 AC TEST CONDITIONS

Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level

Vcc/0V 5ns

0.5Vcc

 AC TEST LOADS AND WAVEFORMS

3.3V

OUTPUT

INCLUDING JIG AND SCOPE

OUTPUT

Vcc

GND

Ω

1269

100PF

Ω

1404

FIGURE 1A

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

→

90%

←

FIGURE 2

3.3V

OUTPUT

INCLUDING JIG AND SCOPE

Ω667

90%

→

1.73V

10%

← 5ns

Ω

1269

5PF

1404

FIGURE 1B

 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

ELQV

t

BA

t

GLQV

t

E1LQX

t

BE

t

GLQX

t

EHQZ

t

BDO

t

GHQZ

t

AXOX

PARAMETER

NAME

t

RC

t

AA

t

ACS

(1)

t

BA

t

OE

t

CLZ

t

BE

t

OLZ

t

CHZ

t

BDO

t

OHZ

t

OH

DESCRIPTION

Read Cycle Time

Address Access Time

Chip Select Access Time

Data Byte Control Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Data Byte Control to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Data Byte Control to Output High Z

Output Disable to Output in High Z

Output Disable to Address Change

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

MUST BE STEADY

MAY CHANGE FROM H TO L

MAY CHANGE FROM L TO H

,

Ω

o

C , Vcc = 3.0V )

BS616LV2013-70

MIN. TYP. MAX.

DON T CAR ANY CHANG PERMITTED

DOES NOT APPLY

70 -- -- 100 -- -- ns

-- -- 70 -- -- 100 ns

(CE) -- -- 70 -- -- 100 ns

(LB,U ) -B - -- 35 -- -- 50 ns

-- -- 35 -- -- 50 ns

(CE) 10 -- -- 15 -- -- ns

(LB,U ) 1B 0 -- -- 15 -- -- ns

10 -- -- 15 -- -- ns

(CE) 0 -- 35 0 -- 40 ns

(LB,UB) 0 -- 35 0 -- 40 ns

0--300--35 ns

10 -- -- 15 -- -- ns

E: CHANGE :

E STATE

BS616LV2013-10

MIN. TYP. MAX.

MUST BE STEADY

WILL BE CHANGE FROM H TO L

WILL BE CHANGE FROM L TO H

UNKNOWN

CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE

UNIT

NOTE :

1. tBAis 35ns/50ns (@speed=70ns/100ns) with address toggle. ; .tBAis 70ns/100ns (@speed=70ns/100ns) without address toggle.

R0201-BS616LV2013

4

Revision 2.5 April 2002

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t AA

t OH

OUT

BS616LV2013

t RC

t OH

READ CYCLE2

CE

LB,UB

D

OUT

READ CYCLE3

ADDRESS

OE

(1,3,4)

(1,4)

t CLZ

t ACS

t BA

(5)

t BE

t BDO

t CHZ

t RC

t AA

t OE

t OH

CE

LB,UB

D

OUT

NOTES:

1. WE is high for read Cycle.

2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.

4. OE = V

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.

R0201-BS616LV2013

IL .

The parameter is guaranteed but not 100% tested.

t OLZ

(5)

t CLZ

(5)

t ACS

t OHZ

t CHZ

(1,5)

t BA

t BE

IL.

t BDO

±

5

Revision 2.5 April 2002

BSI

 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

o

C , Vcc = 3.0V )

BS616LV2013

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

BW

t

WLQZ

t

DVWH

t

WHDX

t

GHQZ

t

WHOX

NOTE :

1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle.

PARAMETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR

(1)

t

BW

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

DESCRIPTION

Write Cycle Time

Chip Select to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

Write recovery Time

Date Byte Control to End of Write

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

BS616LV2013-70

MIN. TYP. MAX.

70 -- -- 100 -- -- ns

0 -- -- 0 -- -- ns

70 -- -- 100 -- -- ns

35 -- -- 50 -- -- ns

(CE,WE) 0 -- -- 0 -- -- ns

(LB,U ) 30B ----40---- ns

0--300--40ns

30 -- -- 40 -- -- ns

0 -- -- 0 -- -- ns

0--300--40ns

5----10---- ns

BS616LV2013-10

MIN. TYP. MAX.

UNIT

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

ADDRESS

OE

CE

LB,UB

WE

(1)

(5)

t AS

(4,10)

t OHZ

D

OUT

t AW

t WC

t CW

t WP

(11)

t BW

(3)

t WR

(3)

(2)

t DH

t DW

D

IN

R0201-BS616LV2013

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Revision 2.5 April 2002

BSI

BS616LV2013

WRITE CYCLE2

ADDRESS

CE

LB,UB

WE

D

OUT

D

IN

(1,6)

t AS

(5)

t AW

(4,10)

t WHZ

t WC

t CW

t WP

t BW

(11)

t WR

(3)

(2)

t DH

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. T

WR is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

OUT is the same phase of write data of this write cycle.

7. D

OUT is the read data of next address.

8. D

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

11. T

CW is measured from the later of CE going low to the end of write.

IL ).

±

R0201-BS616LV2013

7

Revision 2.5 April 2002

BSI

 ORDERING INFORMATION

BS616LV2013 X X -- Y Y

BS616LV2013

SPEED

70: 70ns 10: 100ns

GRADE

o

C: +0

C ~ +70oC

o

I: -40

C ~ +85oC

PACKAGE

T: TSOP 1 - 48 PIN E: TSOP 2 - 44 PIN A: BGA - 48 PIN(6x8mm) D: DICE

 PACKAGE DIMENSIONS

R0201-BS616LV2013

TSOP2-44

8

Revision 2.5 April 2002

BSI

 PACKAGE DIMENSIONS

1

24

1

BS616LV2013

12(2x)

SYMBOL

UNIT

A A1 A2 b b1 c c1 D E e HD L L1 y

Ӱ

A

L

L1

0.04330.004

0.0040.002

0.0390.002

0.0090.002

0.0080.001

0.004 ~ 0.008

0.004 ~ 0.006

0.6450.004

0.4720.004

0.0200.004

0.7080.008

0.02360.006

0.03150.004

0.004 Max. 0~ 8

GAUGE PLANE

0

0.254

MMINCH

1.100.10

0.100.05

1.000.05

0.220.05

0.200.03

0.10 ~ 0.21

0.10 ~ 0.16

16.400.10

12.000.10

0.500.10

18.000.20

0.600.15

0.800.10

0.1 Max. 0~ 8

HD

C L

48

25

D

"A"

25

48

12(2X)

WITH PLATING

c

BASE METAL

12(2X)

e

b

E

Seating Plane

c1

y

A

b

b1

SECTION A-A

A2

A1

SEATING PLANE

"A" DETAIL VIEW

12(2x)

TSOP1-48PIN

1

A15

A14

A13

A12

A11

A10

A9 A8

9

NC

10

NC /WE CE2

13

NC

/UB /LB

NC

16 17

NC

A7

A6

A5

A4

A3

A2

24

A1

Pkg Type :

48TSOP(I)-12x18mm

A16

48 47

NC VSS

46

IO15 IO7 IO14 IO6 IO13 IO5 IO12 IO4 VCC

37

IO11 IO3 IO10 IO2 IO9 IO1 IO8 IO0 /OE

27

VSS /CE

25

A0

R0201-BS616LV2013

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Revision 2.5 April 2002

BSI

 PACKAGE DIMENSIONS (continued)

1.4 Max.

D1

e

VIEW A

BS616LV2013

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.

3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

BALL PITCH e = 0.75

D

EN

8.0 6.0

E1

48 3.75

E1D1

5.25

48 mini-BGA (6 x 8)

R0201-BS616LV2013

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Revision 2.5 April 2002

BS616LV2013

BSI

REVISION HISTORY

Revision Description Date Note

2.2 2001 Data Sheet release Apr. 15, 2001

2.3 Modify Standby Current (Typ. and Max.)

2.4 Modify CSP Pin Configuration Pin number : E3 “ VSS ” rename to “ N.C. “

2.5 Modify some AC parameters April,12,2002

Jun. 29, 2001

Sep.12, 2001

R0201-BS616LV2013

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Revision 2.5 April 2002