Page 1
BSI
Very Low Power/Voltage
64K X 16 bit
CMOS SRAM
BS616LV1010
FEATURES
• Very low operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
DESCRIPTION
The BS616LV1010 is a high performance, very low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616LV1010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1010 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin BGA package.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V Vcc=3.0V
BS616LV1010EC TSOP2-44
+0
O
C to +70
O
C 2.4V ~ 5.5V 70 3uA 0.5uA 35mA 20mA
BS616LV1010AC
BS616LV1010EI TSOP2-44
BS616LV1010AI
PIN CONFIGURATIONS
1
A4
2
A3
3
A2
4
A1
5
A0
6
CE
7
DQ0
8
DQ1
9
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A15
A14
A13
A12
NC
A
B
C
D
E
F
G
BS616LV1010EC
10
11
BS616LV1010EI
12
13
14
15
16
17
18
19
20
21
22
12345
IO8LBUBOEA3
IO9
IO10
VSS
IO11
VCC
IO12
IO14
IO13 A14
IO15 NC A12
-40
A0
A5
NC
NC
A15 IO5
A13 WE IO7
O
C to +85
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4A1CEA2IO0
A6
IO1
A7
IO3
NC
IO4
O
C 2.4V ~ 5.5V 70 5uA 1.5uA 40mA 25mA
BLOCK DIAGRAM
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
6
NC
IO2
VCC
VSS
IO6
POWER DISSIPATION
STANDBY
(I
, Max)
CCSB1
A8
A13
A15
A14
A12
DQ0
DQ15
Vcc
Gnd
Address
Input
Buffer
A7
A6
A5
A4
.
.
.
.
.
.
.
.
CE
WE
OE
UB
LB
Control
Operating
(ICC, Max)
PKG TYPE
BGA-48-0608
BGA-48-0608
18
16
16
Data
Input
Buffer
Data
Output
Buffer
Row
Decoder
512
16
16
Memory Array
512 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
A9
A3 A2 A1
A11
2048
128
14
A10
A0
H
A9A8NC
NCA11A10
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV1010
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Revision 2.2
April 2001
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BSI
PIN DESCRIPTIONS
Name Function
BS616LV1010
A0-A15 Address Input
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
Vcc
Gnd
TRUTH TABLE
These 16 address inputs select one of the 65,536 x 16-bit words in the RAM.
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
MODE CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT
Not selected
(Power Down)
H X X X X High Z High Z I
Output Disabled L H H X X High Z High Z I
L L Dout Dout I
Read L H L
H L High Z Dout I
L H Dout High Z I
L L Din Din I
Write L L X
H L X Din I
L H Din X I
R0201-BS616LV1010
2
CCSB
, I
CCSB1
CC
CC
CC
CC
CC
CC
CC
Revision 2.2
April 2001
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BSI
BS616LV1010
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL PARAMETE R RATING UNITS
V
T
T
P
I
TERM
BIAS
STG
T
OUT
Terminal Voltage with
Respect to GND
Temperature Under Bias -40 to +125
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current 20 mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS ( TA = 0
PARAMETER
NAME
IL
V
IH
V
IL
I
IOL Output Leakage Current
VOL Output Low Voltage Vcc = Max, IOL = 2mA
VOH Output High Voltage Vcc = Min, IOH = -1mA
CC
I
CCSB
I
Standby Current-TTL CE = VIH, IDQ = 0mA
CCSB1
I
Standby Current-CMOS
PARAMETER TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current Vcc = Max, V
Operating Power Supply
Current
-0.5 to
Vcc+0.5
V
O
C
O
C
o
C to + 70oC )
IN
= 0V to Vcc -- -- 1 uA
Vcc = Max, CE = V
I/O
V
= 0V to Vcc
IL
CE = V
, IDQ = 0mA, F = Fmax
CE Њ Vcc-0.2V,
IN
Њ Vcc - 0.2V or VINЉ 0.2V
V
OPERATING RANGE
RANGE
Commercial 0
Industrial -40
CAPACITANCE
SYMBOL PARAMETER CONDITIONS MAX. UNIT
C
C
1. This parameter is guaranteed and not tested.
IH
, or OE = VIH,
IN
DQ
(3)
Input
Capacitance
Input/Output
Capacitance
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
AMBIENT
TEMPERATURE
O
C to +70
O
(1)
-0.5 -- 0.8 V
2.0
2.2
2.4 -- -- V
O
C2.4V ~ 5.5V
C to +85
O
C2.4V ~ 5.5V
(TA = 25oC, f = 1.0 MHz)
VIN=0V 6 pF
I/O
V
=0V 8 pF
(1)
MAX.
-- Vcc+0.2 V
-- -- 1 uA
-- -- 0.4 V
-- -- 20
-- -- 35
-- -- 1
-- -- 2
-- 0.02 0.5
-- 0.4 3
Vcc
UNITS
mA
mA
uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
DATA RETENTION CHARACTERISTICS ( TA = 0
SYMBOL PAR AMETE R TEST CONDITIONS MIN. TYP.
V
I
CCDR
t
CDR
t
.
RC
o
C to + 70oC )
(1)
MAX. UNITS
DR
Vcc for Data Retention
Data Retention Current
CE Њ Vcc - 0.2V
Њ
IN
Vcc - 0.2V or V
V
CE Њ Vcc - 0.2V
Њ
IN
Vcc - 0.2V or V
V
Љ
IN
0.2V
Љ
IN
0.2V
Chip Deselect to Data
Retention Time
R
Operation Recovery Time
See Retention Waveform
1.5 -- -- V
-- 0.02 0.3 uA
0---- ns
(2)
T
RC
-- -- ns
1. Vcc = 1.5V, TA= + 25OC
2. t
= Read Cycle Time
RC
R0201-BS616LV1010
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Revision 2.2
April 2001
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BSI
LOW VCCDATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
≥
Vcc
CE
Vcc
t CDR
VDR 1.5V
≥
CE Vcc - 0.2V
BS616LV1010
Vcc
t R
VIHVIH
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
OUTPUT
Vcc
GND
Ω
1269
100PF
1404
FIGURE 1A
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
→
Ω
90%
←
FIGURE 2
3.3V
OUTPUT
Ω667
90%
→
INCLUDING
JIG AND
SCOPE
10%
←
1269
5PF
FIGURE 1B
1.73V
5ns
AC ELECTRICAL CHARACTERISTICS ( TA = 0
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
E1HQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Output Disable to Output Address Change
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
Ω
Ω
1404
o
C to + 70oC, Vcc = 3.0V )
DESCRIPTION
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CAR
ANY CHANG
PERMITTED
DOES NOT
APPLY
BS616LV1010-70
MIN. TYP. MAX.
E: CHANGE :
E STATE
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
UNIT
70 -- -- ns
-- -- 70 ns
(CE) -- -- 70 ns
(LB,UB) -- -- 40 ns
-- -- 50 ns
(CE) 10 -- -- ns
(LB,UB) 10 -- -- ns
10 -- -- ns
(CE) 0 -- 35 ns
(LB,UB) 0 -- 30 ns
0--30 ns
10 -- -- ns
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Revision 2.2
April 2001
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BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
(1,2,4)
t AA
t OH
OUT
BS616LV1010
t RC
t OH
READ CYCLE2
CE
LB,UB
D
OUT
READ CYCLE3
ADDRESS
OE
(1,3,4)
(1,4)
t CLZ
t ACS
t BA
(5)
(5)
t BE
t RC
t BDO
t CHZ
t AA
t OE
t OH
CE
LB,UB
D
OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = V
3. Address valid prior to or coincident with CE transition low.
4. OE = V
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
R0201-BS616LV1010
IL .
The parameter is guaranteed but not 100% tested.
t OLZ
(5)
t CLZ
(5)
t ACS
t OHZ
t CHZ
(1,5)
t BA
t BE
IL.
t BDO
±
5
Revision 2.2
April 2001
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BSI
BS616LV1010
AC ELECTRICAL CHARACTERISTICS ( TA = 0
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
BW
t
WLQZ
t
DVWH
t
WHDX
t
GHQZ
t
WHOX
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
BW
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write recovery Time
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
o
C to + 70oC, Vcc = 3.0V )
BS616LV1010-70
MIN. TYP. MAX.
70 -- -- ns
70 -- -- ns
0---- ns
70 -- -- ns
50 -- -- ns
(CE,WE) 0 -- -- ns
(LB,UB) 60 -- -- ns
0--30ns
30 -- -- ns
0---- ns
0--30ns
5---- ns
t WC
UNIT
ADDRESS
OE
CE
LB,UB
WE
D
OUT
D
IN
t AS
(4,10)
t OHZ
(3)
t WR
(11)
(5)
t CW
t BW
t AW
t WP
(2)
(3)
t DH
t DW
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Revision 2.2
April 2001
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BSI
BS616LV1010
WRITE CYCLE2
ADDRESS
CE
LB,UB
WE
D
OUT
D
IN
(1,6)
t AS
(5)
(4,10)
t WHZ
t AW
(12)
t WC
t CW
t WP
t BW
(11)
t WR
(3)
(2)
t DH
(7) (8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
WR is measured from the earlier of CE or WE going high at the end of write cycle.
3. T
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
OUT is the same phase of write data of this write cycle.
7. D
OUT is the read data of next address.
8. D
9. If CE goes low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
The parameter is guaranteed but not 100% tested.
CW is measured from the later of CE going low to the end of write.
11. T
12. The change of Read/Write cycle must accompany with CE or address toggled.
IL ).
±
L = 5pF as shown in Figure 1B.
R0201-BS616LV1010
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Revision 2.2
April 2001
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BSI
ORDERING INFORMATION
BS616LV1010 X X -- Y Y
BS616LV1010
SPEED
70: 70ns
GRADE
C: +0oC ~ +70oC
o
C ~ +85oC
I: -40
PACKAGE
E: TSOP II - 44 PIN
A: BGA - 48 PIN(6x8mm)
PACKAGE DIMENSIONS
R0201-BS616LV1010
TSOP2-44
8
Revision 2.2
April 2001
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BSI
PACKAGE DIMENSIONS (continued)
1.4 Max.
D1
e
VIEW A
BS616LV1010
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
EN
8.0 6.0
E1
48 3.75
E1D1
5.25
48 mini-BGA (6 x 8)
R0201-BS616LV1010
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Revision 2.2
April 2001
Page 10
BSI
BS616LV1010
REVISION HISTORY
Revision Description Date Note
2.2 2001 Data Sheet release Apr. 15, 2001
R0201-BS616LV1010
10
Revision 2.2
April 2001
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